HITACHI HN29W12811

HN29W12811 Series
128M AND type Flash Memory
More than 8,029-sector (135,657,984-bit)
ADE-203-1183C (Z)
Rev. 2.0
Feb. 7, 2001
Description
The Hitachi HN29W12811 Series is a CMOS Flash Memory with AND type multi-level memory cells. It has
fully automatic programming and erase capabilities with a single 3.3 V power supply. The functions are
controlled by simple external commands. To fit the I/O card applications, the unit of programming and erase
is as small as (2048 + 64) bytes. Initial available sectors of HN29W12811 are more than 8,029 (98% of all
sector address).
Features
• On-board single power supply (VCC): VCC = 3.3 V ± 0.3 V
• Organization
 AND Flash Memory: (2048 + 64) bytes × (More than 8,029 sectors)
 Data register: (2048 + 64) bytes
• Multi-level memory cell
 2 bit/per memory cell
• Automatic programming
 Sector program time: 2.5 ms (typ)
 System bus free
 Address, data latch function
 Internal automatic program verify function
 Status data polling function
• Automatic erase
 Single sector erase time: 1.0 ms (typ)
 System bus free
 Internal automatic erase verify function
 Status data polling function
HN29W12811 Series
• Erase mode
 Single sector erase ((2048 + 64) byte unit)
• Fast serial read access time:
 First access time: 50 µs (max)
 Serial access time: 60 ns (max)
• Low power dissipation:
 ICC2 = 40 mA (max) (Read)
 ISB2 = 50 µA (max) (Standby)
 ICC3/ICC4 = 40 mA (max) (Erase/Program)
 ISB3 = 5 µA (max) (Deep standby)
• The following architecture is required for data reliability.
 Error correction: more than 1-bit error correction per each sector read
 Spare sectors: 1.8% (145 sectors) within usable sectors
Ordering Information
Type No.
Available sector
Package
HN29W12811T-60
More than 8,029 sectors
12.0 × 18.40 mm 2 0.5 mm pitch
48-pin plastic TSOP I (TFP-48DA)
2
HN29W12811 Series
Pin Arrangement
48-pin TSOP
VCC
VSS
VSS
VSS
VSS
RES
RDY/Busy
SC
OE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
CDE
WE
CE
VSS
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
(Top view)
Pin Description
Pin name
Function
I/O0 to I/O7
Input/output
CE
Chip enable
OE
Output enable
WE
Write enable
CDE
Command data enable
VCC*
1
Power supply
VSS *
1
Ground
RDY/Busy
Ready/Busy
RES
Reset
SC
Serial clock
Note:
1. All V CC and VSS pins should be connected to a common power supply and a ground, respectively.
3
HN29W12811 Series
Block Diagram
Sector
address
buffer
X-decoder
8192 × (2048 + 64) × 8
memory matrix
Data register (2048 + 64)
••
I/O0
to
I/O7
•
•
8029 - 8192
2048 + 64
•
Multiplexer •
Data
input
buffer
•
•
Input
data
control
•
•
Y-gating
Data
output
buffer
Y-decoder
RDY/Busy
••
•••
•
•
VCC
Y-address
counter
VSS
CE
OE
WE
SC
RES
CDE
4
Control
signal
buffer
Read/Program/Erase control
HN29W12811 Series
Memory Map and Address
Sector address
2048 bytes
64 bytes
2048 bytes
64 bytes
2048 bytes
64 bytes
2048 bytes
64 bytes
2048 bytes
64 bytes
2048 bytes
64 bytes
1FFFH
1FFEH
8029 - 8192 sectors *1
1FFDH
0002H
0001H
0000H
800H
000H
83FH Column address
2048 + 64 bytes
Control bytes
Cycles
SA (1):
SA (2):
Column address CA (1):
CA (2):
Address
Sector address
First cycle
Second cycle
First cycle
Second cycle
I/O0 I/O1 I/O2 I/O3
A0 A1 A2 A3
A8 A9 A10 A11
A0 A1 A2 A3
A8 A9 A10 A11
I/O4 I/O5 I/O6 I/O7
A4 A5 A6 A7
A12 ×*2
×
×
A4 A5 A6 A7
×
×
×
×
Notes: 1. Some failed sectors may exist in the device. The failed sectors can be recognized
by reading the sector valid data written in a part of the column address 800 to 83F
(The specific address is TBD.). The sector valid data must be read and kept outside
of the sector before the sector erase. When the sector is programmed, the sector
valid data should be written back to the sector.
2. An × means "Don't care". The pin level can be set to either VIL or VIH, referred
to DC characteristics.
5
HN29W12811 Series
Pin Function
CE: CE is used to select the device. The status returns to the standby at the rising edge of CE in the reading
operation. However, the status does not return to the standby at the rising edge of CE in the busy state in
programming and erase operation.
OE: Memory data and status register data can be read, when OE is VIL .
WE: Commands and address are latched at the rising edge of WE.
SC: Programming and reading data is latched at the rising edge of SC.
RES: RES pin must be kept at the VILR (V SS ± 0.2 V) level when VCC is turned on and off. In this way, data
in the memory is protected against unintentional erase and programming. RES must be kept at the VIHR (VCC
± 0.2 V) level during any operations such as programming, erase and read.
CDE: Commands and data are latched when CDE is VIL and address is latched when CDE is VIH.
RDY/Busy: The RDY/Busy indicates the program/erase status of the flash memory. The RDY/Busy signal
is initially at a high impedance state. It turns to a VO L level after the (40H) command in programming
operation or the (B0H) command in erase operation. After the erase or programming operation finishes, the
RDY/Busy signal turns back to the high impedance state.
I/O0 to I/O7: The I/O pins are used to input data, address and command, and are used to output memory data
and status register data.
Mode Selection
Mode
CE
OE
WE
SC
RES
CDE
RDY/Busy* 3 I/O0 to I/O7
Deep standby
×* 4
×
×
×
VILR
×
VOH
High-Z
Standby
VIH
×
×
×
VIHR
×
VOH
High-Z
VIL
VIH
VIH
×
VIHR
×
VOH
High-Z
VIL
VIL
VIH
×
VIHR
×
VOH
Status register outputs
VIL
VIH
VIL
VIL
VIHR
VIL
VOH
Din
Output disable
1
Status register read*
2
Command write*
Notes: 1. Default mode after the power on is the status register read mode (refer to status transition). From
I/O0 to I/O7 pins output the status, when CE = VIL and OE = VIL (conventional read operation
condition).
2. Refer to the command definition. Data can be read, programmed and erased after commands are
written in this mode.
3. The RDY/Busy bus should be pulled up to VCC to maintain the VOH level while the RDY/Busy pin
outputs a high impedance.
4. An × means “Don’t care”. The pin level can be set to either VIL or VIH referred to DC characteristics.
6
HN29W12811 Series
Command Definition*1, 2
First bus cycle
Second bus cycle
Operation Data in
mode*3
Operation Data in
mode
Write
00H
Write
SA (1)*4
3 + 2h*6 Write
00H
Write
SA (1)*4
Serial read (2)
3
Write
F0H
Write
SA (1)*4
Read identifier codes
1
Write
90H
Read
ID*8, 9
Data recovery read
1
Write
01H
Read
Recovery
data
Single sector
4
Write
20H
Write
SA (1)*4
(Without
CA*7)
4
Write
10H
Write
SA (1)*4
(With CA*7)
4 + 2h*6 Write
10H
Write
SA (1)*4
4
Write
1FH
Write
SA (1)*4
Program (3) (Control bytes)*7 4
Write
0FH
Write
SA (1)*4
(WithoutCA*7) 4
Write
11H
Write
SA (1)*4
4 + 2h*6 Write
11H
Write
SA (1)*4
Reset
1
Write
FFH
Clear status register
1
Write
50H
Data recovery write
4
Write
12H
Write
SA (1)*4
Bus
cycles
Command
Read
Serial read (1) (Without CA) 3
(With CA)
Auto erase
Auto program Program (1)
Program (2)*10
Program (4)
(With CA*7)
Data out
7
HN29W12811 Series
Third bus cycle
Fourth bus cycle
Operation
mode
Data in
Operation
mode
Data in
Write
SA (2)*4
3 + 2h*6 Write
SA (2)*4
Write
CA (1)*5
Serial read (2)
3
Write
SA (2)*4
Read identifier codes
1
Data recovery read
1
Single sector
4
Write
SA (2)*4
Write
B0H*11
(Without
CA*7)
4
Write
SA (2)*4
Write
40H *11, 12
(With CA*7)
4 + 2h*6 Write
SA (2)*4
Write
CA (1)
4
Bus
cycles
Command
Read
Serial read (1) (Without CA) 3
(With CA)
Auto erase
Auto program Program (1)
10
4
Write
SA (2)*
Write
40H *11, 12
Program (3) (Control bytes)*7 4
Write
SA (2)*4
Write
40H *11, 12
(WithoutCA*7) 4
Write
SA (2)*4
Write
40H *11, 12
4 + 2h*6 Write
SA (2)*4
Write
CA (1)
SA (2)*4
Write
40H *11, 12
Program (2)*
Program (4)
(With CA*7)
Reset
1
Clear status register
1
Data recovery write
4
8
Write
HN29W12811 Series
Bus
cycles
Command
Read
Sixth bus cycle
Operation
mode
Operation
mode
Data in
CA (2)*5
Write
40H *11, 12
CA (2)
Write
40H *11, 12
Data in
Serial read (1) (Without CA) 3
3 + 2h*6 Write
(With CA)
Auto erase
Fifth bus cycle
Serial read (2)
3
Read identifier codes
1
Data recovery read
1
Single sector
4
Auto program Program (1)
(Without
CA*7)
4
(With CA*7)
4 + 2h*6 Write
Program (2)*10
CA (2)*5
4
7
Program (3) (Control bytes)* 4
Program (4)
(WithoutCA*7) 4
(With CA*7)
4 + 2h*6 Write
Reset
1
Clear status register
1
Data recovery write
4
Notes: 1. Commands and sector address are latched at rising edge of WE pulses. Program data is latched
at rising edge of SC pulses.
2. The chip is in the read status register mode when RES is set to VIHR first time after the power up.
3. Refer to the command read and write mode in mode selection.
4. SA (1) = Sector address (A0 to A7), SA (2) = Sector address (A8 to A12).
5. CA (1) = Column address (A0 to A7), CA (2) = Column address (A8 to A11).
(0 ≤ A11 to A0 ≤ 83FH)
6. The variable h is the input number of times of set of CA (1) and CA (2) (1 ≤ h ≤ 2048 + 64).
Set of CA (1) and CA (2) can be input without limitation.
7. By using program (1) and (3), data can additionally be programmed maximum 15 times for each
sector before erase.
8. ID = Identifier code; Manufacturer code (07H), Device code (95H).
9. The manufacturer identifier code is output when CDE is low and the device identifier code is output
when CDE is high.
10. Before program (2) operations, data in the programmed sector must be erased.
11. No commands can be written during auto program and erase (when the RDY/Busy pin outputs a
VOL ).
12. The fourth or sixth cycle of the auto program comes after the program data input is complete.
9
HN29W12811 Series
Mode Description
Read
Serial Read (1): Memory data D0 to D2111 in the sector of address SA is sequentially read. Output data is
not valid after the number of the SC pulse exceeds 2112. When CA is input, memory data D (m) to D (m + j)
in the sector of address SA is sequentially read. Then output data is not valid after the number of the SC pulse
exceeds (2112 to m). The mode turns back to the standby mode at any time when CE is VIH.
Serial Read (2): Memory data D2048 to D2111 in the sector of address SA is sequentially read. Output data
is not valid after the number of the SC pulse exceeds 64. The mode turns back to the standby mode at any
time when CE is VIH.
Automatic Erase
Single Sector Erase: Memory data D0 to D2111 in the sector of address SA is erased automatically by
internal control circuits. After the sector erase starts, the erasure completion can be checked through the
RDY/Busy signal and status data polling. All the bits in the sector are "1" after the erase. The sector valid
data stored in a part of memory data D2048 to D2111 must be read and kept outside of the sector before the
sector erase.
Automatic Program
Program (1): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by
internal control circuits. When CA is input, program data PD (m) to PD (m + j) is programmed from CA into
the sector of address SA automatically by internal control circuits. By using program (1), data can
additionally be programed for each sector before the following erase. When the column is programmed, the
data of the column must be [FF]. After the programming starts, the program completion can be checked
through the RDY/Busy signal and status data polling. Programmed bits in the sector turn from "1" to "0"
when they are programmed. The sector valid data should be included in the program data PD2048 to PD2111.
Program (2): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by
internal control circuits. After the programming starts, the program completion can be checked through the
RDY/Busy signal and status data polling. Programmed bits in the sector turn from "1" to "0" when they are
programmed. The sector must be erased before programming. The sector valid data should be included in the
program data PD2048 to PD2111.
Program (3): Program data PD2048 to PD2111 is programmed into the sector of address SA automatically
by internal control circuits. By using program (3), data can additionally be programed for each sector befor
the following erase. When the column is programmed, the data of the column must be [FF]. After the
programming starts, the program completion can be checked through the RDY/Busy signal and status data
polling. Programmed bits in the sector turn from "1" to "0" when they are programmed.
10
HN29W12811 Series
Program (4): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by
internal control circuits. When CA is input, program data PD (m) to PD (m + j) is programmed from CA into
the sector of address SA automatically by internal control circuits. By using program (4), data can be
rewritten for each sector before the following erase. So the column data before programming operation are
either "1" or "0". In this mode, E/W number of times must be counted whenever program (4) execute. After
the programming starts, the program completion can be checked through the RDY/Busy signal and status data
polling. The sector valid data should be included in the program data PD2048 to PD2111.
8191
8191
Sector
address
8191
Sector
address
Sector
address
Memory array
Memory array
0
Memory array
0
0
2111
Register
Serial read (1) (Without CA)
Program (1) (Without CA)
Program (2)
0
0
Column address
2111
Register
Serial read (1) (With CA)
Program (1) (With CA)
0
2048
2111
Register
Serial read (2)
Program (3)
Status Register Read
The status returns to the status register read mode from standby mode, when CE and OE is VIL. In the status
register read mode, I/O pins output the same operation status as in the status data polling defined in the
function description.
Identifier Read
The manufacturer and device identifier code can be read in the identifier read mode. The manufacturer and
device identifier code is selected with CDE VIL and V IH, respectively.
11
HN29W12811 Series
Data Recovery Read
When the programming was an error, the program data can be read by using data recovery read. When an
additional programming was an error, the data compounded of the program data and the origin data in the
sector address SA can be read. Output data are not valid after the number of SA pulse exeeds 2112. The
mode turns back to the standby mode at any time when CE is VIH. The read data are invalid when addresses
are latched at a rising edge of WE pulse after the data recovery read command is written.
Data Recovery Write
When the programming into a sector of address SA was an error, the program data can be rewritten
automatically by internal control circuit into the other selected sector of address SA’. In this case, top address
[SA12] of sector of address SA’ must be the same as SA. Since the data recovery write mode is internally
Program (4) mode, rewritten sector of address SA’ needs no sector erase before rewrite. After the data
recovery write mode starts, the program completion can be checked through the RDY/Busy signal and the
status data polling.
12
HN29W12811 Series
Command/Address/Data Input Sequence
Serial Read (1) (With CA before SC)
Command
/Address
CDE
00H
SA (1)
SA (2)
CA (1)
CA (2)
CA (1)'
CA (2)'
WE
SC Low
Data output
Data output
Serial Read (1) (With CA after SC)
Command
/Address
00H
SA (1)
SA (2)
CA (1)
CA (2)
CA (1)'
CA (2)'
CDE
WE
SC
Low
Data output
Data output
Data output
Serial Read (1) (Without CA), (2)
Command/Address
00H/F0H
SA (1)
SA (2)
CDE
WE
SC
Low
Data output
Single Sector Erase
Command/Address
20H
SA (1)
SA (2)
B0H
CDE
WE
SC
Low
Erase start
13
HN29W12811 Series
Program (1), (4) (With CA before SC)
Command
/Address
10H/11H
SA (1)
SA (2)
CA (1)
CA (2)
CA (1)'
CA (2)'
40H
CDE
WE
SC
Low
Data input
Data input
Program start
Program (1), (4) (With CA after SC)
Command
/Address
10H/11H
SA (1)
SA (2)
CA (1)
CA (2)
CA (1)'
CA (2)'
40H
CDE
WE
SC
Low
Data input
Data input
Data input
Program start
Program (1), (4) (Without CA)
Command/Address
10H/11H
SA (1)
SA (2)
40H
CDE
WE
SC
Low
Data input
Program start
Program (2)
Command/Address
1FH
SA (1)
SA (2)
40H
CDE
WE
SC
Low
Data input
14
Program start
HN29W12811 Series
Program (3)
Command/Address
0FH
SA (1)
SA (2)
40H
CDE
WE
SC
Low
Data input
Program start
ID Read Mode
Command/Address
90H
CDE
WE
SC
Low
Manufacture Device code Manufacture
code output output
code output
Data Recovery Read Mode
Command/Address
01H
CDE
WE
SC
Low
Data output
Data Recovery Write Mode
Command/Address
12H
SA (1)
SA (2)
40H
CDE
WE
SC
Low
Program start
15
HN29W12811 Series
Status Transition
VCC
Deep
standby
Column address
input
Power off
CA(1)
CA(2)
RES
00H/F0H
FFH
CE
90H
Read (1) / (2) SA (1), SA (2)
setup
ID read setup
CDE, OE
Sector address OE, SC
input
CA(1)' OE
CA(2)' SC
Read (1) / (2)
ID read
FFH
CE
BUSY
20H
FFH
Sector
Erase setup
SA (1), SA (2)
Sector
address input
B0H
Erase
start
OE
Status register
read
Erase finish
Column address SC, CDE
PD(m)
input
CA(1)
CA(2)
CE
Standby
CA(1)' to
CA(2)' PD(m+j)
PD0 to
10H
SA (1),
PD2111
OE
40H
Output /11H
SA
(2)
Program
Sector address
Program
Program
disable
(1)/(4) setup
input
data input
start
FFH
SC, CDE
Program finish
Status register
read
PD0 to
1FH
SA (1),
PD2111*3
OE
40H
/0FH Program (2)/(3) SA (2) Sector address
Status register
Program
Program
read
input
data
input
setup
start
SC,
CDE
FFH
Program finish
Program error or
Status register clear 50H
Erase error
CE*2
FFH*2
ERROR
01H*1
Data recovery OE, SC
Data recovery
read setup
read
SA(1)
1
Error CE
Output 12H* Data recovery SA(2) Sector address 40H
standby
disable
write setup
input
*4
FFH
OE
Notes: 1.
2.
3.
4.
16
Status register
read
OE
Status register
read
(01H)/(12H) Data recovery read/write can be used only for Program (1), (2), (3), (4) errors.
When reset is done by CE or FFH, error status flag is cleared.
When Program (3) mode, input data is PD2048 to PD2111.
When Error standby, ICC3 level is current.
HN29W12811 Series
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Notes
VCC voltage
VCC
–0.6 to +4.6
V
1
VSS voltage
VSS
0
V
All input and output voltages
Vin, Vout
–0.6 to VCC + 0.3
V
Operating temperature range
Topr
0 to +70
˚C
Storage temperature range
Tstg
–65 to +125
˚C
Storage temperature under bias
Tbias
–10 to +80
˚C
1, 2
3
Notes: 1. Relative to VSS .
2. Vin, Vout = –2.0 V for pulse width ≤ 20 ns.
3. Device storage temperature range before programming.
Capacitance (Ta = 25˚C, f = 1 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input capacitance
Cin
—
—
6
pF
Vin = 0 V
Output capacitance
Cout
—
—
12
pF
Vout = 0 V
17
HN29W12811 Series
DC Characteristics (VCC = 3.3 V ± 0.3 V, Ta = 0 to +70˚C)
Parameter
Symbol Min
Typ
Max
Unit
Test conditions
Input leakage current
I LI
—
—
2
µA
Vin = VSS to V CC
Output leakage current
I LO
—
—
2
µA
Vout = VSS to V CC
Standby V CC current
I SB1
—
0.3
1
mA
CE = VIH
I SB2
—
30
50
µA
CE = VCC ± 0.2 V,
RES = VCC ± 0.2 V
Deep standby VCC current
I SB3
—
1
5
µA
RES = VSS ± 0.2 V
Operating VCC current
I CC1
—
5
20
mA
Iout = 0 mA, f = 0.2 MHz
I CC2
—
20
40
mA
Iout = 0 mA, f = 20 MHz
Operating VCC current (Program) I CC3
—
20
40
mA
In programming
Operating VCC current (Erase)
—
20
40
mA
In erase
—
0.8
Input voltage
Input voltage (RES pin)
Output voltage
I CC4
VIL
1, 2
–0.3*
V
3
VIH
2.0
—
VCC + 0.3*
V
VILR
–0.2
—
0.2
V
VIHR
VCC – 0.2 —
VCC + 0.2
V
VOL
—
—
0.4
V
I OL = 2 mA
VOH
2.4
—
—
V
I OH = –2 mA
Notes: 1. VIL min = –1.0 V for pulse width ≤ 50 ns in the read operation. VIL min = –2.0 V for pulse width ≤ 20
ns in the read operation.
2. VIL min = –0.6 V for pulse width ≤ 20 ns in the erase/data programming operation.
3. VIH max = VCC + 1.5 V for pulse width ≤ 20 ns. If VIH is over the specified maximum value, the
operations are not guaranteed.
AC Characteristics (VCC = 3.3 V ± 0.3 V, Ta = 0 to +70˚C)
Test Conditions
•
•
•
•
•
18
Input pulse levels: 0.4 V/2.4 V
Input pulse levels for RES: 0.2 V/VCC – 0.2 V
Input rise and fall time: 5 ns
Output load: 1 TTL gate + 100 pF (Including scope and jig.)
Reference levels for measuring timing: 0.8 V, 1.8 V
HN29W12811 Series
Power on and off, Serial Read Mode
HN29W12811
-60
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Write cycle time
t CWC
120
—
—
ns
Serial clock cycle time
t SCC
60
—
—
ns
CE setup time
t CES
0
—
—
ns
CE hold time
t CEH
0
—
—
ns
Write pulse time
t WP
60
—
—
ns
Write pulse high time
t WPH
40
—
—
ns
Address setup time
t AS
50
—
—
ns
Address hold time
t AH
10
—
—
ns
Data setup time
t DS
50
—
—
ns
Data hold time
t DH
10
—
—
ns
SC to output delay
t SAC
—
—
60
ns
OE setup time for SC
t OES
0
—
—
ns
OE low to output low-Z
t OEL
0
—
40
ns
OE setup time before read
t OER
250
—
—
ns
OE setup time before command
write
t OEWS
0
—
—
ns
SC to output hold
t SH
15
—
—
ns
CE = OE = VIL, WE = VIH
OE high to output float
t DF
—
—
40
ns
CE = VIL, WE = VIH
WE to SC delay time
t WSD
50
—
—
µs
RES to CE setup time
t RP
1
—
—
ms
SC to OE hold time
t SOH
50
—
—
ns
SC pulse width
t SP
25
—
—
ns
SC pulse low time
t SPL
25
—
—
ns
SC setup time for CE
t SCS
0
—
—
ns
CDE setup time for WE
t CDS
0
—
—
ns
CDE hold time for WE
t CDH
20
—
—
ns
VCC setup time for RES
t VRS
1
—
—
µs
CE = VIH
RES to V CC hold time
t VRH
1
—
—
µs
CE = VIH
CE setup time for RES
t CESR
1
—
—
µs
RDY/Busy undefined for V CC off
t DFP
0
—
—
ns
Notes
CE = VIL, OE = VIH
CE = OE = VIL, WE = VIH
1
2
19
HN29W12811 Series
HN29W12811
-60
Parameter
Symbol
Min
Typ
Max
Unit
RES high to device ready
t BSY
—
—
1
ms
CE pulse high time
t CPH
200
—
—
ns
CE, WE setup time for RES
t CWRS
0
—
—
ns
RES to CE, WE hold time
t CWRH
0
—
—
ns
SC setup for WE
t SW
50
—
—
ns
CE hold time for OE
t COH
0
—
—
ns
SA (2) to CA (2) delay time
t SCD
—
—
30
µs
RDY/Busy setup for SC
t RS
200
—
—
ns
Time to device busy on read mode t DBR
—
—
1
µs
Busy time on reset mode
—
45
—
µs
t RBSY
Test conditions
Notes
Notes: 1. t DF is a time after which the I/O pins become open.
2. t WSD (min) is specified as a reference point only for SC, if t WSD is greater than the specified tWSD (min)
limit, then access time is controlled exclusively by tSAC.
20
HN29W12811 Series
Program, Erase and Erase Verify
HN29W12811
-60
Parameter
Symbol
Min
Typ
Max
Unit
Write cycle time
t CWC
120
—
—
ns
Serial clock cycle time
t SCC
60
—
—
ns
CE setup time
t CES
0
—
—
ns
CE hold time
t CEH
0
—
—
ns
Write pulse time
t WP
60
—
—
ns
Write pulse high time
t WPH
40
—
—
ns
Address setup time
t AS
50
—
—
ns
Address hold time
t AH
10
—
—
ns
Data setup time
t DS
50
—
—
ns
Data hold time
t DH
10
—
—
ns
OE setup time before command
write
t OEWS
0
—
—
ns
OE setup time before status polling t OEPS
40
—
—
ns
OE setup time before read
t OER
250
—
—
ns
Time to device busy
t DB
—
—
150
ns
Time to device busy on read mode t DBR
—
—
1
µs
Auto erase time
t ASE
—
1.0
14.0
ms
Auto program time
Program(1), (3)
t ASP
—
2.5
22.0
ms
Program(2)
t ASP
—
2.0
22.0
ms
Program(4),
Data recovery write
t ASP
—
2.5
30.0
ms
WE to SC delay time
t WSD
50
—
—
µs
WE to SC delay time on recovery
read mode
t WSDR
2
—
—
µs
CE pulse high time
t CPH
200
—
—
ns
SC pulse width
t SP
25
—
—
ns
SC pulse low time
t SPL
25
—
—
ns
Data setup time for SC
t SDS
0
—
—
ns
Data hold time for SC
t SDH
35
—
—
ns
SC setup for WE
t SW
50
—
—
ns
Test conditions
Note
CDE = VIL
21
HN29W12811 Series
HN29W12811
-60
Parameter
Symbol
Min
Typ
Max
Unit
SC setup for CE
t SCS
0
—
—
ns
SC hold time for WE
t SCHW
20
—
—
ns
CE to output delay
t CE
—
—
120
ns
OE to output delay
t OE
—
—
60
ns
OE high to output float
t DF
—
—
40
ns
RES to CE setup time
t RP
1
—
—
ms
CDE setup time for WE
t CDS
0
—
—
ns
CDE hold time for WE
t CDH
20
—
—
ns
CDE setup time for SC
t CDSS
1.5
—
—
µs
CDE hold time for SC
t CDSH
30
—
—
ns
Next cycle ready time
t RDY
0
—
—
ns
CDE to OE hold time
t CDOH
50
—
—
ns
CDE to output delay
t CDAC
—
—
50
ns
CDE to output invalid
t CDF
—
—
100
ns
CE setup time for OE
t COS
0
—
—
ns
CE hold time for OE
t COH
0
—
—
ns
CDE to OE setup time
t CDOS
20
—
—
ns
OE setup time for SC
t OES
0
—
—
ns
OE low to output low-Z
t OEL
0
—
40
ns
SC to output delay
t SAC
—
—
60
ns
SC to output hold
t SH
15
—
—
ns
RDY/Busy setup for SC
t RS
200
—
—
ns
CE hold time for WE
t CWH
1.0
—
—
µs
CE hold time for WE on recovery
read mode
t CWHR
2
—
—
µs
WE hold time for WE
t WWH
1
—
—
µs
Busy time on read mode
t RBSY
—
45
—
µs
Note:
22
1. t DF is a time after which the I/O pins become open.
Test conditions
Note
1
HN29W12811 Series
Timing Waveforms
Power on and off Sequence
VCC
tVRS
CE
tRP
tCES
tCEH tCESR
tRP
WE
*1
tCESR
tVRH
*2
tBSY
tCEH
tCWRH
tCWRS
RES
tCES
High-Z
tDFP
*1
Ready
tBSY
RDY
/Busy
Notes: 1. RES must be kept at the VILR level referred to DC characteristics at the rising and falling edges of VCC
to guarantee data stored in the chip.
2. RES must be kept at the VIHR level referred to DC characteristics while I/O7 outputs the VOL level in the
status data polling and RDY/Busy outputs the VOL level.
3.
: Undefined
23
HN29W12811 Series
Serial Read (1) (2) Timing Waveform
*1
tCOH
CE
tCPH
tCES
OE
*3
tCWC
tCWC
tWPH
tOEWS
tCEH
tOER
tWPH
WE
tCDS
tWP
tCDS
CDE
tWP
tWP tCDH
tWP
tOES
tSCC
tWSD
tCDH
SC
tSCS
tDH
tAS
tDS
tAH
tSP
tAH
tAS
SA(1)
SA(2)
RES
D0out/D2048out
tSOH
*2
tSAC
tSH
tSPL
tSAC tSH
tOEL
I/O0 to I/O7
00H
/F0H
tSCC
tSAC
tSAC
D1out/D2049out
tCDS
tDS tDH
tDF
D2111out/D2111out
FFH
*2
tRBSY
tRP
tRS
tDBR
High-Z
RDY
/Busy
Notes: 1. The status returns to the standby at the rising edge of CE.
2. Output data is not valid after the number of the SC pulse exceeds 2112 and 64 in the serial read mode (1)and (2), respectively.
3. After any commands are written, the status can return to the standby after the command FFH is input and CE turns to the VIH level.
Serial Read (1) with CA before SC Timing Waveform
5
h-1 cycle *
tCOH*1
CE
tCPH
tCES
OE
tCWC
tCWC
tWPH
tOEWS
tCWC
tWPH
tWPH
tOEWS
tCWC
tWPH
tOER
tCDS
tWP
tCDS t
WP
tSW
tWP
tWP
tWP
tSCD
CDE
tOES
tSCC
tWSD
tCDH
SC
tOER
tWPH
WE
tSCC *2
tWP
tWP
tSOH
tWP tCDH
tOES tSCC
tSCC *3
tSOH
tCDS
tSP
tSCS
tDS tDH
tAS tAH
tAS tAH
tAS tAH
tAS tAH
tSAC
tSPL tSAC
t
tOEL SAC t
tSH
SH
tSAC
tDF
tAS tAH
tAS
tAH
I/O0 to I/O7
tRP
00H
SA(1)
SA(2)
CA(1)
CA(2)
D(n)out
D(n+1)out
D(n+i)out *2
CA(1)'
CA(2)'
tSAC
tOEL
tSP tSPL tSAC
tSAC
tSH
tSH
D(m)out
D(m+1)out
tSAC
tDF
D(m+j)out *3
RES
tDBR
RDY
/Busy
tRBSY
tRS
High-Z
The status returns to the Standby at the rising edge of CE.
Output data is not valid after the number of the SC pulse exceeds (2112-n). (i ≤ 2111-n, 0 ≤ n ≤ 2111)
Output data is not valid after the number of the SC pulse exceeds (2112-m). (j ≤ 2111-m, 0 ≤ m ≤ 2111)
After any commands are written, the status can return to the standby after the command FFH is input and CE turns
to the VIH level.
5. This interval can be repeated (h-1) cycle. (1≤ h ≤ 2048 + 64)
Notes: 1.
2.
3.
4.
24
tCEH*4
tCWC
tDS
tDH
FFH
HN29W12811 Series
Serial Read (1) with CA after SC Timing Waveform
h cycle*
5
tCOH *1
CE
tCPH
tCES
OE
tCWC
tWPH
tOEWS
tOEWS
tCWC
tOER
tWPH
tSW
tWP
tWP
tWP
tWP
tCDH
CDE
tOER
tWPH
WE
tWP
tWP tCDH
tOES
tOES
tCDS
tCDS
tSCC
tWSD
tSOH
tSCC 2
*
tSCC
SC
tSCS
tDS tDH
tAS tAH
tSAC
t
t
tOEL t SP SPL
tSH
SAC
tAS tAH
tSAC
tSAC
tDF
tAH
tAS
tSH
tAS
tAH
I/O0 to I/O7
00H
SA(1)
SA(2)
D0out
D(k)out *2
D1out
tSCC *3
tSOH
tCDS
tSP
tOEL
tRP
4
tCEH*
tCWC
CA(1)
CA(2)
tSAC
tSAC tSPL tSAC
tSH
tSH
D(m)out
D(m+1)out
tSAC
tDF
tDS
tDH
FFH
D(m+j)out *3
RES
tRBSY
tDBR
tRS
High-Z
RDY
/Busy
Notes: 1.
2.
3.
4.
5.
The status returns to the Standby at the rising edge of CE.
Output data is not valid after the number of the SC pulse exceeds 2112. (0 ≤ k ≤ 2111)
Output data is not valid after the number of the SC pulse exceeds (2112-m). (j ≤ 2111-m, 0 ≤ m ≤ 2111)
After any commands are written, the status can return to the standby after the command FFH is input and CE turns to the VIH level.
This interval can be repeated h cycle. (1≤ h ≤ 2048 + 64)
Erase and Status Data Polling Timing Waveform (Sector Erase)
CE
OE
tCWC
tCWC
tWPH
tOEWS
tCE
tCEH
tCES
tCWC
tWPH
tOE
tOEPS
tASE
tWPH
tRDY
WE
tCDS
CDE
tCDS
tWP
tCDS
tWP
tWP
tWP
tCDS
tCDH
tCDH
tSCHW
tCDH
SC
tSCS
tDH
tAS
tDS
tAH
tAH
tAS
tDH
tDF
tDS
tDF
I/O0 to I/O7
20H
SA(1)
SA(2)
IO7 = VOL
B0H
IO7 = VOH
RES
tRP
RDY
/Busy
High-Z
*2
High-Z
tDB
*1
Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/Busy outputs a VOL.
2. The status returns to the standby status after RDY/Busy returns to High-Z.
25
HN29W12811 Series
Program (1) and Status Data Polling Timing Waveform
CE
tCES
OE
tCEH
tOEWS tCWC
tCE
tCWC
tWPH
tOEPS
tWPH
tRDY
tOE
WE
tCDS
tWPtCDS tWP
tCDSS
tWP
tCDS
tASP
tSW tWP
CDE
tCDH
tSCC
tSPL
*1
tSDH
tSP
tSDS
tSP
tCDH
tCDH
tSCHW
SC
tSCS
tDS
tDH
tAS
tAH
tAS
tAH
tDS
tDF
tDH
tDF
I/O0 to I/O7
10H
SA (1)
SA (2)
RES
PD0
PD1
PD2111
40H
I/O7 = VOL
tDB
tRP
Notes: 1.
2.
3.
4.
26
*3
High-Z
High-Z
RDY
/Busy
The programming operation is not guranteed when the number of the SC pulse exceeds 2112.
Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.
The status returns to the standby status after RDY/Busy returns to High-Z.
By using program (1), data can be programmed additionally for each sector before erase.
I/O7 = VOH
*2
HN29W12811 Series
Program (1) with CA before SC and Status Data Polling Timing Waveform
h–1 cycle*6
CE
tCES
OE
tCEH tCE
tCWC
tCWC
tWPH
tWPH
tOEWS
tCWC
tWPH
tCWC
tWPH
tCWC
tWPH
WE
tOEPS
tOE
tRDY
tSW
tCDS t
t
WP CDS tWP
tWP
tWP
tWP
tWP
tCDS
tCDSS
tWP
tWP
tCDSS
tSCS
tCDH
tSCC
tSPL
tCDH
SC
tDS
t
tDHAS
tAH
tAS
tAH
tAH
tAS
tAS
tAH
t
tSDS SDH
tSP
*1
tCDSH
tSP
tAS
tSCC
tSPL
tCDH
tAH
tAS
tAH
tSDS
tCDS
tASP
tSW
CDE
tSDH
tCDH
tSCHW
*2
tSP
tDH
tSP tDS
tDF
tDF
I/O0 to I/O7
10H
SA(1)
SA(2)
CA(1)
CA(2)
PD(n) PD(n+1) PD(n+i)*1
CA(1)'
CA(2)'
PD(m) PD(m+1)PD(m+j)*2 40H
I/O7=VOL
I/O7=VOH
RES
tRP
tDB
High-Z
RDY
/Busy
High-Z*4
*3
Notes: 1.
2.
3.
4.
5.
6.
The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – n).(i ≤ 2111 – n, 0 ≤ n ≤ 2111)
The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)
Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.
The status returns to the standby status after RDY/Busy returns to High-Z.
By using program (1), data can be programmed additionally for each sector before erase.
This interval can be repeated (h – 1) cycle.(1 ≤ h ≤ 2048 + 64)
Program (1) with CA after SC and Status Data Polling Timing Waveform
h cycle*6
CE
tCES
OE
tOEWS
tCEH tCE
tCWC
tWPH
tCWC
tCWC
tWPH
tWPH
WE
tOEPS
tOE
tRDY
tSW
tCDS tWP tCDS tWP
tWP
tWP
tCDS
tCDSS
tWP
tWP
tCDSS
CDE
tSCS
tCDH
tSCC
tSPL
tCDH
SC
tDS
t
tDHAS
tAH
tAS
tAH
tSDS
tSDH
*1
tSP
tCDSH
tSP
tAS
tSCC
tSPL
tCDH
tAH
tAS
tAH
tSDS
tCDS
tASP
tSW
tSDH
tCDH
tSCHW
*2
tSP
tSP
tDH
tDS
tDF
tDF
I/O0 to I/O7
10H
SA(1)
SA(2)
PD0
PD1
PD(k)*1
CA(1)
CA(2)
PD(m) PD(m+1)PD(m+j)*2 40H
I/O7=VOL
I/O7=VOH
RES
tRP
RDY
/Busy
Notes: 1.
2.
3.
4.
5.
6.
High-Z
tDB
High-Z*4
*3
The programming operation is not guaranteed when the number of the SC pulse exceeds 2112.(0 ≤ k ≤ 2111)
The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)
Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.
The status returns to the standby status after RDY/Busy returns to High-Z.
By using program (1), data can be programmed additionally for each sector before erase.
This interval can be repeated h cycle.(1 ≤ h ≤ 2048 + 64)
27
HN29W12811 Series
Program (2) and Status Data Polling Timing Waveform
CE
tCES
OE
tCEH
tOEWS tCWC
tCE
tCWC
tWPH
tOEPS
tWPH
tRDY
tOE
WE
tCDS
tWPtCDS tWP
tCDSS
tWP
tASP
tSW tWP
tCDS
CDE
tCDH
tSCC
tSPL
*1
tSDH
tSP
tSDS
tSP
tCDH
tCDH
tSCHW
SC
tSCS
tDS
tDH
tAS
tAH
tAS
tAH
tDS
tDF
tDH
tDF
I/O0 to I/O7
1FH
SA (1)
SA (2)
RES
Notes: 1.
2.
3.
4.
28
PD1
PD2111
40H
I/O7 = VOL
tDB
tRP
RDY
/Busy
PD0
I/O7 = VOH
*3
High-Z
High-Z
*2
The programming operation is not guranteed when the number of the SC pulse exceeds 2112.
Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.
The status returns to the standby status after RDY/Busy returns to High-Z.
By using program (2), the programmed data of each sector must be erased before programming next data.
HN29W12811 Series
Program (3) and Status Data Polling Timing Waveform
CE
tCES
OE
tCEH
tOEWS tCWC
tCE
tCWC
tOEPS
tWPH
tRDY
tOE
WE
tCDS
tWPtCDS tWP
tCDSS
tWP
tASP
tSW tWP
tCDS
CDE
tCDH
tCDH
tSCC
tSPL
*1
tSDH
tSP
tSDS
tSP
tCDH
tSCHW
SC
tSCS
tDS
tDH
tAS
tAH
tAS
tAH
tDS
tDF
tDH
tDF
I/O0 to I/O7
0FH
SA (1)
SA (2) PD2048 PD2049 PD2111
RES
40H
I/O7 = VOL
tDB
tRP
Notes: 1.
2.
3.
4.
*3
High-Z
High-Z
RDY
/Busy
I/O7 = VOH
*2
The programming operation is not guranteed when the number of the SC pulse exceeds 64.
Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.
The status returns to the standby status after RDY/Busy returns to High-Z.
By using program (3), the data can be programmed additionally for each sector before erase.
29
HN29W12811 Series
Program (4) and Status Data Polling Timing Waveform
CE
tCES
OE
tCEH
tOEWS tCWC
tCE
tCWC
tWPH
tOEPS
tWPH
tRDY
tOE
WE
tCDS
tWPtCDS tWP
tCDSS
tWP
tASP
tSW tWP
tCDS
CDE
tCDH
tSCC
tSPL
*1
tSDH
tSP
tSDS
tSP
tCDH
tCDH
tSCHW
tWSD
SC
tSCS
tDS
tDH
tAS
tAH
tAS
tAH
tDS
tDF
tDH
tDF
I/O0 to I/O7
11H
SA (1)
SA (2)
PD0
PD1
RES
tDBR
tRP
PD2111
40H
I/O7 = VOL
tDB
tRS
*2
tRBSY
Notes: 1.
2.
3.
4.
30
*3
High-Z
High-Z
RDY
/Busy
The programming operation is not guranteed when the number of the SC pulse exceeds 2112.
Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.
The status returns to the standby status after RDY/Busy returns to High-Z.
By using program (4), data can be rewritten for each sector.
I/O7 = VOH
HN29W12811 Series
Program (4) with CA before SC and Status Data Polling Timing Waveform
h–1 cycle*6
CE
tCES
OE
tCEH tCE
tCWC
tCWC
tWPH
tWPH
tOEWS
tCWC
tWPH
tCWC
tWPH
tCWC
tWPH
WE
tOEPS
tOE
tRDY
tSW
tCDS tWP tCDS tWP
tWP
tWP
tWP
tWP
tCDS
tCDSS
tWP
tWP
tCDSS
CDE
tSCS
tCDH
tSCC
tSPL
tCDH
tWSD
SC
tDS
t
tDHAS
tAH
tAH
tAS
tAS
tAH
tAS
tAH
t
tSDS SDH
tSP
*1
tCDSH
tSP
tAS
tSCC
tSPL
tCDH
tAH
tAS
tAH
tSDS
tCDS
tASP
tSW
tSDH
tCDH
tSCHW
*2
tSP
tDH
tSP tDS
tDF
tDF
I/O0 to I/O7
11H
SA(1)
SA(2)
CA(1)
CA(2)
PD(n) PD(n+1) PD(n+i)*1
CA(1)'
CA(2)'
PD(m) PD(m+1)PD(m+j)*2 40H
I/O7=VOL
I/O7=VOH
RES
tRP
tDBR
tRS
tRBSY
RDY
/Busy
Notes: 1.
2.
3.
4.
5.
6.
tDB
High-Z
High-Z*4
*3
The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – n).(i ≤ 2111 – n, 0 ≤ n ≤ 2111)
The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)
Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.
The status returns to the standby status after RDY/Busy returns to High-Z.
By using program (4), data can be rewritten for each sector.
This interval can be repeated (h – 1) cycle.(1 ≤ h ≤ 2048 + 64)
Program (4) with CA after SC and Status Data Polling Timing Waveform
h cycle*6
CE
tCES
OE
tOEWS
tCEH tCE
tCWC
tWPH
tCWC
tCWC
tWPH
tWPH
WE
tOEPS
tOE
tRDY
tSW
tCDS tWP tCDS tWP
tWP
tWP
tCDS
tCDSS
tWP
tWP
tCDSS
CDE
tSCS
tCDH
tWSD
tCDH
tSCC
tSPL
SC
tDS
t
tDHAS
tAH
tAS
tAH
tSDS
tSDH
*1
tSP
tCDSH
tSP
tAS
tSCC
tSPL
tCDH
tAH
tAS
tAH
tSDS
tCDS
tASP
tSW
tSDH
tCDH
tSCHW
*2
tSP
tSP
tDH
tDS
tDF
tDF
I/O0 to I/O7
11H
SA(1)
SA(2)
RES
Notes: 1.
2.
3.
4.
5.
6.
PD1
PD(k)*1
CA(1)
CA(2)
PD(m) PD(m+1)PD(m+j)*2 40H
I/O7=VOL
I/O7=VOH
tRBSY
tRP
RDY
/Busy
PD0
tDBR
tRS
High-Z
tDB
High-Z*4
*3
The programming operation is not guaranteed when the number of the SC pulse exceeds 2112.(0 ≤ k ≤ 2111)
The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)
Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.
The status returns to the standby status after RDY/Busy returns to High-Z.
By using program (4), data can be rewritten for each sector.
This interval can be repeated h cycle.(1 ≤ h ≤ 2048 + 64)
31
HN29W12811 Series
ID and Status Register Read Timing Waveform
*1
*1
CE
tCES
tCOH
tCOH
OE
tOEWS
tOEPS
WE
tCDS
tCDH
tWP
tCDCH
CDE
tCE
tSCHW
SC
tSCS
tDH t
OE tCDF
tDS
tCDAC
tCDF
tCDAC
tDF
tSCS
tOE
tDF
I/O0 to I/O7
90H
Manufacturer Device Manufacturer
code
code
code
RES
tRP
RDY
/Busy
Note: 1. The status returns to the standby at the rising edge of CE.
32
High-Z
Status
register
HN29W12811 Series
Data Recovery Read Timing Waveform
*3
*1
tCPH
CE
tCES
tCOH
tCWHR
tCEH
OE
tOEWS
tOER
tCDS
tCDH
tCDOS
WE
tWP
CDE
tWP
tCDH
tOES
tWSDR
tSCC
tSP
SC
tSCS
tDS
tDH
tOEL
tSCC
*2
tSPL
tSAC
t
t
tSH SAC tSH SAC
tSOH
tSAC
tCDS
tDH
tDF
tDS
I/O0 to I/O7
01H
D0out
D1out
D2111out
*2
FFH
High
RES
High-Z
RDY
/Busy
Notes: 1. The status returns to the standby at the rising edge of CE.
2. Output data is not valid after the number of the SC pulse exceed 2112 in the recovery data read mode.
3. After any commands are written, the status can turns to the standby after the command FFH is input
and CE turns to the VIH level.
33
HN29W12811 Series
Data Recovery Write Timing Waveform
CE
OE
tCWC
tCWC
tWPH
tOEWS
tCE
tCEH
tCES
tCWC
tWPH
tCOS
tOE
tOEPS
tRDY
tWPH
WE
tCDS
CDE
tWP
tCDS
tWP
tWP
tCDS
tASP
tWP
tCDS
tCDH
tCDH
tSCHW
tCDH
SC
tSCS
tDH
tAS
tDS
tAH
tAH
tAS
tDH
tDF
tDS
tDF
I/O0 to I/O7
12H
SA(1)
SA(2)
IO7 = VOL
40H
IO7 = VOH
High
RES
High-Z
RDY
/Busy
*2
High-Z
tDB
*1
Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/Busy is VOL.
2. The status returns to the standby status after RDY/Busy returns to High-Z.
34
HN29W12811 Series
Clear Status Register Timing Waveform
*1
CE
tCPH
tCES
OE
tCWH
tOEWS
tWWH
tOEWS
WE
tCDS
tWP tCDH
tCES
tCDS
tWP
tCDH
tWP tCDH
CDE
tCDS
SC
tSCS
tDS
tDH
tDS tDH
tSCS
tDS tDH
I/O0 to I/O7
50H
RES
RDY
/Busy
Next
Command
Next
Command
High
High-Z
Note 1. The status returns to the standby at the rising edge of CE.
35
HN29W12811 Series
Function Description
Status Register: The HN29W12811 outputs the operation status data as follows: I/O7 pin outputs a V OL to
indicate that the memory is in either erase or program operation. The level of I/O7 pin turns to a VOH when
the operation finishes. I/O5 and I/O4 pins output V OLs to indicate that the erase and program operations
complete in a finite time, respectively. If these pins output VOHs, it indicates that these operations have timed
out. When these pins monitor, I/O7 pin must turn to a VOH . To execute other erase and program operation,
the status data must be cleared after a time out occurs. From I/O0 to I/O3 pins are reserved for future use.
The pins output VOLs and should be masked out during the status data read mode. The function of the status
register is summarized in the following table.
I/O
Flag definition
Definition
I/O7
Ready/Busy
VOH = Ready, VOL = Busy
I/O6
Reserved
Outputs a V OL and should be masked out during the status data poling mode.
I/O5
Erase check
VOH = Fail, VOL = Pass
I/O4
Program check
VOH = Fail, VOL = Pass
I/O3
Reserved
Outputs a V OL and should be masked out during the status data poling mode.
I/O2
Reserved
I/O1
Reserved
I/O0
Reserved
Requirement for System
Specifications
Item
Min
Typ
Max
Unit
Usable sectors (initially)
8,029
—
8,192
sector
Spare sectors
145
—
—
sector
ECC (Error Correction Code)
1
—
—
—
3 × 10
Program/Erase endurance
36
—
bit/sector
5
cycle
HN29W12811 Series
Unusable Sector
Initially, the HN29W12811 includes unusable sectors. The unusable sectors must be distinguished from the
usable sectors by the system as follows.
1. Check the partial invalid sectors in the devices on the system. The usable sectors were programmed the
following data. Refer to the flowchart “The Unusable Sector Indication Flow”.
Initial Data of Usable Sectors
Column address
0H to 81FH
820H
821H
822H
823H
824H
825H
826H to 83FH
Data
FFH
1CH
71H
C7H
1CH
71H
C7H
FFH
2. Do not erase and program to the partial invalid sectors by the system.
START
Sector number = 0
Read data
Sector number =
Sector number + 1
Bad sector*2
No
Column address = 820H to 825H
Check data*1
Yes
No
Sector number = 8,191
Yes
END
Notes: 1. Refer to table "Initial data of usable sectors".
2. Bad sectors are installed in system.
The Unusable Sector Indication Flow
37
HN29W12811 Series
Requirements for High System Reliability
The device may fail during a program, erase or read operation due to write or erase cycles. The following
architecture will enable high system reliability if a failure occurs.
1. For an error in read operation: An error correction more than 1-bit error correction per each sector read is
required for data reliability.
2. For errors in program or erase operations: The device may fail during a program or erase operation due to
write or erase cycles. The status register indicates if the erase and program operation complete in a finite
time. When an error occurred in the sector, try to reprogram the data into another sector. Avoid further
system access to the sector that error happens. Typically, recommended number of a spare sectors are
1.8% of initial usable 8,029 sectors by each device. If the number of failed sectors exceeds the number of
the spare sectors, usable data area in the device decreases. For the reprogramming, do not use the data
from the failed sectors, because the data from the failed sectors are not fixed. So the reprogram data must
be the data reloaded from external buffer, or use the Data recovery read mode or the Data recovery write
mode (see the “Mode Description” and under figure “Spare Sector Replacement Flow after Program
Error”). To avoid consecutive sector failures, choose addresses of spare sectors as far as possible from the
failed sectors.
38
HN29W12811 Series
START
Program start
Set an usable sector
Program end
Check RDY/Busy
Check status
Yes
No
Clear status register
Load data from
external buffer
Data recovery read
Data recovery write
Program start
Set another
usable sector
Program end
Check RDY/Busy
Check status
No
Yes
Check status: Status register read
END
Spare Sector Replacement Flow after Program Error
39
HN29W12811 Series
Memory Structure
8,192 sectors
bit
sector
byte (8 bits)
2,112 bytes (16,896 bits)
Bit: Minimum unit of data.
Byte: Input/output data unit in programming and reading. (1 byte = 8 bits)
Sector: Page unit in erase, programming and reading. (1 sector = 2,112 bytes = 16,896 bits)
Device: 1 device = 8,192 sectors.
40
HN29W12811 Series
Package Dimensions
HN29W12811T Series (TFP-48DA)
12.00
12.40 Max
25
18.40
48
Unit: mm
24
1.20 Max
*0.22 ± 0.08
0.08 M
0.20 ± 0.06
0.45 Max
0.10
*Dimension including the plating thickness
Base material dimension
0.80
20.00 ± 0.20
0° – 5°
0.05 ± 0.05
0.50
*0.17 ± 0.05
0.125 ± 0.04
1
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
TFP-48DA
Conforms
Conforms
0.49 g
41
HN29W12811 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
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7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
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42