SCLS518 − AUGUST 2003 D Qualification in Accordance With D OR PW PACKAGE (TOP VIEW) AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control D D D D D D D D D D D SH/LD CLK E F G H QH GND Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 1500 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 13 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Complementary Outputs Direct Overriding Load (Data) Inputs Gated Clock Inputs Parallel-to-Serial Data Conversion 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLK INH D C B A SER QH † Contact factory for details. Q100 qualification data available on request. description/ordering information The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SN74HC165 also features a clock-inhibit (CLK INH) function and a complementary serial (QH) output. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs. ORDERING INFORMATION −40°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA TOP-SIDE MARKING SOIC − D Tape and reel SN74HC165QDRQ1 TSSOP − PW Tape and reel SN74HC165QPWRQ1 HC165Q1 HC165Q1 ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS518 − AUGUST 2003 FUNCTION TABLE INPUTS FUNCTION SH/LD CLK CLK INH L X X H H X No change H X H H L ↑ No change Shift† H ↑ L Shift† Parallel load † Shift = content of each internal register shifts toward serial output QH. Data at SER is shifted into the first register. logic diagram (positive logic) A SH/LD CLK INH CLK SER 1 B 11 C 12 D 13 E 14 F 3 G 4 H 5 6 9 15 10 S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R 7 2 QH 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QH SCLS518 − AUGUST 2003 typical shift, load, and inhibit sequence CLK CLK INH SER L SH/LD Data Inputs A H B L C H D L E H F L G H H H QH H H L H L H L H QH L L H L H L H L Inhibit Serial Shift Load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCLS518 − AUGUST 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO ∆t/∆v‡ MIN NOM MAX 2 5 6 Input voltage 3.15 0.5 1.35 Input transition rise/fall time VCC = 6 V V 1.8 0 VCC = 2 V VCC = 4.5 V V 4.2 0 Output voltage V 1.5 VCC = 4.5 V VCC = 6 V Low-level input voltage UNIT VCC VCC V V 1000 500 ns 400 TA Operating free-air temperature −40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS518 − AUGUST 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 µA VOH VI = VIH or VIL IOH = −4 mA IOH = −5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC VI = VCC or 0 VI = VCC or 0, IO = 0 Ci VCC MIN MIN 2V 1.9 1.998 1.9 4.5 V 4.4 4.499 4.4 6V 5.9 5.999 5.9 4.5 V 3.98 4.3 3.7 6V 5.48 5.8 MAX UNIT V 5.2 2V 0.002 0.1 0.1 4.5 V 0.001 0.1 0.1 6V 0.001 0.1 0.1 4.5 V 0.17 0.26 0.4 6V 0.15 0.26 0.4 6V ±0.1 ±100 ±1000 nA 8 160 µA 3 10 10 pF 6V 2 V to 6 V POST OFFICE BOX 655303 TA = 25°C TYP MAX • DALLAS, TEXAS 75265 V 5 SCLS518 − AUGUST 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency SH/LD low tw Pulse duration CLK high or low SH/LD high before CLK↑ SER before CLK↑ tsu Setup time CLK INH low before CLK↑ CLK INH high before CLK↑ Data before SH/LD↓ SER data after CLK↑ th Hold time PAR data after SH/LD↓ 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TA = 25°C MIN MAX MIN MAX 2V 6 4.2 4.5 V 31 21 6V 36 25 2V 80 120 4.5 V 16 24 6V 14 20 2V 80 120 4.5 V 16 24 6V 14 20 2V 80 120 4.5 V 16 24 6V 14 20 2V 40 60 4.5 V 8 12 6V 7 10 2V 100 150 4.5 V 20 30 6V 17 25 2V 40 60 4.5 V 8 12 6V 7 10 2V 100 150 4.5 V 20 30 6V 17 26 2V 5 5 4.5 V 5 5 6V 5 5 2V 5 5 4.5 V 5 5 6V 5 5 UNIT MHz ns ns ns SCLS518 − AUGUST 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax SH/LD tpd QH or QH CLK QH or QH H QH or QH tt Any VCC MIN TA = 25°C TYP MAX MIN 2V 6 13 4.2 4.5 V 31 50 21 6V 36 62 25 MAX UNIT MHz 2V 80 150 225 4.5 V 20 30 45 6V 16 26 38 2V 75 150 225 4.5 V 15 30 45 6V 13 26 38 2V 75 150 225 4.5 V 15 30 45 6V 13 26 38 2V 38 75 110 4.5 V 8 15 22 6V 6 13 19 ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 75 UNIT pF 7 SCLS518 − AUGUST 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% 50% 10% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. 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