TI SN74ALVTH162245VR

SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
D
D
D
D
D
D
D
D
D
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus  Design for
2.5-V and 3.3-V Operation and Low
Static-Power Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V VCC )
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
High Drive
– A Port = –12/12 mA at 3.3-V VCC
– B port = –32/64 mA at 3.3-V VCC
Ioff and Power-Up 3-State Support Hot
Insertion
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
A-Port Outputs Have Equivalent 30-Ω
Series Resistors, So No External Resistors
Are Required
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
SN54ALVTH162245 . . . WD PACKAGE
SN74ALVTH162245 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
description
The ’ALVTH162245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for 2.5-V or 3.3-V
VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively
isolated.
The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 30-Ω series resistors
to reduce overshoot and undershoot.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
description (continued)
When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
SN74ALVTH162245 . . . GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
A
B
C
D
E
F
G
1
2
3
4
5
6
A
1DIR
NC
NC
NC
NC
1OE
B
1B2
1B1
GND
GND
1A1
1A2
C
1B4
1B3
1A4
1B6
1B5
VCC
GND
1A3
D
VCC
GND
1A5
1A6
E
1B8
1B7
1A7
1A8
F
2B1
2B2
2A2
2A1
G
2B3
2B4
GND
GND
2A4
2A3
H
2B5
2B6
2B7
2B8
VCC
GND
2A5
J
VCC
GND
2A6
H
2A8
2A7
J
K
2DIR
NC
NC
NC
NC
2OE
K
NC – No internal connection
ORDERING INFORMATION
TA
–40°C
40°C to 85°C
–55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TOP-SIDE
MARKING
SSOP – DL
Tape and reel
SN74ALVTH162245LR
ALVTH162245
TSSOP – DGG
Tape and reel
SN74ALVTH162245GR
ALVTH162245
TVSOP – DGV
Tape and reel
SN74ALVTH162245VR
VT2245
VFBGA – GQL
Tape and reel
SN74ALVTH162245QR
CFP – WD
Tube
SNJ54ALVTH162245WD
SNJ54ALVTH162245WD
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit section)
INPUTS
2
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
logic diagram (positive logic)
1DIR
1
2DIR
48
1A1
25
1OE
47
2A1
2
24
2OE
36
13
1B1
To Seven Other Channels
2B1
To Seven Other Channels
Pin numbers shown are for the DGG, DGV, DL, and WD packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output current in the low state, IO: SN54ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Output current in the high state, IO: SN54ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA
SN74ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3)
SN54ALVTH162245
SN74ALVTH162245
MIN
MIN
VCC
VIH
Supply voltage
2.3
High-level input voltage
1.7
VIL
VI
Low-level input voltage
IOH
IOL
TYP
MAX
2.7
TYP
2.3
2.7
1.7
0
VCC
5.5
0
VCC
V
5.5
V
–6
–8
High-level output current (B port)
–6
–8
Low-level output current (A port)
6
12
Low-level output current (B port)
6
8
18
24
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
–55
Outputs enabled
10
10
mA
mA
ns/V
µs/V
200
125
V
0.7
High-level output current (A port)
Low-level output current;
current duty cycle ≤ 50%; f ≥ 1 kHz (B port)
UNIT
V
0.7
Input voltage
MAX
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3)
SN54ALVTH162245
SN74ALVTH162245
MIN
MIN
VCC
VIH
Supply voltage
3
High-level input voltage
2
VIL
VI
Low-level input voltage
IOH
IOL
TYP
MAX
3.6
TYP
3
3.6
2
0
VCC
5.5
0
VCC
V
5.5
V
–8
–12
High-level output current (B port)
–24
–32
Low-level output current (A port)
8
12
Low-level output current (B port)
24
32
Low-level output current;
current duty cycle ≤ 50%; f ≥ 1 kHz (B port)
48
64
10
10
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
–55
Outputs enabled
–40
mA
mA
ns/V
µs/V
200
125
V
0.8
High-level output current (A port)
∆t/∆v
UNIT
V
0.8
Input voltage
MAX
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
electrical characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
VIK
A port
VOH
VCC = 2.3 V,
VCC = 2.3 V to 2.7 V,
II = –18 mA
IOH = –100 µA
3V
VCC = 2
2.3
IOH = –6 mA
IOH = –8 mA
VCC = 2.3 V to 2.7 V,
B port
VCC = 2
2.3
3V
VCC = 2.3 V to 2.7 V,
A port
VCC = 2
2.3
3V
VCC = 2.3 V to 2.7 V,
VOL
B port
3V
VCC = 2
2.3
Control inputs
VCC = 2.7 V,
VCC = 0 or 2.7 V,
A or B ports
VCC = 2.7 V
II
Ioff
IBHL‡
IBHH§
IBHLO¶
IBHHO#
IEX||
SN54ALVTH162245
MIN TYP†
MAX
TEST CONDITIONS
SN74ALVTH162245
MIN TYP†
MAX
–1.2
–1.2
VCC–0.2
1.7
VCC–0.2
VCC–0.2
1.7
VCC–0.2
1.7
IOH = –100 µA
IOH = –6 mA
IOH = –8 mA
IOL = 100 µA
V
V
1.7
0.2
IOL = 6 mA
IOL = 12 mA
0.4
IOL = 100 µA
IOL = 6 mA
0.2
0.2
0.4
0.2
0.4
IOL = 8 mA
IOL = 18 mA
0.5
IOL = 24 mA
VI = GND
±1
±1
VI = 5.5 V
VI = 5.5 V
10
10
20
20
VI = VCC
VI = 0
1
1
–5
–5
V
0.4
0.5
VCC = 0,
VCC = 2.3 V,
VI or VO = 0 to 4.5 V
VI = 0.7 V
VCC = 2.3 V,
VCC = 2.7 V,
VI = 1.7 V
VI = 0 to VCC
VCC = 2.7 V,
VCC = 2.3 V,
VI = 0 to VCC
VO = 5.5 V
±100
115
–10
µA
µA
115
µA
–10
µA
300
300
µA
–300
–300
µA
125
125
µA
±100
±100
µA
IOZ(PU/PD)k
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don’t care
VCC = 2.7 V,
IO = 0,
VI = VCC or GND
Outputs high
0.04
0.1
0.04
0.1
ICC
Outputs low
2.3
4.5
2.3
4.5
Outputs disabled
0.04
0.1
0.04
0.1
VCC = 2.5 V,
VCC = 2.5 V,
VI = 2.5 V or 0
VO = 2.5 V or 0
3.5
Ci
UNIT
3.5
mA
pF
Cio
8
8
pF
† All typical values are at VCC = 2.5 V, TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
|| Current into an output in the high state when VO > VCC
k High-impedance state during power up or power down
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
electrical characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
VIK
A port
VOH
VCC = 3 V,
VCC = 3 V to 3.6 V,
II = –18 mA
IOH = –100 µA
VCC = 3 V
IOH = –8 mA
IOH = –12 mA
VCC = 3 V to 3.6 V,
B port
VCC = 3 V
VCC = 3 V to 3.6 V,
A port
VCC = 3 V
VCC = 3 V to 3.6 V,
VOL
B port
VCC = 3 V
Control inputs
VCC = 3.6 V,
VCC = 0 or 3.6 V,
A or B ports
VCC = 3.6 V
II
Ioff
IBHL‡
IBHH§
IBHLO¶
IBHHO#
IEX||
SN54ALVTH162245
MIN TYP†
MAX
TEST CONDITIONS
SN74ALVTH162245
MIN TYP†
MAX
–1.2
–1.2
VCC–0.2
2
VCC–0.2
VCC–0.2
2
VCC–0.2
2
IOH = –100 µA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
UNIT
V
V
2
0.2
IOL = 8 mA
IOL = 12 mA
?
IOL = 100 µA
IOL = 24 mA
0.2
0.2
0.8
0.2
0.5
IOL = 32 mA
IOL = 48 mA
V
0.5
0.55
IOL = 64 mA
VI = VCC or GND
0.55
±1
±1
VI = 5.5 V
VI = 5.5 V
10
10
20
20
VI = VCC
VI = 0
1
1
–5
–5
VCC = 0,
VCC = 3 V,
VI or VO = 0 to 4.5 V
VI = 0.8 V
VCC = 3 V,
VCC = 3.6 V,
VCC = 3.6 V,
VCC = 3 V,
±100
µA
µA
75
75
µA
VI = 2 V
VI = 0 to VCC
–75
–75
µA
500
500
µA
VI = 0 to VCC
VO = 5.5 V
–500
–500
µA
IOZ(PU/PD)k
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don’t care
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
∆ICCh
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VCC = 3.3 V,
VCC = 3.3 V,
125
125
µA
±100
±100
µA
Outputs high
0.07
0.1
0.07
0.1
Outputs low
3.2
5
3.2
5
0.07
0.1
0.07
0.1
Outputs disabled
VI = 3.3 V or 0
VO = 3.3 V or 0
0.2
3.5
0.2
3.5
mA
mA
pF
Cio
8
8
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
|| Current into an output in the high state when VO > VCC
k High-impedance state during power up or power down
h This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
switching characteristics over recommended operating free-air temperature range, CL = 30 pF,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
B
tPLH
tPHL
B
A
tPZH
tPZL
OE
A
tPZH
tPZL
OE
B
OE
A
OE
B
tPHZ
tPLZ
tPHZ
tPLZ
SN54ALVTH162245
SN74ALVTH162245
MIN
MAX
MIN
MAX
0.3
3.6
0.3
3.6
0.5
3.5
0.5
3.5
1.1
4.3
1.1
4.3
1.1
3.8
1.1
3.8
2
5.6
2
5.6
1.8
4.4
1.8
4.4
1.5
5.1
1.5
5.1
1.5
4.1
1.5
4.1
1.9
4.9
1.9
4.9
1.5
4.3
1.5
4.3
1.9
4.8
1.9
4.8
1.5
4.1
1.5
4.1
UNIT
ns
ns
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
B
tPLH
tPHL
B
A
tPZH
tPZL
OE
A
tPZH
tPZL
OE
B
OE
A
OE
B
tPHZ
tPLZ
tPHZ
tPLZ
SN54ALVTH162245
SN74ALVTH162245
MIN
MAX
MIN
MAX
0.5
3.1
0.5
3.1
0.5
3
0.5
3
1
3.7
1
3.7
1
3.4
1
3.4
1.4
4.7
1.4
4.7
1.4
3.9
1.4
3.9
1
3.8
1
3.8
0.7
3.4
0.7
3.4
2.4
5
2.4
5
2.6
4.9
2.6
4.9
2.4
4.7
2.4
4.7
2.3
4.8
2.3
4.8
UNIT
ns
ns
ns
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
30 pF
50 pF
VCC
2.5 V ±0.2 V
3.3 V ±0.3 V
LOAD CIRCUIT
V∆
0.15 V
0.3 V
RL
500 Ω
500 Ω
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
Output
VCC/2
VOL
tPHL
VCC/2
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VOH
Output
VCC/2
tPZL
VOH
VCC/2
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
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MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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