TI SN74ABT16843DL

SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MAY 1997
D
D
D
D
D
D
D
SN54ABT16843 . . . WD PACKAGE
SN74ABT16843 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Impedance State During Power Up
and Power Down
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), 300-mil Shrink
Small-Outline (DL) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
1CLR
1OE
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2OE
2CLR
description
The ’ABT16843 18-bit bus-interface D-type
latches are designed specifically for driving highly
capacitive or relatively low-impedance loads.
They are particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The ’ABT16843 can be used as two 9-bit latches
or one 18-bit latch. The 18 latches are transparent
D-type latches. The device provides true data at
its outputs.
A buffered output-enable (OE) input can be used
to place the nine outputs in either a normal logic
state (high or low logic levels) or a
high-impedance state. The outputs are in the
high-impedance state during power up and power
down. The outputs remain in the high-impedance
state while the device is powered down. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
need for interface or pullup components.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1LE
1PRE
1D1
GND
1D2
1D3
VCC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2PRE
2LE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MAY 1997
description (continued)
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16843 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16843 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit latch)
INPUTS
2
PRE
CLR
OE
LE
D
OUTPUT
Q
L
X
L
X
X
H
H
L
L
X
X
L
H
H
L
H
L
L
H
H
L
H
H
H
H
H
L
L
X
Q0
X
X
H
X
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MAY 1997
logic diagram (positive logic)
1OE
1PRE
1CLR
1LE
2
55
1
56
S2
1D1
C1
54
3
1Q1
1D
R
To Eight Other Channels
2OE
2PRE
27
30
28
2CLR
29
2LE
S2
2D1
C1
42
1D
15
2Q1
R
To Eight Other Channels
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT16843 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT16843 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT16843
MIN
MAX
4.5
5.5
4.5
5.5
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
–55
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
MAX
VCC
VIH
High-level input voltage
SN74ABT16843
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC
–24
V
V
0.8
0
UNIT
VCC
–32
V
V
mA
48
64
mA
10
10
ns/V
µs/V
200
125
–40
85
°C
SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
VCC = 4
4.5
5V
MIN
TA = 25°C
TYP†
MAX
SN54ABT16843
MIN
–1.2
MAX
SN74ABT16843
MIN
–1.2
–1.2
2.5
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
IOL = 64 mA
II
IOZPU‡
V
V
0.55
0.55*
0.55
100
VCC = 0 to 5.5 V,
VI = VCC or GND
UNIT
2
0.55
Vhys
MAX
V
mV
±1
±1
±1
µA
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE = X
±50
±50
±50
µA
IOZPD‡
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE = X
±50
±50
±50
µA
IOZH
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE ≥ 2 V
10
10
10
µA
IOZL
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE ≥ 2 V
–10
–10
–10
µA
±100
µA
Ioff
ICEX
IO§
Outputs high
VCC = 0,
VCC = 5.5 V,
VI or VO ≤ 4.5 V
VO = 5.5 V
VCC = 5.5 V,
VO = 2.5 V
±100
50
–50
–100
Outputs high
ICC
Outputs low
Outputs disabled
5 5 V,
V IO = 0,
0
VCC = 5.5
VI = VCC or GND
∆ICC¶
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
Ci
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
Co
–180
50
–50
–180
–50
50
µA
–180
mA
0.5
0.5
85
85
0.5
85
0.5
0.5
0.5
1.5
1.5
1.5
mA
mA
3.5
pF
8
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ This parameter is characterized, but not production tested.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MAY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time,
time data before LE↓
th
time data after LE↓
Hold time,
SN54ABT16843
MAX
MIN
MAX
SN74ABT16843
MIN
CLR low
3.3
3.3
3.3
PRE low
3.3
3.3
3.3
LE high
3.3
3.3
3.3
High
0.9
0.9
0.9
Low
0.6
0.6
0.6
High
1.7
1.7
1.7
Low
1.8
1.8
1.8
UNIT
MAX
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Q
tPLH
tPHL
PRE
Q
tPLH
tPHL
CLR
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
PARAMETER
VCC = 5 V,
TA = 25°C
SN54ABT16843
MIN
TYP
MAX
MIN
MAX
MIN
MAX
1.6
3.1
4.2
1.6
5.1
1.6
4.8
1.6
3.2
4.2
1.6
5
1.6
4.8
2.3
4
5
2.3
6.3
2.3
5.9
2.5
3.9
4.8
2.5
5.6
2.5
5.3
2.1
4
5.1
2.1
6.3
2.1
6.1
2.2
3.7
4.6
2.2
5.3
2.2
5
1.9
3.7
4.8
1.9
5.7
1.9
5.4
2.2
4.2
5.3
2.2
6.1
2.2
6
1.6
3.3
4.3
1.6
5.5
1.6
5.4
2
3.2
4.6
2
5.9
2
5.8
1.7
4
5.5
1.7
6.4
1.7
6.3
1.7
3.7
4.4
1.7
5.3
1.7
5.2
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303
SN74ABT16843
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
ns
ns
SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
0V
1.5 V
1.5 V
VOL
tPLH
tPHL
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
VOH
Output
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated