We make the parts that set creative people free Features General Description The AL1201 stereo DAC is a high performance 24-bit digital to analog audio converter. Dynamic range is 107dB (Aweighted). The sensible pinout and easy user interface are unprecedented. The part contains an internal high quality phaselocked loop that eliminates the need for external high frequency clocks. G G G G G G G G G G G G 1 OUTL- 16 G 24 bit conversion 107dB dynamic range (A-wt) .003% THD at full scale output linear phase analog outputs 128x over sampling, 5th order 1 bit ∆-Σ modulator 2nd order switched cap filter and 2nd order continuous-time filter on chip sample rate variable 24kHz-55kHz selectable deemphasis (15us/50µs at Fs=44.1kHz) total power consumption 170mW (Fs=48kHz) internal PLL derives all necessary timing signals from external Fs clock serial input bit-rate, selectable 32/24 bits/frame full scale differential output = +/-4V ([OUT+]-[OUT-]) 5V operation OUTL+ OUTROUTR+ AGND MID REF+ VA REF- AGND VD DGND DIN 9 8 FORMAT DEM WDCLK 16 pin SOIC 150 mils wide Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com DS1201-0702 Pin Description Pin # Name 1 OUTL2 OUTL+ 3 AGND REF+ 4 5 REFVD 6 7 DIN 8 FORMAT 9 WDCLK 10 DEM 11 DGND 12 AGND Pin Type OUTPUT OUTPUT GND PWR GND PWR INPUT INPUT INPUT INPUT GND GND 13 VA PWR 14 15 16 MID OUTR+ OUTR- OUTPUT OUTPUT OUTPUT Description negative analog output, left channel positive analog output, left channel analog ground positive reference, 5V, connect .1µ bypass cap to REFnegative reference, connect to GND digital supply, 5V, connect .1µ bypass cap to GND serial data input format select, 0=32 bits/frame, 1=24bits/frame sample frequency wordclock deemphasis select, 0=no deem, 1=deem digital ground analog ground analog supply, 5V, input, connect .1µ bypass cap to GND MID reference output, connect .1µ cap to GND positive analog output, right channel negative analog output, right channel Dimensions (Typical) Inches Millimeters C B 16 9 1 8 A B C D E F G H J K L A 7° nom K 4° nom D H E J L G .389” .154” .236” .100” .008” .025” .050” .017” .011” .170” .033” Notes: Dimension “A” does not include mold flash, protrusions or gate burrs. F DS1201-0702 Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -2- 9.88 3.91 5.99 2.50 0.20 0.64 1.27 0.42 0.27 4.32 0.83 Analog Characteristics (Ta=25°C, VA=VD=VREF=5V, Fs=48kHz, input=1kHz 24 bit data, measurement bandwidth=20Hz20kHz, unless otherwise specified) Parameter Dynamic Range THD+N Crosstalk Output voltage Max. output current Output impedance Power supply current REF current Power consumption Gain Error PSRR Comments output=-60dBFS (A-wt) output= 0dBFS output=-20dBFS output=-60dBFS output= 0dBFS [OUT+]-[OUT-]1 Fullscale interchannel match differential dc offset common mode dc bias Min differential analog (IA) digital (ID) IREF2 Typ 107 -90 -84 -44 -118 +/-4.0 .05 1 2.5 +/-0.4 3 28 6 190 170 REF+ held at 5V REF+ held at 5V Max +/-.69 70 Units dB dB dB dB dB V dB mV V mA Ohm mA mA µA mW % dB Note 1: Output voltage scales linearly with reference potential ([REF+]-[REF-]) Note 2: REF current scales with Fs. Combined Digital and Analog Filter Characteristics (Ta=25°C, VA=VD=VREF=5V, Fs48kHz) Parameter Passband Stopband Group delay Deemphasis Filter Comments +/-0.1dB BW1 Ripple Frequency1 Attenuation Fs=44.1kHz ‘pole’ time constant ‘zero’ time constant Min 0 Typ Max 21.77K +/-.007 28.5 Units Hz dB Hz dB 1/Fs 50 15 µs µs 26.23k -70 Note 1: passband, stopband, and deemphasis frequencies scale with Fs. DS1201-0702 Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -3- Recommended Operating Conditions (GNDA=GNDD=0V) Parameter VA VD Ta Fs rl Comments analog supply voltage digital supply voltage ambient temperature sample frequency differential load resistance Electrical Characteristics – Digital Pins (Ta=25°C) Parameter Comments INPUTS (WDCLK, DIN, DEM, FORMAT) Vih Logical “1” input voltage Voh Logical “0” input voltage Iin input leakage current Cin input capacitance DS1201-0702 Min 4.5 4.5 0 24 12K Typ 5.0 5.0 25 48 Max 5.5 5.5 70 55 Units V V °C kHz Ohm Min Typ Max Units .1VD 1 V V µA pF 0.55VD 5 Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -4- System Description Serial Interface and Timing Input Logic Levels The AL1201 receives its 2’s complement serial data in a standard MSB-first format. Two bit-rates are allowed for. The 32 bits/frame (FORMAT low) is suitable for use in systems where a 256Fs master clock is present. The 24 bits/frame (FORMAT high) is convenient when interfacing with systems where a 384Fs clock is present. The AL1201 can properly receive input logical ‘1’ voltages of .55VD. This means the AL1201 can interface directly with logic signals supplied from 3.3V systems. No special interface circuitry is required. The input sample period is defined between rising edges of wordclock (WDCLK) input. Nominally, this is a 50% duty-cycle clock at frequency Fs, but it can be a pulse with Ts/256 < pulse-width < Ts (255/256); Ts=1/Fs. Left channel data is presented to the AL1201 with rising edge of WDCLK, and right channel data is presented Ts/2 seconds later (when WDCLK falls if 50% duty cycle). The AL1201 contains an internal PLL that locks to the rising edge of WDCLK and produces all necessary high frequency clocks and timing signals to operate the device. This high quality PLL will reject any high-frequency jitter on the incoming wordclock (jitter rejection corner approx. 4kHz). Internal Phase-Locked Loop (PLL) The PLL allows a simplified user interface and eliminates the need of running high frequency clocks on PCB traces to the part. This reduces unwanted RF noise and coupling problems that can occur when these clocks are required as input pins for a device. The serial bits are clocked into the AL1201 input registers on the falling edge of an internally generated bit clock (rising edge aligned with rising edge of WDCLK) that runs at 64Fs when FORMAT is low (32 bits/frame), or 48Fs when FORMAT is high (24 bits/frame). The input data should be valid +/-100ns from the falling edge of this internally generated clock. See timing diagram next page. DS1201-0702 Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -5- Serial Input Formats Right Channel Left Channel WDCLK (Fs, 50% duty cycle shown) DIN, 32 bits/frame 23 DIN, 24 bits/frame 23 0 Don't Care 23 0 0 23 0 Timing Example 32 bits/frame WDCLK (Fs, 50% duty cycle shown) LEFT RIGHT 64Fs bitclk (internal) DIN VALID 100ns100ns VALID 100ns100ns Ts/128 VALID VALID 100ns100ns 100ns100ns Ts/128 Ts/64 Ts/64 24 bits/frame WDCLK (Fs, 50% duty cycle shown) LEFT RIGHT 48Fs bitclk (internal) DIN VALID 100ns100ns VALID 100ns100ns Ts/96 DS1201-0702 VALID 100ns100ns VALID 100ns100ns Ts/96 Ts/48 Ts/48 Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -6- Don't Care Differential Analog Outputs The AL1201 outputs are self-biased to MID potential. Maximum differential output signal level is +/-4V. The outputs have been internally filtered to reduce out-of-band noise, and further filtering is suggested where this is considered critical. The differential-to-single-ended filter shown is a two-pole 48kHz lowpass filter whose frequency response is flat from dc to 20kHz +/-.03dB. Its group delay deviation from flat is 1.3µs at 20kHz. High quality ceramic or film capacitors suggested. 8.2k 4Vpp 390p MID 10 +µ IN- 1.8k 8.2k Out 1000p 10 +µ IN+ + 1.8k 8.2k 8Vpp GND 4Vpp MID 8.2k 390p GND GND Differential to Single-ended Converter and 2-pole 48kHz lowpass filter Reference and Mid Power Supplies and Ground The differential potential between the REF+ and REF- pins (connected to VA and GND respectively) determines the amount of charge that is added to or removed from the switched-capacitor filter input for each ∆-Σ modulator output (128Fs). It is very important that REF+ is well bypassed to REF- (.1µF ceramic as close as possible to pins) to remove the unwanted effects of high frequency noise. A single low-impedance 5V supply is all that is required to achieve specified performance. A 5V supply plane is recommended if possible. VA and VD can be directly connected to 5V, and REF+ should be isolated with a 220-ohm resistor to 5V. A single low impedance ground plane can be used for all GND connections, simplifying PCB layout. Each supply pin should be bypassed to GND with a .1µF ceramic cap positioned as close to the pin as possible. The MID potential is developed on chip (VA/2 volts) and is used to bias the internal amplifiers in the switched-capacitor and continuous-time filters. It requires a .1µF bypass to GND at the pin. No load current should be taken from the MID pin. DS1201-0702 Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -7- 1 OUTL- OUTR- 16 OUTPUT Conditioning OUTPUT Conditioning LEFT OUT 2 3 GND OUTR+ OUTL+ MID AGND RIGHT OUT 15 14 0.1µ* GND +5V +5V 4 220Ω VA REF+ 13 0.1µ* 0.1µ* 5 REF- AGND 12 GND GND 6 VD DGND 11 DEM 10 GND 0.1µ* DIN 7 DIN DEM GND FORMAT 8 FORMAT WDCLK 9 WDCLKIN 24-bit DAC Suggested Connections * Position caps as close to pins as possible DS1201-0702 Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -8- NOTICE Alesis Semiconductor reserves the right to make changes to their products or to discontinue any product or service without notice. All products are sold subject to terms and conditions of sale supplied at the time of order acknowledgement. Alesis Semiconductor assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Information contained herein is only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, no responsibility is assumed for inaccuracies. Alesis Semiconductor products are not designed for use in applications which involve potential risks of death, personal injury, or severe property or environmental damage or life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. All trademarks and registered trademarks are property of their respective owners. Contact Information: Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone: (310) 301-0780 Fax: (310) 306-1551 Email: [email protected] Copyright 2002 Alesis Semiconductor Datasheet July 2002 Reproduction, in part or in whole, without the prior written consent of Alesis Semiconductor is prohibited. DS1201-0702 Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -9-