ES2838 V.90/V.92 PCI HSP Modem Product Brief ESS Technology, Inc. FEATURES DESCRIPTION The ES2838 is a high-performance, single-chip, host-based modem solution that delivers high connectivity and throughput without the need for a dedicated DSP. With the addition of an external transformer DAA, the ES2838 TeleDrive modem chip provides a very low-cost modem solution for add-in cards, desktops, and notebooks. The ES2838 modem is capable of send/receive data and fax and supports telephone answering machine (TAM), and is capable data/fax/voice call discrimination. With its built-in ACPI and D3cold wake-on-ring support, the ES2838 is an ideal modem solution for notebooks and battery-operated devices. • V.90/V.92 analog data/fax/TAM modem • Data mode capabilities: —– —– V.90/V.92: 56 kbps ITU-T V.34: 33.6 kbps and fallbacks • Fax mode capabilities: —– —– ITU-T V.17, V.29, V.27ter, and V.21ch2 Group 3 (TIA/EIA-578 Class 1 and Class 2) • Requires minimum 166-MHz Pentium with MMX technology • PC99/PC2001-compliant with support for V.250, V.251, and V.253 commands V.80 (H.324 software-stack -compatible) Buzzer generator feature generates oscillation on handshaking Caller ID Data/fax/voice call discrimination Worldwide homologation Compliance with ACPI 1.0 and PCI Power Management Interface 1.0, supporting the D3cold wake-on-ring The ES2838 includes a PCI bus interface and a codec. It also includes ADC and DAC conversion of modem/voice signal data and provide the interface and control logic needed to transfer data between its serial I/O terminals and the PCI interface. The ES2838 ADC and DAC operate synchronously so that data reception at the ADC channel and data transmission from the DAC channel occur during the same time interval. • • • • • • The ES2838 modem solution meets all the requirements Microsoft WHQL certification, as well as V.250, V.251, and V.253 commands. • 16-bit ADC and DAC with built-in anti-aliasing and The ES2838 is available in a 100-pin low-profile quad flat pack (LQFP) package. • • • • • • reconstruction filters Separate analog (5V) and digital (3.3V with 5V-tolerant input pads) power supplies Internal PLL requiring a lower-frequency crystal for 18.816-MHz input EEPROM interface for subsystem vendor ID Supports Microsoft Windows Unimodem V and TAPI specifications Supports Microsoft Windows 98/SE/ME/2000 Supports Microsoft Windows NT 4.0 SYSTEM BLOCK DIAGRAM Figure 1 shows the ES2838 system block diagram. MINI-PCI OR PCI BUS ES2838 V.90 HSP MODEM TRANSFORMER DAA PHONE LINE SERIAL EEPROM Figure 1 ES2838 System Block Diagram ESS Technology, Inc. SAM0316-041101 1 ES2838 PRODUCT BRIEF PINOUT VDD GND OSCO OSCI VDD DSPK /PF11 CLKRUN # DPBX # COMPLX# CURLIM# GND O F FHO OK / P F6 GND AVDD PF1 NC NC NC NC AGND 100-Pin LQFP PF5 PF4 LCS/PF3 PF2 VDD SECS SECLK SEDI SEDO GND AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VDD CBE0# AD8 AD9 AD10 AD11 AD12 AD13 GND AD15 AD14 FRAME# GND IR DY# TR DY# D E V S EL # STOP# P AR CB E1 # AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 VDD CBE2# CBE3# VDD ES2838S 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TXN TXP AGND AVDD VAUX RING_IN/PF0 PME# VAUXP RST# INTA# VDD PCICLK GND AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 IDS EL GND NC AGND AGND 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC VCM VREF RXP RXN Figure 2 shows the ES2838 pinout diagram. Figure 2 ES2838 Pinout Diagram 2 SAM0316-041101 ESS Technology, Inc. ES2838 PRODUCT BRIEF ES2838 PIN DESCRIPTIONS Table 1 lists the ES2838 pin descriptions. Table 1 ES2838 Pin Descriptions Names Pin Numbers I/O Definitions C/BE3:0# 1, 13, 21, 31 I/O Multiplexed bus command/byte enable. These pins indicate cycle type during the address phase of a transaction. They indicate active-low byte enable information for the current data phase during the data phases of a transaction. These pins are inputs during slave operation and outputs during bus mastering operation. 2 I Initialization device select, active-high. Used as a chip select during PCI configuration read and write cycles. GND 3, 15, 22, 41, 52, 61, 91 G Digital ground. VDD 12, 32, 46, 51, 58, 89, 100 P Digital voltage [VDD (3.3V)]. 4:11, 23:30, 33:40, 92:99 I/O Address and data AD31:0. FRAME# 14 I/O Cycle frame, active-low. The current PCI bus master drives this pin to indicate the beginning and duration of a transaction. IRDY# 16 I/O Initiator ready, active-low. The current PCI bus master drives this pin to indicate that as the initiator it is ready to transmit or receive data (and complete the current data phase). TRDY# 17 I/O Target ready pin, active-low. The current PCI bus master drives this pin to indicate that as the target device it is ready to transmit or receive data (and complete the current data phase). DEVSEL# 18 I/O Device select, active-low. The PCI bus target device drives this pin to indicate that it has decoded the address of the current transaction as its own chip select range. STOP# 19 I/O Stop transaction, active-low. The current PCI bus target drives this pin active to indicate a request to the master to stop the current transaction. PAR 20 I/O Parity pin, active-high. Indicates even parity across AD[31:0] and C/BE[3:0]# for both address and data phases. The signal is delayed one PCI clock from either the address or data phase for which parity is generated. SEDO 42 I Serial EPROM data output pin with internal pullup. SEDI 43 O Serial EPROM data input pin. SECLK 44 O Serial EPROM data clock input pin with internal pulldown. SECS 45 O Serial EPROM port chip select pin with internal pulldown. LCS / PF3 48 I Local current sense input when selected. PF[5:4] and PF[2:1] 47, 49, 50, 64 I/O General-purpose programmable bidirectional flag. Can be used for interfacing with a telephone or other device, performing such functions as phone off-hook, phone on-hook, ring, and caller ID. CURLIM# 53 O Current limit control output. COMPLX# 54 O Complex impedance select output. DPBX# 55 I Digital PBX detection input. CLKRUN# 56 I/O PCI clock state for power management. O Modem speaker digital output. O General-purpose programable flag. IDSEL AD31:0 DSPK PF11 57 OSCI 59 I 18.816-MHz crystal oscillator input. OSCO 60 O 18.816-MHz crystal oscillator output. ESS Technology, Inc. SAM0316-041101 3 ES2838 PRODUCT BRIEF Table 1 ES2838 Pin Descriptions (Continued) Names Pin Numbers OFFHOOK I/O Definitions O Offhook output driving 5V. O General-purpose programmable flag. 65, 82 P Analog voltage pins [AVDD (5V)]. NC 66, 67, 69, 70, 75, 76 — No connect. AGND 68, 77, 78, 81 G Analog ground. RXN 71 I Codec analog differential negative input. The DC level is Vcm, and the full-scale input is either 0.22 Vp-p ±5% or 1.1 Vp-p±5%, depending on the gain setting. RXP 72 I Codec analog differential positive input. The DC level is Vcm, and the full-scale input is either 0.22 Vp-p ±5% or 1.1 Vp-p±5%, depending on the gain setting. VREF 73 O Voltage reference bypass. Has a range of 1.2356V±5%. Bypass to AGND with 0.1-µF ceramic chip capacitor parallel with 10-µF tantalum capacitor. VCM 74 O Common mode voltage bypass. Has a range of 2.16V±5%. Bypass to AGND with 0.1-µF ceramic chip capacitor parallel with 10-µF tantalum capacitor. TXN 79 O Codec negative analog output. The DC level is Vcm, and the full-scale ac output is 2.8V p-p±5%. The maximum loading is 1k Ω in parallel with 20 pF for modem applications. For audio applications with low-impedance load, the maximum distortion-free (THD <–60 db) current is 10 mA rms. TXP 80 O Codec positive analog output. The DC level is Vcm, and the full-scale ac output is 2.8V p-p±5%. The maximum loading is 1k Ω in parallel with 20 pF for modem applications. For audio applications with low-impedance load, the maximum distortion-free (THD <–60 db) current is 10 mA rms. VAUX 83 P Power to device during implementation of the D3cold state required by PCI Power Management Interface specification. I RING_IN function, using a Schmitt trigger. O General-purpose programable flag. PF6 AVDD 63 RING_IN PF0 84 PME# 85 O Power management enable interrupt output to wake up the system. VAUXP 86 I VAUX support detection pin. VAUXP pin is driven high to indicate that ACPI is supported with D3cold state. No support when driven low. RST# 87 I Active-low ES2838 reset input. INTA# 88 O Interrupt request, active-low. The level triggered interrupt pin dedicated to servicing internal device interrupt sources. PCICLK 90 I System bus clock input. ORDERING INFORMATION Part Number ES2838S Description V.90/V.92 PCI HSP Modem ESS Technology, Inc. 48401 Fremont Blvd. Fremont, CA 94538 Tel: (510) 492-1088 Fax: (510) 492-1898 4 Package 100-pin LQFP No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. assumes no responsibility for any errors contained herein. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All other trademarks are owned by their respective holders and are used for identification purposes only. TeleDrive is a registered trademark of ESS Technology, Inc. (P) U.S. patents pending. All specifications are subject to change without prior notice. © 2001 ESS Technology, Inc. All rights reserved. SAM0316-041101