SUMMIT S9408 MICROELECTRONICS, Inc. Serial Input, Quad 8-Bit Nonvolatile DACPOT™ FEATURES • Four 8-Bit DACS – Differential Non-linearity - ±0.5LSB max – Integral Non-Linearity - ±1LSB max • Each DAC has Independent Reference Inputs – Output Buffer Amplifiers Swing Rail-to-Rail – Ground to VDD Reference Input Range • Each DAC’s Digital Input Data Maintained in Nonvolatile EEPROM • Power-On Reset Reloads Registers with Nonvolatile Data • Simple Serial Interface for Reading and Writing DAC values, SPI™ and QSPI™ compatible. • Fully operational from 2.7V to 5.5V OVERVIEW The S9408 DACPOT™ is a serial input, voltage output, quad 8-bit digital to analog converter. The S9408 operates from a single +2.7V to +5.5V supply. Internal precision buffers swing rail-to-rail and the reference input range includes both ground and the positive supply. The S9408 integrates four 8-bit DACs and their associated circuits which include an enhanced unity-gain operational amplifier output, an 8-bit data latch, an 8-bit nonvolatile register, and an industry-standard serial interface for reading and writing data to the DACs’ data latches and registers. The DACs are independently programmable and each has its own electrically isolated Vreference inputs. • Low Power: <1mW @ 2.7V FUNCTIONAL BLOCK DIAGRAM Memory Control 8-Bit E2PROM DAC SECTION 0 VDD 3 RDY/BSY# 4 Serial Data In AMP 8-Bit Data Register CS# 6 DI 7 CLK 5 00/REG# 9 Programming Memory Controller VREFH0 18 VOUT0 11 VREFL0 1 VREFH1 17 VOUT1 12 VREFL1 20 VREFH2 16 VOUT2 13 VREFL2 19 VREFH3 15 VOUT3 14 VREFL3 8 DO 8-Bit DAC Serial Data Out DAC SECTION 1 Control Logic DAC SECTION 2 GND 2 10 DAC SECTION 3 2015 T BD 2.0 © SUMMIT MICROELECTRONICS, Inc. 2000 • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Phone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com Characteristics subject to change without notice 2015 2.2 8/2/00 1 S9408 PINOUT and SIGNAL DEFINITION Pin 20-Pin PDIP or 20-Pin SOIC 1, 2 VREFH 20, 19 3 VREFH1 VREFH0 VDD RDY/BSY# CLK CS# DI DO 00/REG# GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Name 4 VREFH2 VREFH3 VOUT0 VOUT1 VOUT2 VOUT3 VREFL3 VREFL2 VREFL1 VREFL0 2015 T PCon 2.0 The analog outputs of the S9408 can be programmed to any one of 256 individual voltage steps. Each step value is 1/256th of the voltage differential between VREFH and VREFL of the respective DAC. Once programmed these settings can be retained in nonvolatile memory during all power conditions and will be automatically recalled upon a power-up sequence. Each DAC can be independently read without affecting the output voltage during the read cycle. In addition, each output can be adjusted an unlimited number of times without altering the value stored in the nonvolatile memory. DEVICE OPERATION Analog Section The S9804 is an 8-bit, voltage output digital-to-analog converter (DAC). The DAC consists of a resistor network that converts 8-bit digital inputs into equivalent analog output voltages in proportion to the applied reference voltage. Reference inputs The voltage differential between the VREFL and VREFH inputs sets the full-scale output voltage for its respective DAC. VREFL must be equal to or greater than ground (positive voltage). VREFH must be greater (more positive) than VREFL and less than or equal to VDD. VDD Function Vreference High: VREFL < VREFH - VDD Power Supply Voltage RDY/BSY# Ready/Busy: open drain output indicating status of nonvolatile write operations 5 CLK Clock Input Pin: used for serial data communication 6 CS# Chip Select: When high deselects the device and places it in a low power mode 7 DI Data Input: serial data input pin 8 DO Data Output: serial data output pin 9 00/REG# Power On Recall Option Input 10 GND Power Supply Ground 11, 12 13, 14 VREFL Vreference Low: VREFH > VREFL • GND 15, 16 17, 18 VOUT DAC Output: buffered D to A converter output Output Buffer Amplifiers The voltage outputs are precision unity-gain followers that slew up to 1V/µs. The outputs can swing from VREFL to VREFH. With a 0V to 5V output transition the amplifier outputs typically settle to 1LSB in 40µs. DIGITAL INTERFACE The S9408 employs a common 4-wire serial interface. It is comprised of a Clock (CLK), Chip Select (CS#), Data In (DI) and Data Out (DO). Data is clocked into the device on the clock’s rising edge and out of the device on the clock’s falling edge. Data is shifted in and out MSB first. DO only becomes active after the device has been selected and after a valid read command and address has been received. All data transfers are initiated after CS# goes low and a logic ‘1’ is clocked into the device. This first data transfer is the start bit and must precede all operations. Following the start bit are two command bits used to specify which of four commands to execute. The next two bits are the address bits used to select one of the four DACs. The action of the next eight clock cycles will be dependent upon the command issued. 2015 2.2 8/2/00 2 SUMMIT MICROELECTRONICS, Inc. S9408 Start C1 C0 A1 A0 Command 1 0 0 A A NV Write Enable 1 0 1 A A Write — Data In 1 1 0 A A Read — Data Out 1 1 1 A A Recall selected data register. This read will not affect the contents of the register or the output of the DAC. Refer to Figure 1 for an illustration of the sequence of bus conditions for a read operation. TABLE 1. COMMAND FORMAT Internally there are four DACs and associated with each are two registers. There is one data register that is used by the DAC to hold the digital value it converts. There is also one nonvolatile register that holds the default value that can be recalled into the data register during powerup or by executing the Recall command. READ Read operations are initiated by taking CS# low and clocking in a start bit followed by the read command and the address of the data register to be read. The next eight clocks will output on the DO pin the contents of the WRITE Write operations are initiated by taking CS# low and clocking in a start bit followed by the write command and the address of the data register to be written. This action is followed by the host clocking eight bits of data into the register, MSB first. The output of the selected DAC will change as the last bit is clocked into the device. At this point the clock counter will reset the command register, requiring a full sequence to be initiated in order to write to the DAC again. NOTE: This write operation does not affect the contents of the nonvolatile register. Therefore, the nonvolatile register can contain the power-on default settings (e.g. volume), and the write DAC command can be used to make situational adjustments. Refer to Figure 2 for an illustration of the sequence of bus conditions for a write operation. CS# CLK DI S T A R T DO C1 C0 A1 A0 Hi Z D7 D6 D5 D4 D3 D2 D1 D0 Hi Z (Pulled up to VDD) RDY/BSY# FIGURE 1. READ SEQUENCE 2015 2.2 8/2/00 SUMMIT MICROELECTRONICS, Inc. 2015 T fig01 2.0 3 S9408 CS# CLK DI S T A R T C1 C0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi Z DO (Pulled up to VDD) RDY/BSY# VOUT 2015 T fig02 2.0 FIGURE 2. WRITE SEQUENCE Rising Edge Sets NV Write Enable Latch Rising Edge Starts NV Write CS# CLK DI C1 C0 A1 D0 C1 C0 A1 A0 D7 D6 D5 D4 Address and Data are Don’t Care D3 D2 D1 D0 NV Write Enable Latch is Reset RDY/BSY# 2015 T fig03 2.0 FIGURE 3. NONVOLATILE WRITE SEQUENCE NONVOLATILE WRITE A nonvolatile write is a two step operation: it is initiated by taking CS# low and clocking in a start bit followed by the NV Enable command. At this point the host can take CS# back high or continue clocking in data. This data is don’t care and will be ignored by the S9408. If any command other than write follows NV enable the NV latch will be cleared. Next, the host takes CS# low again and issues a write command and address and then clocks in the eight data bits to be programmed. The host will then bring CS# HIGH and the data will be latched into the data register and a nonvolatile write operation will commence. The status of the nonvolatile write can be monitored on the RDY/BSY# pin. A logic low indicates the write is still in progress and the S9408 will not be accessible to the host; a logic high indicates the write has completed and the S9408 is ready for the next command. Refer to Figure 3 for an illustration of the sequence of bus conditions for a nonvolatile write operation. 2015 2.2 8/2/00 4 SUMMIT MICROELECTRONICS, Inc. S9408 RECALL COMMAND The recall command will retrieve data from the selected nonvolatile register and write it into the data register of the associated DAC. This operation is initiated by taking CS# low and clocking in a start bit followed by the recall command and the address of the nonvolatile register to be recalled. The eight bits of data are don’t care, so CS# can be taken high any time after the address bits are clocked in. Refer to Figure 4 for an illustration of the sequence of bus conditions for a Recall operation. Power-on recall Whenever the S9408 is powered on the DAC output values will be returned to the selected default setting. The default setting can be the nonvolatile register contents or all zeroes. The state of the 00/REG# pin will determine which operation will be performed. If it is tied to ground (or left floating) the nonvolatile register contents will be recalled. Conversely, if it is tied to VDD the S9408 will recall zeroes. CS# CLK DI S T A R T C1 C0 A1 A0 VOUT 2015 T fig04 2.0 FIGURE 4. RECALL COMMAND SEQUENCE 2015 2.2 8/2/00 SUMMIT MICROELECTRONICS, Inc. 5 S9408 ABSOLUTE MAXIMUM RATINGS VDD to GND .................................................................... -0.5V to +7V Digital Inputs to GND ............................................ -0.5V to VDD+0.5V Analog Inputs to GND ........................................... -0.5V to VDD+0.5V Digital Outputs to GND ......................................... -0.5V to VDD+0.5V Analog Outputs to GND ........................................ -0.5V to VDD+0.5V Temperature Under Bias ........................................... -55°C to +125°C Storage Temperature ................................................ -65°C to +150°C Lead Soldering (10 Sec Max) .................................................... 300°C RECOMMENDED OPERATING CONDITIONS Condition Temperature VDD Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Min -40°C +2.7V Max +85°C +5.5V 2015 PGM T2 1.2 RELIABILITY CHARACTERISTICS (Over recommended operating conditions unless otherwise specified) Symbol Parameter Min Max Unit VZAP ESD Susceptibility 2000 V ILTH Latch-up 100 mA TDR Data Retention 100 Years NEND Endurance 1,000,000 Storage Cycles DC ELECTRICAL CHARACTERISTICS (Over recommended operating conditions unless otherwise specified) Symbol Parameter Conditions Min Typ Max Unit IDD Supply current during store (note 1) CS = VIL 1.8 23.0 .5 mA ISB Standby supply current CS = VIH 260 500 µA IIH Input leakage current VIN = VDD <1 10 µA IIL Input leakage current VIN = 0V <1 –10 µA VIH High level input voltage 2 VDD V VIL Low level input voltage 0 0.8 V VOH High level output voltage IOH = –400µA VOL Low level output voltage IOL = 1mA, VDD = 5V; IOL = 0.4mA, VDD = 2.7V VDD – 0.3 V 0.4 V Note 1: IDD is the supply current drawn while the EEPROM is being updated. 2015 2.2 8/2/00 6 SUMMIT MICROELECTRONICS, Inc. S9408 AC ELECTRICAL CHARACTERISTICS VDD = +4.5V to +5.5V, VREFH = VDD, VREFL = 0V, TA = -40°C to +85°C, unless otherwise specified Symbol Parameter fC Clock Frequency DC tWH Minimum CLK High Time 500 ns tWL Minimum CLK Low Time 300 ns tCS Minimum CS High Time 150 ns tCSS CS Setup Time 100 ns tCSH CS Hold Time 0 ns tSU Data In Setup Time CL = 100pF 50 ns tH Data In Hold Time See Note 1 50 ns tV Output Valid Time tHO Data Out Hold Time tDIS Output Disable Time 400 tBUSY Write Cycle Time 3.3 Notes: Conditions Min. Typ. Max. Units 1 MHz 150 ns 0 ns ns 5 ms 2015 PGM T5 1.1 1. All timing measurements are defined at the point of signal crossing VDD/2. tCS CS# tCSS tWL tWH tCSH CLK tSU tH DI tV Hi Z tHO tDIS Hi Z DO RDY/BSY# 2015 T fig05 2.0 FIGURE 5. AC TIMING DIAGRAM 2015 2.2 8/2/00 SUMMIT MICROELECTRONICS, Inc. 7 S9408 DAC DC ELECTRICAL CHARACTERISTICS VDD = 2.7V to 5.5V, VREFH = VDD, VREFL = 0V, TA = -40°C to +85°C, unless otherwise specified Property Accuracy Symbol Conditions Min Typ Max Unit INL Integral non-linearity ILOAD = 100µA 0.5 ±1 LSB DNL Differential non-linearity ILOAD = 100µA (note 1) 0.1 ±0.5 LSB VREFH Input voltage VREFL VDD V VREFL Input voltage GND VREFh V Ω VREFH to VREFL resistance 40k TCRIN Temp. coefficient of RIN 300 600 ppm/ºC ∆RIN Input resistance match ±0.5 ±1 % ±1 LSB 5 mV 50 µV/ºC 1000 µA References RIN GEFS Analog Output Parameter Full-scale gain error D = FFHEX VOUTZS Output offset voltage D = 00HEX TCVOUT VOUT temp. coeffiecient VDD = 5V, ILOAD = 50µA (note 1) 0 2.5 IL Amp output load current ROUT Amp output resistance ILOAD = 100µA PSRR Power supply rejection ILOAD = 10µA tS DAC settling time to 1LSB 10pF 10pF 5V 3V 36 27 eN Amp output noise f = 1kHz, VDD = 5V 90 nV√Hz THD Total harmonic distortion VREFH = 2.5V, VDD = 5V, f = 1kHz, VIN = 1VRMS 0.08 % BW Bandwidth –3dB VREFH = 2.5V, VDD = 5V, VIN = 100mVRMS 300 kHz –200 5V 3V Ω Ω 10 20 1 LSB/V 40 35 µs µs Note 1: Guaranteed but not tested 2015 2.2 8/2/00 8 SUMMIT MICROELECTRONICS, Inc. S9408 20 Pin SOIC (.300) Package 0.496 - 0.512 (12.598 - 13.005) 0.394 - 0.419 (10.007 - 10.643) 0.291 - 0.299 (7.391 - 7.595) 0.010 - 0.029 0.093 - 0.104 0.037 - 0.045 (2.362 - 2.642) x45° (0.940 - 1.143 (0.254 - 0.737) 0° to 8° typ 0.009 - 0.013 0.016 - 0.050 0.050 (0.229 - 0.330) (0.406 - 1.270) (1.270) 0.004 - 0.012 0.014 - 0.019 (0.102 - 0.305) (0.356 - 0.482) 20pn SOIC ILL.1 41.5 2015 T fig06 2.0 RESISTANCE (kΩ) 41.0 40.5 40.0 VL = GND VH = 5.5V VH = 4.5V VH = 2.7V 39.5 39.0 –40 25 90 TEMPERATURE (ºC) FIGURE 6. VL to VH END-TO-END RESISTANCE OVER TEMPERATURE 2015 2.2 8/2/00 SUMMIT MICROELECTRONICS, Inc. 9 S9408 ORDERING INFORMATION S9408 Base Part Number P Package P = 20 Pin PDIP * S = 20 Pin SOIC * Special order 2015 Tree 2.0 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2000 SUMMIT Microelectronics, Inc. 2015 2.2 8/2/00 10 SUMMIT MICROELECTRONICS, Inc.