ETC C8051F236

C8051F236
8K Flash, 1.25K RAM, 48-Pin MCU
PRELIMINARY
ANALOG PERIPHERALS
Two Comparators
- Programmable Hysteresis
- Configurable to Generate Interrupts or Reset
VDD Monitor and Brown-out Detector
ON-CHIP JTAG DEBUG
- On-Chip Debug Circuitry Facilitates Full Speed,
Non-Intrusive In-System Debug (No Emulator
Required!)
- Provides Breakpoints, Single Stepping,
Watchpoints, Stack Monitor
- Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using
ICE-Chips, Target Pods, and Sockets
- Low Cost, Complete Development Kit
SUPPLY VOLTAGE ......................2.7V to 3.6V
- Typical Operating Current: 9mA @ 25MHz
- Typical Stop Mode Current: <0.1uA
Temperature Range: –40°°C to +85°°C
48-Pin TQFP Package
8051-COMPATIBLE µC Core
- Pipelined Instruction Architecture; Executes 70%
of Instructions in 1 or 2 System Clocks
- Up to 25MIPS Throughput with 25MHz Clock
- Expanded Interrupt Handler
MEMORY
- 1280 Bytes Internal Data RAM (256 + 1k)
- 8k Bytes FLASH; In-System Programmable in 512
byte Sectors
DIGITAL PERIPHERALS
- 32 Port I/O; All are 5V tolerant
TM
- Hardware SPI and UART Serial Ports Available
Concurrently
- Three 16-bit Counter/Timers
- Dedicated Watch-Dog Timer
- Bi-directional Reset
CLOCK SOURCES
- Internal Programmable Oscillator: 2-to-16MHz
- External Oscillator: Crystal, RC, C, or Clock
- Can Switch Between Clock Sources on-the-fly;
Useful in Power Saving Modes
SPI is a trademark of Motorola, Inc.
VDD
VDD
Analog/Digital
Power
Port 0
Latch
GND
GND
NC
NC
NC
P
0
UART
M
U
X
Timer 0
Timer 1
P
0
D
r
v
P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
Timer 2
TCK
TMS
TDI
TDO
JTAG
Logic
Debug HW
Reset
/RST
MONEN
VDD
Monitor
XTAL1
XTAL2
External
Oscillator
Circuit
Internal
Oscillator
8
0
5
1
WDT
System Clock
C
o
r
e
8kbyte
FLASH
Port 1
Latch
CP0+
256 byte
RAM
CP0
CP0
CP0CP1+
CP1
CP1
1024 byte
XRAM
SFR Bus
CP1-
P
1
M
U
X
P
1
D
r
v
P1.0/CP0+
P1.1/CP0P1.2/CP0
P1.3/CP1+
P1.4/CP1P1.5/CP1
P1.6/SYSCLK
P1.7
SYSCLK
Port 2
Latch
SPI
P
2
P
2
M
U
X
D
r
v
P
3
Port 3
Latch
D
r
v
P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
NC
7.15.2002
C8051F236
8K Flash, 1.25K RAM, 48-Pin MCU
PRELIMINARY
SELECTED ELECTRICAL SPECIFICATIONS TA = -40°C to +85°C, VDD = 2.7V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
GLOBAL CHARACTERISTICS
Supply Voltage
2.7
3.6
Supply Current (CPU
Clock=25MHz
9
active)
Clock=1MHz
0.4
Clock=32kHz; VDD Monitor Disabled
11
Supply Current (shutdown)
Oscillator not running; VDD Monitor
10
Enabled
Oscillator not running; VDD Monitor
0.1
Disabled
Clock Frequency Range
DC
25
COMPARATORS
Supply Current
(each comparator)
1.5
Response Time
(CP+) – (CP-) = 100mV
4.0
PACKAGE INFORMATION
C8051F226DK DEVELOPMENT KIT
D
MIN NOM MAX
(mm) (mm) (mm)
D1
A
E1
E
-
A1 0.05
-
1.20
-
0.15
A2 0.95 1.00 1.05
b
48
PIN 1
IDENTIFIER
A2
1
0.17 0.22 0.27
D
-
9.00
-
D1
-
7.00
-
e
-
0.50
-
E
-
9.00
-
E1
-
7.00
-
e
A
b
A1
UNITS
V
mA
mA
µA
µA
µA
MHz
µA
µs