Acer Laboratories Inc. --Confidential, Proprietary-- M5232P : RS-232 Chip M5232P : Multiple RS-232 Drivers and Receivers 1. Features n Drivers - Current Limited Output ... 10mA Typical - Power-off Output impedance ... 300ohm Min. - Slew rate control by load capacitor - Flexible Supply Voltage Range - Input compatible with most TTL and DTL circuits n Receivers - Input resistance ..... 3kohm to 7kohm - Input signal range .... ± 30V - Built-in Input Hysteresis 2. Description The ALi's M5232P combines three drivers and five receivers from ASP trade standard AP232 bipolar quadruple drivers and receivers, respectively. The pinout matches the flow through design of the AP232 to decrease the part count, reduce the board space required, and allow easy interconnection of the UART and serial-port connector of IBM PC/AT and compatibles. The bipolar circuits and processing of the M5232P provides a rugged low-cost solution for this function at the expense of quiescent power and external passive components relative to the AP232. The M5232P complies with the requirements of the EIA/TIA 232-D and ITU (formally CCITT) v.28 standards. These standards are for data interchange between a host computer and peripheral at signalling rates up to 20k bits/sec. The switching speeds of the M5232P are fast enough to support rates up to 120 kbps with lower capacitive loads (shorter cables). Interoperability at the higher signalling rates cannot be assured unless the designer has design control of the cable and the interface circuits at both ends. For compatibility with signalling rates to 120 kbps, use of EIA/ITA-423-B (ITU v.10) and EIA/ ITA-422-B (ITU v.11) standards are recommended. The M5232P is operable at the temperature range of 0oC to 75oC. 06-28-1997, Document Number: 5232DS02.doc Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Page 1 Tel: 886-(02) 762-8800 Fax: 762-6060 --Confidential, Proprietary-- Acer Laboratories Inc. M5232P : RS-232 Chip 3. Pin Diagram VDD RA1 RA2 RA3 DY1 DY2 RA4 DY3 RA5 Vss 4. Pin Description Table 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Vcc RY1 RY2 RY3 DA1 DA2 RY4 DA3 RY5 GND 5. Functional Block Diagram Page 2 Pin Name RAx RYx DAx DYx Description Receiver inputs Receiver outputs Driver inputs Driver outputs 6. Logic Diagram RA1 RY1 RA1 RY1 RA2 RY2 RA2 RY2 RA3 RY3 RA3 RY3 DY1 DA1 DY1 DA1 DY2 DA2 DY2 DA2 RA4 RY4 RA4 RY4 DY3 DA3 DY3 DA3 RA5 RY5 RA5 RY5 06-28-1997, Document Number: 5232DS02.doc Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800 Fax: 762-6060