ETC GS816136D-133

Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
This supplemental information applies to the GS816118/36T datasheet, which you will
find attached to this document. This supplement includes a new package offering (the
165-bump BGA—Package D), as well as an additional organization (x32, which is only
offered in the 165 BGA for this part).
1/8
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BB
NC
E3
BW
ADSC
ADV
A
A19
A
B
NC
A
E2
NC
BA
CK
GW
G
ADSP
A
NC
B
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQA
C
D
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
D
E
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
E
F
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
F
G
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
G
H
FT
MCL
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
H
J
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
J
K
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
K
L
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
L
M
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
M
N
DQB
NC
VDDQ
VSS
NC
A18
NC
VSS
VDDQ
NC
NC
N
P
NC
NC
A
A
TDI
A1
TDO
A
A
A
A17
P
R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
2/8
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
165 Bump BGA—x32 Common I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BC
BB
E3
BW
ADSC
ADV
A
NC
A
B
NC
A
E2
BD
BA
CK
GW
G
ADSP
A
NC
B
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
NC
C
D
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
D
E
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
E
F
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
F
G
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
G
H
FT
MCL
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
H
J
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
J
K
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
K
L
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
L
M
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
M
N
NC
NC
VDDQ
VSS
NC
A18
NC
VSS
VDDQ
NC
NC
N
P
NC
NC
A
A
TDI
A1
TDO
A
A
A
A17
P
R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
3/8
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
165 Bump BGA—x36 Common I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BC
BB
E3
BW
ADSC
ADV
A
NC
A
B
NC
A
E2
BD
BA
CK
GW
G
ADSP
A
NC
B
C
DQC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQB
C
D
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
D
E
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
E
F
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
F
G
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
G
H
FT
MCL
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
H
J
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
J
K
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
K
L
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
L
M
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
M
N
DQD
NC
VDDQ
VSS
NC
A18
NC
VSS
VDDQ
NC
DQA
N
P
NC
NC
A
A
TDI
A1
TDO
A
A
A
A17
P
R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
4/8
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
GS816118/32/36D 165-Bump BGA Pin Description
Symbol
Type
Description
A 0, A 1
I
Address field LSBs and Address Counter Preset Inputs
An
I
Address Inputs
A17, A18, A19
I
Address Inputs
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
I/O
Data Input and Output pins
BA , BB , BC , BD
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC
—
No Connect
CK
I
Clock Input Signal; active high
BW
I
Byte Write—Writes all enabled bytes; active low
GW
I
Global Write Enable—Writes all bytes; active low
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active l0w
ADSC, ADSP
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
MCL
—
Must Connect Low
VDD
I
Core power supply
VSS
I
I/O and Core Ground
VDDQ
I
Output driver power supply
5/8
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
Package Dimensions—165-Bump FPBGA (Package D)
A1 CORNER
TOP VIEW
BOTTOM VIEW
Ø0.10 M C
Ø0.25 M C A B
Ø0.40~0.50 (165x)
1 2 3 4 5 6 7 8 9 10 11
A1 CORNER
11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1.0
14.0
15±0.07
1.0
A
B
C
D
E
F
G
H
I
J
K
L
M
N
P
R
A
1.0
1.0
0.15 C
C
SEATING PLANE
B
13±0.07
0.20(4x)
0.25~0.40
1.20 MAX.
(0.26)
0.45±0.05
0.25 C
10.0
6/8
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
Ordering Information
Org
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
1M x 18
GS816118D-250
Pipeline/Flow Through
165 BGA
250/5.5
C
1M x 18
GS816118D-225
Pipeline/Flow Through
165 BGA
225/6
C
1M x 18
GS816118D-200
Pipeline/Flow Through
165 BGA
200/6.5
C
1M x 18
GS816118D-166
Pipeline/Flow Through
165 BGA
166/7
C
1M x 18
GS816118D-150
Pipeline/Flow Through
165 BGA
150/7.5
C
1M x 18
GS816118D-133
Pipeline/Flow Through
165 BGA
133/8.5
C
512K x 32
GS816132D-250
Pipeline/Flow Through
165 BGA
250/5.5
C
512K x 32
GS816132D-225
Pipeline/Flow Through
165 BGA
225/6
C
512K x 32
GS816132D-200
Pipeline/Flow Through
165 BGA
200/6.5
C
512K x 32
GS816132D-166
Pipeline/Flow Through
165 BGA
166/7
C
512K x 32
GS816132D-150
Pipeline/Flow Through
165 BGA
150/7.5
C
512K x 32
GS816132D-133
Pipeline/Flow Through
165 BGA
133/8.5
C
512K x 36
GS816136D-250
Pipeline/Flow Through
165 BGA
250/5.5
C
512K x 36
GS816136D-225
Pipeline/Flow Through
165 BGA
225/6
C
512K x 36
GS816136D-200
Pipeline/Flow Through
165 BGA
200/6.5
C
512K x 36
GS816136D-166
Pipeline/Flow Through
165 BGA
166/7
C
512K x 36
GS816136D-150
Pipeline/Flow Through
165 BGA
150/7.5
C
512K x 36
GS816136D-133
Pipeline/Flow Through
165 BGA
133/8.5
C
1M x 18
GS816118D-250I
Pipeline/Flow Through
165 BGA
250/5.5
I
1M x 18
GS816118D-225I
Pipeline/Flow Through
165 BGA
225/6
I
1M x 18
GS816118D-200I
Pipeline/Flow Through
165 BGA
200/6.5
I
1M x 18
GS816118D-166I
Pipeline/Flow Through
165 BGA
166/7
I
1M x 18
GS816118D-150I
Pipeline/Flow Through
165 BGA
150/7.5
I
1M x 18
GS816118D-133I
Pipeline/Flow Through
165 BGA
133/8.5
I
512K x 32
GS816132D-250I
Pipeline/Flow Through
165 BGA
250/5.5
I
512K x 32
GS816132D-225I
Pipeline/Flow Through
165 BGA
225/6
I
Status
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816136AD-100IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
7/8
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
Ordering Information
Org
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
512K x 32
GS816132D-200I
Pipeline/Flow Through
165 BGA
200/6.5
I
512K x 32
GS816132D-166I
Pipeline/Flow Through
165 BGA
166/7
I
512K x 32
GS816132D-150I
Pipeline/Flow Through
165 BGA
150/7.5
I
512K x 32
GS816132D-133I
Pipeline/Flow Through
165 BGA
133/8.5
I
512K x 36
GS816136D-250I
Pipeline/Flow Through
165 BGA
250/5.5
I
512K x 36
GS816136D-225I
Pipeline/Flow Through
165 BGA
225/6
I
512K x 36
GS816136D-200I
Pipeline/Flow Through
165 BGA
200/6.5
I
512K x 36
GS816136D-166I
Pipeline/Flow Through
165 BGA
166/7
I
512K x 36
GS816136D-150I
Pipeline/Flow Through
165 BGA
150/7.5
I
512K x 36
GS816136D-133I
Pipeline/Flow Through
165 BGA
133/8.5
I
Status
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816136AD-100IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
8/8
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
1M x 18, 512K x 36
18Mb Sync Burst SRAMs
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard package
Pipeline
3-1-1-1
3.3 V
2.5 V
Flow
Through
2-1-1-1
3.3 V
2.5 V
tKQ
tCycle
Curr (x18)
Curr (x36)
Curr (x18)
Curr (x36)
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.4 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
280
330
275
320
255
300
250
295
230
270
230
265
200
230
195
225
185
215
180
210
165
190
165
185
mA
mA
mA
mA
tKQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
Curr (x18)
Curr (x36)
Curr (x18)
Curr (x36)
175
200
175
200
165
190
165
190
160
180
160
180
150
170
150
170
145
165
145
165
135
150
135
150
mA
mA
mA
mA
250 MHz–133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode pin
low places the RAM in Flow Through mode, causing output
data to bypass the Data Output Register. Holding FT high
places the RAM in Pipeline mode, activating the rising-edgetriggered Data Output Register.
SCD Pipelined Reads
The GS816118/36T is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Functional Description
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Applications
Core and Interface Voltages
The GS816118/36T is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
The GS816118/36T operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output
power (VDDQ) pins are used to decouple output noise from the
internal circuits and are 3.3 V and 2.5 V compatible.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be
initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Rev: 2.12 9/2002
1/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
A6
A7
E1
A18
NC
NC
BB
BA
A17
VDD
VSS
CK
GW
BW
G
ADSC
ADSP
ADV
A8
A9
GS816118 100-Pin TQFP Pinout
VDDQ
LBO
A5
A4
A3
A2
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
FT
VDD
NC
VSS
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
1M
X
18
10
71
11
Top View
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.12 9/2002
A19
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
NC
VSS
VDDQ
NC
NC
NC
A1
A0
TMS
TDI
VSS
VDD
TDO
TCK
A10
A11
A12
A13
A14
A15
A16
NC
NC
NC
2/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
A6
A7
E1
A18
BD
BC
BB
BA
A17
VDD
VSS
CK
GW
BW
G
ADSC
ADSP
ADV
A8
A9
GS816136 100-Pin TQFP Pinout
LBO
A5
A4
A3
A2
A1
A0
TMS
TDI
VSS
VDD
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
DQD9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K
x
36
10
71
11
Top View
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.12 9/2002
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
TDO
TCK
A10
A11
A12
A13
A14
A15
A16
DQC9
DQC8
DQC7
VDDQ
3/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
TQFP Pin Description
Symbol
Type
Description
A 0, A 1
I
Address field LSBs and Address Counter preset Inputs
A2–A18
I
Address Inputs
A19
I
Address Input
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
I/O
Data Input and Output pins
NC
—
No Connect
BW
I
Byte Write—Writes all enabled bytes; active low
BA, BB, BC, BD
I
Byte Write Enable for DQA, DQB Data I/Os; active low
CK
I
Clock Input Signal; active high
GW
I
Global Write Enable—Writes all bytes; active low
E1
I
Chip Enable; active low
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active low
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep Mode control; active high
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
VDD
I
Core power supply
VSS
I
I/O and Core Ground
VDDQ
I
Output driver power supply
Rev: 2.12 9/2002
4/32
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GS816118/36T-250/225/200/166/150/133
GS816118/36 Block Diagram
A0–An
Register
D
Q
A0
A0
D0
A1
Q0
A1
D1
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
36
36
Register
D
Q
BB
4
4
Register
D
Q
Q
Register
D
D
Q
D
Q
Register
Register
D
Q
Register
BC
BD
Register
D
36
Q
36
36
Register
E1
D
Q
4
32
36
Parity
Encode
Register
D
Q
4
Parity
Compare
FT
G
ZZ
36
Power Down
1
DQx1–DQx9
NC
NC
Control
Note: Only x36 version shown for simplicity.
Rev: 2.12 9/2002
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GS816118/36T-250/225/200/166/150/133
Mode Pin Functions
Mode Name
Pin
Name
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
State
Function
L
Linear Burst
H
Interleaved Burst
L
Flow Through
H or NC
Pipeline
L or NC
Active
H
Standby, IDD = ISB
Note:
There arepull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Burst Counter Sequences
Interleaved Burst Sequence
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
1st address
00
01
10
11
2nd address
01
10
11
00
2nd address
01
00
11
10
3rd address
10
11
00
01
3rd address
10
11
00
01
4th address
11
00
01
10
4th address
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 2.12 9/2002
6/32
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GS816118/36T-250/225/200/166/150/133
Byte Write Truth Table
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Note:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x36 version.
Rev: 2.12 9/2002
7/32
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© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Synchronous Truth Table
Operation
Address Used
State
Diagram
Key5
E1
ADSP
ADSC
ADV
W3
DQ4
Deselect Cycle, Power Down
None
X
H
X
L
X
X
High-Z
Read Cycle, Begin Burst
External
R
L
L
X
X
X
Q
Read Cycle, Begin Burst
External
R
L
H
L
X
F
Q
Write Cycle, Begin Burst
External
W
L
H
L
X
T
D
Read Cycle, Continue Burst
Next
CR
X
H
H
L
F
Q
Read Cycle, Continue Burst
Next
CR
H
X
H
L
F
Q
Write Cycle, Continue Burst
Next
CW
X
H
H
L
T
D
Write Cycle, Continue Burst
Next
CW
H
X
H
L
T
D
Read Cycle, Suspend Burst
Current
X
H
H
H
F
Q
Read Cycle, Suspend Burst
Current
H
X
H
H
F
Q
Write Cycle, Suspend Burst
Current
X
H
H
H
T
D
Write Cycle, Suspend Burst
Current
H
X
H
H
T
D
Notes:
1. X = Don’t Care, H = High, L = Low
2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 2.12 9/2002
8/32
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© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Simplified State Diagram
X
Deselect
W
R
Simple Burst Synchronous Operation
Simple Synchronous Operation
W
X
R
R
First Write
CW
First Read
CR
CR
W
X
R
R
X
Burst Write
Burst Read
X
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 2.12 9/2002
9/32
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© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Simplified State Diagram with G
X
Deselect
W
R
W
X
R
R
First Write
CR
CW
W
CW
W
X
First Read
X
CR
R
Burst Write
R
CR
CW
W
Burst Read
X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 2.12 9/2002
10/32
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© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
–0.5 to 4.6
V
VCK
Voltage on Clock Input Pin
–0.5 to 6
V
VI/O
Voltage on I/O Pins
–0.5 to VDDQ +0.5 (≤ 4.6 V max.)
V
VIN
Voltage on Other Input Pins
–0.5 to VDD +0.5 (≤ 4.6 V max.)
V
IIN
Input Current on Any Pin
+/–20
mA
IOUT
Output Current on Any I/O Pin
+/–20
mA
PD
Package Power Dissipation
1.5
W
TSTG
Storage Temperature
–55 to 125
oC
TBIAS
Temperature Under Bias
–55 to 125
o
C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Rev: 2.12 9/2002
11/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Power Supply Voltage Ranges
Parameter
Symbol
Min.
Typ.
Max.
Unit
3.3 V Supply Voltage
VDD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
VDD2
2.3
2.5
2.7
V
3.3 V VDDQ I/O Supply Voltage
VDDQ3
3.0
3.3
3.6
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.3
2.5
2.7
V
Notes
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
VDDQ3 Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
2.0
—
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
–0.3
—
0.8
V
1
VDDQ I/O Input High Voltage
VIHQ
2.0
—
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
VILQ
–0.3
—
0.8
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
VDDQ2 Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
0.6*VDD
—
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
–0.3
—
0.3*VDD
V
1
VDDQ I/O Input High Voltage
VIHQ
0.6*VDD
—
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
VILQ
–0.3
—
0.3*VDD
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 2.12 9/2002
12/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Recommended Operating Temperatures
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)
TA
0
25
70
°C
2
Ambient Temperature (Industrial Range Versions)
TA
–40
25
85
°C
2
Note:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
VSS
50%
50%
VDD
VSS – 2.0 V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
4
5
pF
Input/Output Capacitance
CI/O
VOUT = 0 V
6
7
pF
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Layer Board
Symbol
Max
Unit
Notes
Junction to Ambient (at 200 lfm)
single
RΘJA
40
°C/W
1,2
Junction to Ambient (at 200 lfm)
four
RΘJA
24
°C/W
1,2
Junction to Case (TOP)
—
RΘJC
9
°C/W
3
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 2.12 9/2002
13/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
Output reference level
VDDQ/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
30pF*
50Ω
VDDQ/2
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
ZZ Input Current
IIN1
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
100 uA
FT Input Current
IIN2
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–1 uA
1 uA
1 uA
Output Leakage Current
IOL
Output Disable, VOUT = 0 to VDD
–1 uA
1 uA
Output High Voltage
VOH2
IOH = –8 mA, VDDQ = 2.375 V
1.7 V
—
Output High Voltage
VOH3
IOH = –8 mA, VDDQ = 3.135 V
2.4 V
—
Output Low Voltage
VOL
IOL = 8 mA
—
0.4 V
Rev: 2.12 9/2002
14/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
Rev: 2.12 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
15/32
—
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
Deselect
Current
165
10
IDD
IDD
60
85
IDD
Pipeline
Flow
Through
20
ISB
20
ISB
Pipeline
Flow
Through
165
10
260
15
180
20
IDDQ
IDD
IDDQ
IDD
IDDQ
IDD
IDDQ
IDD
Flow
Through
Pipeline
Flow
Through
Pipeline
290
30
260
20
IDD
IDDQ
Pipeline
IDDQ
180
20
IDD
IDDQ
Flow
Through
Flow
Through
290
40
0
to
70°C
IDD
IDDQ
Symbol
Pipeline
Mode
65
90
30
30
175
10
270
15
190
20
300
30
175
10
270
20
190
20
300
40
–40
to
85°C
-250
60
80
20
20
155
10
235
15
170
20
265
30
155
10
235
20
170
20
265
35
65
85
30
30
165
10
245
15
180
20
275
30
165
10
245
20
180
20
275
35
–40
to
85°C
-225
0
to
70°C
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
—
ZZ ≥ VDD – 0.2 V
(x18)
(x36)
(x18)
(x36)
Standby
Current
2.5 V
Operating
Current
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
Operating
Current
3.3 V
Test Conditions
Parameter
Operating Currents
50
75
20
20
150
10
215
15
165
15
240
25
150
10
215
15
165
15
240
30
0
to
70°C
55
80
30
30
160
10
225
15
175
15
250
25
160
10
225
15
175
15
250
30
–40
to
85°C
-200
50
64
20
20
140
10
185
10
155
15
205
20
140
10
185
15
155
15
205
25
0
to
70°C
55
70
30
30
150
10
195
10
165
15
215
20
150
10
195
15
165
15
215
25
–40
to
85°C
-166
50
60
20
20
135
10
170
10
150
15
190
20
135
10
170
15
150
15
190
25
0
to
70°C
55
65
30
30
145
10
180
10
160
15
200
20
145
10
180
15
160
15
200
25
–40
to
85°C
-150
45
50
20
20
125
10
155
10
140
10
170
15
125
10
155
10
140
10
170
20
0
to
70°C
50
55
30
30
135
10
165
10
150
10
180
15
135
10
165
10
150
10
180
20
–40
to
85°C
-133
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Unit
GS816118/36T-250/225/200/166/150/133
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
AC Electrical Characteristics
Pipeline
Flow
Through
Parameter
Symbol
Clock Cycle Time
-250
-225
-200
-166
-150
-133
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tKC
4.0
—
4.4
—
5.0
—
6.0
—
6.7
—
7.5
—
ns
Clock to Output Valid
tKQ
—
2.5
—
2.7
—
3.0
—
3.4
—
3.8
—
4.0
ns
Clock to Output Invalid
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock to Output in Low-Z
tLZ1
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Setup time
tS
1.2
—
1.3
—
1.4
—
1.5
—
1.5
—
1.5
—
ns
Hold time
tH
0.2
—
0.3
—
0.4
—
0.5
—
0.5
—
0.5
—
ns
Clock Cycle Time
tKC
5.5
—
6.0
—
6.5
—
7.0
—
7.5
—
8.5
—
ns
Clock to Output Valid
tKQ
—
5.5
—
6.0
—
6.5
—
7.0
—
7.5
—
8.5
ns
Clock to Output Invalid
tKQX
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock to Output in Low-Z
tLZ1
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Setup time
tS
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Hold time
tH
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
Clock HIGH Time
tKH
1.3
—
1.3
—
1.3
—
1.3
—
1.5
—
1.7
—
ns
Clock LOW Time
tKL
1.5
—
1.5
—
1.5
—
1.5
—
1.7
—
2
—
ns
Clock to Output in
High-Z
tHZ1
1.5
2.3
1.5
2.5
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
G to Output Valid
tOE
—
2.3
—
2.5
—
3.2
—
3.5
—
3.8
—
4.0
ns
G to output in Low-Z
tOLZ1
0
—
0
—
0
—
0
—
0
—
0
—
ns
G to output in High-Z
tOHZ1
—
2.3
—
2.5
—
3.0
—
3.0
—
3.0
—
3.0
ns
ZZ setup time
tZZS2
5
—
5
—
5
—
5
—
5
—
5
—
ns
ZZ hold time
tZZH2
1
—
1
—
1
—
1
—
1
—
1
—
ns
ZZ recovery
tZZR
20
—
20
—
20
—
20
—
20
—
20
—
ns
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 2.12 9/2002
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Write Cycle Timing
Single Write
Burst Write
Deselected
Write
CK
tS tH
tKH tKL
tKC
ADSP is blocked by E inactive
ADSP
tS tH
ADSC initiated write
ADSC
tS tH
ADV
tS tH
A0–An
ADV must be inactive for ADSP Write
WR2
WR1
WR3
tS tH
GW
tS
tH
BW
tS tH
BA–BD
WR2
WR1
WR1
tS tH
WR3
WR3
E1 masks ADSP
E1
E1 only sampled with ADSP or ADSC
G
tS tH
DQA–DQD
Rev: 2.12 9/2002
Hi-Z
Write specified byte for 2A and all bytes for 2B, 2C& 2D
D1A
D2A
D2B
D2C
D2D
17/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
D3A
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tKH
tS tH
ADSP
tKC
ADSP is blocked by E inactive
tS tH
ADSC initiated read
ADSC
tS tH
Suspend Burst
Suspend Burst
ADV
tS tH
A0–An
RD1
RD2
RD3
tS
tH
tS
tH
GW
BW
BA–BD
tS tH
E1 masks ADSP
E1
tOE
tOHZ
G
tKQX
tOLZ
DQA–DQD
Hi-Z
Q1A
Q2A
tKQX
Q2B
Q2c
Q2D
Q3A
tLZ
tHZ
tKQ
Rev: 2.12 9/2002
18/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Flow Through Read-Write Cycle Timing
Single Write
Single Read
Burst Read
CK
tS tH
tKH tKL
ADSP
tKC
ADSP is blocked by E inactive
tS tH
ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0–An
WR1
RD1
tS
RD2
tH
GW
tH
tS
BW
tS tH
BA–BD
WR1
tS tH
E1 masks ADSP
E1
tOE
tOHZ
G
DQA–DQD
Hi-Z
tS
tKQ
Q1A
tH
D1A
Q2A
Q2B
Q2c
Q2D
Q2A
Burst wrap around to it’s initial state
Rev: 2.12 9/2002
19/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Pipelined SCD Read Cycle Timing
Single Read
Burst Read
CK
tKH
tS tH
tKL
tKC
ADSP
ADSP is blocked by E inactive
tS tH
ADSC initiated read
ADSC
tS tH
Suspend Burst
ADV
tS tH
A0–An
RD2
RD1
RD3
tS
tH
tS
tH
GW
BW
BWA–BWD
tS tH
E1 masks ADSP
E1
tOE
G
DQA–DQD
tOHZ
Hi-Z
tKQX
tKQX
tOLZ
Q1A
tLZ
Q2A
Q2B
Q2c
Q2D
Q3A
tHZ
tKQ
Rev: 2.12 9/2002
20/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Pipelined SCD Read-Write Cycle Timing
Single Write
Single Read
Burst Read
tKL
CK
tS tH
tKH
tKC
ADSP is blocked by E inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0–An
WR1
RD1
RD2
tS tH
GW
tS
tH
BW
tS tH
BWA–BWD
WR1
tS tH
E1 masks ADSP
E1
tOE
tOHZ
G
DQA–DQD
Rev: 2.12 9/2002
Hi-Z
tS tH
tKQ
Q1A
D1A
Q2A
21/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q2B
Q2c
Q2D
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
tKH tKL
ADSP
ADSC
tZZS
ZZ
~
~ ~
~
tKC
~
~
tS tH
tZZH
~
~~
~
CK
~
~ ~
~ ~
~~
~ ~
~ ~
~
Sleep Mode Timing Diagram
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Rev: 2.12 9/2002
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDI
Test Data In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and
0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising
edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI
and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Rev: 2.12 9/2002
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
JTAG TAP Block Diagram
0
Bypass Register
2 1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
·
· · ·
2 1 0
Boundary Scan Register
n
· · · · · ·
· · ·
2 1 0
TMS
Test Access Port (TAP) Controller
TCK
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Die
Revision
Code
GSI Technology
JEDEC Vendor
ID Code
I/O
Configuration
Not Used
Presence Register
ID Register Contents
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x36
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0 0 1 1 0 1 1 0 0 1
1
x18
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0 0 1 1 0 1 1 0 0 1
1
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 2.12 9/2002
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
JTAG Tap Controller State Diagram
1
0
Test Logic Reset
0
Run Test Idle
1
Select DR
1
Select IR
0
0
1
1
Capture DR
Capture IR
0
0
Shift DR
1
1
Shift IR
0
1
1
Exit1 DR
0
Exit1 IR
0
0
Pause DR
1
Exit2 DR
1
Update DR
1
1
0
0
Pause IR
1
Exit2 IR
0
1
0
0
Update IR
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to ShiftDR state then places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
Rev: 2.12 9/2002
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© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when
the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the
sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in
parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the
Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 2.12 9/2002
26/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
3.3 V Test Port Input High Voltage
VIHJ3
2.0
VDD3 +0.3
V
1
3.3 V Test Port Input Low Voltage
VILJ3
–0.3
0.8
V
1
2.5 V Test Port Input High Voltage
VIHJ2
0.6 * VDD2
VDD2 +0.3
V
1
2.5 V Test Port Input Low Voltage
VILJ2
–0.3
0.3 * VDD2
V
1
TMS, TCK and TDI Input Leakage Current
IINHJ
–300
1
uA
2
TMS, TCK and TDI Input Leakage Current
IINLJ
–1
100
uA
3
TDO Output Leakage Current
IOLJ
–1
1
uA
4
Test Port Output High Voltage
VOHJ
1.7
—
V
5, 6
Test Port Output Low Voltage
VOLJ
—
0.4
V
5, 7
Test Port Output CMOS High
VOHJC
VDDQ – 100 mV
—
V
5, 8
Test Port Output CMOS Low
VOLJC
—
100 mV
V
5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOHJC = +100 uA
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
2.3 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
1.25 V
Output reference level
1.25 V
50Ω
30pF*
VT = 1.25 V
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
Rev: 2.12 9/2002
JTAG Port AC Test Load
DQ
27/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
JTAG Port Timing Diagram
tTKL
tTKH
tTKC
TCK
tTS
tTH
TMS
TDI
TDO
tTKQ
JTAG Port AC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tTKC
50
—
ns
TCK Low to TDO Valid
tTKQ
—
20
ns
TCK High Pulse Width
tTKH
20
—
ns
TCK Low Pulse Width
tTKL
20
—
ns
TDI & TMS Set Up Time
tTS
10
—
ns
TDI & TMS Hold Time
tTH
10
—
ns
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: [email protected]
Rev: 2.12 9/2002
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
TQFP Package Drawing
L
Description
Min. Nom. Max
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
L
Foot Length
L1
Lead Length
Y
Coplanarity
θ
Lead Angle
L1
c
Pin 1
Symbol
θ
0.20
D
D1
e
b
0.65
0.45
0.60
0.75
1.00
A1
A2
0.10
Y
0°
7°
E1
E
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 2.12 9/2002
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
Org
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
1M x 18
GS816118T-250
Pipeline/Flow Through
TQFP
250/5.5
C
1M x 18
GS816118T-225
Pipeline/Flow Through
TQFP
225/6
C
1M x 18
GS816118T-200
Pipeline/Flow Through
TQFP
200/6.5
C
1M x 18
GS816118T-166
Pipeline/Flow Through
TQFP
166/7
C
1M x 18
GS816118T-150
Pipeline/Flow Through
TQFP
150/7.5
C
1M x 18
GS816118T-133
Pipeline/Flow Through
TQFP
133/8.5
C
512K x 36
GS816136T-250
Pipeline/Flow Through
TQFP
250/5.5
C
512K x 36
GS816136T-225
Pipeline/Flow Through
TQFP
225/6
C
512K x 36
GS81613T-200
Pipeline/Flow Through
TQFP
200/6.5
C
512K x 36
GS816136T-166
Pipeline/Flow Through
TQFP
166/7
C
512K x 36
GS816136T-150
Pipeline/Flow Through
TQFP
150/7.5
C
512K x 36
GS816136T-133
Pipeline/Flow Through
TQFP
133/8.5
C
1M x 18
GS816118T-250I
Pipeline/Flow Through
TQFP
250/5.5
I
Not Available
1M x 18
GS816118T-225I
Pipeline/Flow Through
TQFP
225/6
I
Not Available
1M x 18
GS816118T-200I
Pipeline/Flow Through
TQFP
200/6.5
I
Not Available
1M x 18
GS816118T-166I
Pipeline/Flow Through
TQFP
166/7
I
1M x 18
GS816118T-150I
Pipeline/Flow Through
TQFP
150/7.5
I
1M x 18
GS816118T-133I
Pipeline/Flow Through
TQFP
133/8.5
I
512K x 36
GS816136T-250I
Pipeline/Flow Through
TQFP
250/5.5
I
Not Available
512K x 36
GS816136T-225I
Pipeline/Flow Through
TQFP
225/6
I
Not Available
512K x 36
GS816136T-200I
Pipeline/Flow Through
TQFP
200/6.5
I
Not Available
512K x 36
GS816136T-166I
Pipeline/Flow Through
TQFP
166/7
I
512K x 36
GS816136T-150I
Pipeline/Flow Through
TQFP
150/7.5
I
512K x 36
GS816136T-133I
Pipeline/Flow Through
TQFP
133/8.5
I
Status
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816118T-166IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 2.12 9/2002
30/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
GS816118T-150IT 1.00 9/
1999A;GS816118T-150IT
2.00 1/1999B
Types of Changes
Format or Content
Content
• Converted from 0.25u 3.3V process to 0.18u 2.5V process.
Master File Rev B
• Added x72 Pinout.
• Added GSI Logo.
• Changed pin description in TQFP to match order of pins in
pinout.
GS816118T 2.01 1/
2000C;GS816118 T 2.02 1/
2000D
• Front page; Features - changed 2.5V I/O supply to 2.5V
or3.3V I/O supply; Core and Interface voltages - Changed
paragraph to include information for 3.3V;Completeness
• Absolute Maximum Ratings; Changed VDDQ - Value: From: .05 to VDD : to : -.05 to 3.6; Completeness.
• Recommended Operating Conditions;Changed: I/O Supply
Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from
VDD +0.3 to 3.6; Same page - took out Note 1;Completeness
• Electrical Characteristics - Added second Output High Voltage
line to table; completeness.
• Note: There was not a Rev 2.02 for the 8160Z or the 8161Z.
GS18/362.0 1/2000DGS18/
362.03 2/2000E
GS18/362.03 2/200E;
816118_r2_04
Page;Revisions;Reason
Content
• Changed the value of ZZ recovery in the AC Electrical
Characteristics table on page 15 from 20 ns to 100 ns
• Added 225 MHz speed bin
• Updated Pg. 1 table, AC Characteristics table, and Operating
Currents table to match 815xxx
• Updated format to comply with Technical Publications
standards
816118_r2_04;
816118_r2_05
Content/Format
816118_2_05;
816118_r2_06
Content
• Updated Capitance table—removed Input row and changed
Output row to I/O
816118_r2_06;
811618_r2_07
Content
• Updated Features list on page 1
• Completely reworked table on page 1
• Updated Mode Pin Functions table on page 7
Content
• Added 3.3 V references to entire document
• Updated Operating Conditions table
• Updated Boundary Scan Chain table
• Updated JTAG section
• Added Pin 56 to Pin Description table
• Updated Operating Currents table and added note
• Update table on page 1; added power numbers
• Updated Application Tips paragraph
816118_r2_07;
811618_r2_08
Rev: 2.12 9/2002
31/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
Content
• Updated Synchronous Truth Table
• Updated Operating Currents table
• Updated table on page 1; updated power numbers
• Updated Recommended Operating Conditions table (added
VDDQ references)
Content
• Updated table on page 1
• Created recommended operating conditions tables on pages
11 and 12
• Updated AC Electrical Characteristics table
• Added Sleep mode description on page 22
• Updated Ordering Information for 225 MHz part (changed
from 7ns to 6.5 ns)
• Updated BSR table (2 and 3 changed to X (value undefined))
• Added 250 MHz speed bin
• Deleted 180 MHz speed bin
816118_r2_10;
816118_r2_11
Content
• Updated AC Characteristics table
• Updated FT power numbers
• Updated Mb references from 16Mb to 18Mb
• Removed ByteSafe references
• Changed DP and QE pins to NC
• Updated ZZ recovery time diagram
• Updated AC Test Conditions table and removed Output Load
2 diagram
816118_r2_11;
816118_r2_12
Content
• Removed Preliminary banner
• Removed pin locations from pin description table
• Removed BSR table
816118_r2_08;
811618_r2_09
816118_r2_09;
816118_r2_10
Rev: 2.12 9/2002
32/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.