ICS2694 Integrated Circuit Systems, Inc. Motherboard Clock Generator Description Features The ICS2694 Motherboard Clock Generator is an integrated circuit using PLL and VCO technology to generate virtually all the clock signals required in a PC. The use of the device can be generalized to satisfy the timing needs of most digital systems by reprogramming the VCO or reconfiguring the counter stages which derive the output frequencies from the VCO’s. • The primary VCO is customarily used to generate the CPU clock and is so labeled on the ICS2694. Pre-programmed frequency sets are listed on page 6. These choices were made to match the major microprocessor families. CPUSEL (0-3) allow the user to select the appropriate frequency for the application. • • • Applications • • • • • • CPU clock and Co-processor clock Hard Disk and Floppy Disk clock Keyboard clock Serial Port clock Bus clock System counting or timing functions • • • • Pin Configuration OUT2 OUT1 OUT0 OUT9 CPUCLK VSS DVDD STROBE CPUSEL0 CPUSEL1 CPUSEL2 CPUSEL3 1 2 3 4 5 6 7 8 9 10 11 12 ICS2694 Due to the filter in the phase-locked loop, the CPUCLK will move in a linear fashion from one frequency to a newlyselected frequency without glitches. If a fixed CPUCLK value is desired, CPUSEL (0-3) may be hard wired to the desired address with STROBE tied high. (It has a pull-up.) For board test and debug, pulling OUTPUTE to Ground will tristate all the outputs. • Low cost - eliminates multiple oscillators and Count Down Logic Primary VCO has 16 Mask Programmable frequencies (normally CPU clock) Secondary VCO has 1 Mask Programmable frequency (usually 96 MHz) Pre-programmed versions for typical PC applications 10 Outputs in addition to the primary CPU clock Capability to reconfigure counter stages to change the frequencies of the outputs via mask options Advanced PLL design On-chip PLL filters Very Flexible Architecture 24 23 22 21 20 19 18 17 16 15 14 13 24-Pin DIP or SOIC ICS2694RevA1094 OUT3 OUT4 OUT5 OUT6 OUT7 (CPUCLK/2) OUT8 AVDD XTAL2 XTAL1 AVSS OUTPUTE CLKIN ICS2694 Pin Description PIN NUMBER 1 2 3 4 5 NAME OUT2 OUT1 OUT0 OUT9 CPUCLK 6 7 8 VSS DVDD STROBE 9 10 11 12 13 CPUSEL0 CPUSEL1 CPUSEL2 CPUSEL3 CLKIN 14 15 16 17 OUTPUTE AVSS XTAL1 XTAL2 18 19 20 21 22 23 24 AVDD OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 DESCRIPTION 4mA Output. 4mA Output. 4mA Output 4mA Output. 4mA Output driven by Voltage Controlled Oscillator 1 (VC01). VC01 is controlled by a 16 word ROM. Ground for digital portion of chip. Plus supply for digital portion of chip. Input control for transparent latches associated with CPU (0-3) which select one of 16 values for CPUCLK. Holding STROBE high causes the latches to be transparent. LSB CPUCLK address bit. CPUCLK address bit. CPUCLK address bit. MSB CPUCLK address bit. An alternative input for the reference clock. The crystal oscillator output and CLKIN are gated together to generate the reference clock for the VCO’s. If CLKIN is used, XTAL1 should be held high and XTAL2 left open. If the internal oscillator is used, hold CLKIN high. Pulling this line low tristates all outputs. Ground for analog portion of chip. Input of internal crystal oscillator stage. Output of internal crystal oscillator stage. This pin should have nothing connected to it but one of the quartz crystal terminals. Positive supply for analog portion of chip. 4mA Output. 4mA Output. (Usually assigned as CPUCLK/2 for co-processor use.) 4mA Output. 4mA Output. 4mA Output. 4mA Output. 2 ICS2694 Frequency Reference Power Supply Conditioning The internal reference oscillator contains all of the passive components required. An appropriate series-resonant crystal should be connected between XTAL1 (1) and XTAL2 (2). In IBM-compatible applications, this will typically be a 14.31818 MHz crystal, but fundamental mode crystals between 10 MHz and 25 MHz have been tested. Maintain short lead lengths between the crystal and the ICS2694. In order to optimize the quality of the quartz crystal oscillator, the input switching threshold of XTAL1 is VDD/2 rather than the conventional 1.4V of TTL. Therefore, XTAL1 may not respond properly to a legal TTL signal since TTL is not required to exceed VDD/2. Therefore, another clock input CLKIN (pin 13) has been added to the chip which is sized to have an input switching point of 1.4V. Inside the chip, these two inputs are ANDED. Therefore, when using the XTAL1 and XTAL2, CLKIN should be held high. (It has a pull-up.) When using CLKIN, XTAL1 should be held high. (It does not have a pull-up because a pull-up would interfere with the oscillator bias.) The ICS2694 is a member of the second generation of dot clock products. By incorporating the loop filter on chip and upgrading the VCO, the ease of application has been substantially improved over earlier products. If a stable and noise-free power supply is available, no external components are required. However, in some applications it may be judicious to decouple the power supply as shown in Figures 1 or 2. Figure 1 is the normal configuration for 5 volt only applications. Which of the two provides superior performance depends on the noise content of the power supplies. In general, the configuration of Figure 1 is satisfactory. Figure 2 is the more conventional if a 12 volt analog supply is available, although the improved performance comes at a cost of an extra component; however, the cost of the discretes used in Figure 1’s are less than the cost of Figure 1’s discrete components. Since the ICS2694 outputs a large number of high-frequency clocks, conservative design practices are recommended. Care should be exercised in the board layout of supply and ground traces, and adequate power supply decoupling capacitors consistent with the application should be used. It is anticipated that some applications will use both clock inputs, properly gated, for either board test or unique system functions. By generating all the system clocks from one reference input, the phase and delay relationships between the various outputs will remain relatively fixed, thereby eliminating problems arising from totally unsynchronized clocks interacting in a system. +5 +50 C1 C1 DVDD DVDD .µ1F .µ1F 33 +5 470 R1 C2 C3 22µV .µ1F AVDD +120 VSS, AVSS Figure 1 R1 D1 C2 4.7V .µ1F Figure 2 3 AVDD VSS, AVSS ICS2694 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . VDD. . . . . . . . . . . . Input Voltage . . . . . . . . . . . . . . . . . . VIN . . . . . . . . . . . . Output Voltage . . . . . . . . . . . . . . . . VOUT. . . . . . . . . . Clamp Diode Current . . . . . . . . . . . VIK & IOK . . . . . . . Output Current per Pin . . . . . . . . . . IOUT . . . . . . . . . . . Operating Temperature . . . . . . . . . . TO . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . TS . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . PD . . . . . . . . . . . . . -0.5V to +7V -0.5V to VDD +0.5V -0.5V to VDD +0.5V ±30mA ±50mA 0°C to + 150°C -85°C to + 150°C 500mW Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than the maximum rated voltages. For proper operation, it is recommended that VIN and VOUT be constrained to > = VSS and < = VDD. DC Characteristics (0°C to 70°C) PARAMETER Operating Voltage Range Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage Supply Current Internal Pull-up Resistors Input Pin Capacitance Output Pin Capacitance SYMBOL VDD VIL VIH IIH VOL VOH IDD RUP * Cin Cout CONDITIONS VDD = 5V VDD = 5V VIN = Vcc IOL = 4.0 mA IOH = 4.0 mA VDD = 5V, CPUCLK = 80 MHz VDD = 5V, Vin = 0V Fc = 1 MHz Fc = 1 MHz MIN 4.0 VSS 2.0 2.4 50 - * The following inputs have pull-ups: OUTPUTE, STROBE, CPUSEL (0-3), CLKIN. 4 MAX 5.5 0.8 VDD 10 0.4 55 8 12 UNITS V V V uA V V mA k ohm pF pF ICS2694 AC Timing Characteristics The following notes apply to all parameters presented in this section: 1. 2. 3. 4. 5. 6. 7. Xtal Frequency = 14.31818 MHz All units are in nanoseconds (ns). Rise and fall time is between 0.8 and 2.0 VDC. Output pin loading = 15pF Duty cycle is measured at 1.4V. Supply Voltage Range = 4.5 to 5.5 volts Temperature Range = 0°C to 70°C SYMBOL PARAMETER Tpw Tsu Thd Strobe Pulse Width Setup Time Data to Strobe Hold Time Data to Strobe Tr Tf - Rise Time Fall Time Frequency Error Maximum Frequency MIN STROBE TIMING 20 10 10 FOUT TIMING - MAX NOTES 3 3 0.5 135 Duty Cycle 40% min. to 60% max. at 80 MHz % MHz Note: Pattern -004 has rising edges of CPUCLK and CPUCLK/2 matched to ± 2 ns. Tpw STROBE CPUSEL (0-3) Tsu 5 Thd ICS2694 24-Pin DIP Package Ordering Information ICS2694N-XXX Example: ICS XXXX M -XXX Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type N=DIP (Plastic) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device 6 ICS2694 LEAD COUNT DIMENSION L 14L 0.354 16L 0.404 18L 0.454 20L 0.504 24L 0.604 28L 0.704 32L 0.804 SOIC Packages Ordering Information ICS2694M-XXX Example: ICS XXXX M -XXX Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device 7 ICS2694 Another alternative for CPU CLOCK generation is the ICS2494-244 if the additional functions of the ICS2694 are not needed in the application. 32 MHz 1.846 MHz 24 MHz 6 MHz CPUCLK VSS DVDD STROBE CPUSEL0 CPUSEL1 CPUSEL2 CPUSEL3 1 2 3 4 5 6 7 8 9 10 11 12 ICS2694-004 ICS2694 Standard Patterns 24 23 22 21 20 19 18 17 16 15 14 13 16 MHz 8 MHz 9.6 MHz 14.318 MHz CPUCLK/2 1.19 MHz AVDD XTAL2 XTAL1 AVSS OUTPUTE CLKIN CPUSEL0-3 (Hex) CPUCLK OUTPUT (Pin 5) (MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 10 20 24 25 32 33.33 40 48 50 54 66.67 68 80 100 16 Note: Pattern -004 has rising edges of CPUCLK and CPUCLK/2 matched to ± 2 ns. 8 ICS Part Number Address FS3-0 (Hex) ICS2494244 Frequency (MHz) 0 1 2 3 4 5 6 7 8 9 0 B C D E F 20 24 32 40 50 66.6 80 100 54 70 90 110 25 33.3 40 50 Address MS1-0 (Hex) 0 1 2 3 Frequency (MHz) 16 24 50 66.6