ICS9150-02 Integrated Circuit Systems, Inc. Preliminary Product Preview Pentium Pro and SDRAM Frequency Generator General Description Features The ICS9150-02 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel Pentium Pro. Two different reference frequency multiplying factors are externally selectable with smooth frequency transitions. An output enable is provided for testability. High drive PCICLK & SDRAM outputs typically provide greater than 1V/ns slew rate into 30 pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50 ± 5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. Generates five processor, six bus, two 14.31818MHz and 13 SDRAM clocks. Synchronous clocks skew matched to 250 ps window on PCLKs and 500 ps window on BCLKs Test clock mode eases system design Spread Spectrum available I2C interface for programming Skew from CPU (earlier) to PCI clock -1 to 4ns, center 2.6ns 3.0V 3.7V supply range 56-pin SSOP package Pin Configuration Block Diagram 56-Pin SSOP Functionality FS0 0 1 CPUCLK, SDRAM (M H z) 60.0 66.6 X1, REF (M H z) P C IC L K (M H z) 14.318 14.318 30 3 3 .3 Pentium is a trademark of Intel Corporation 9150-02 Rev D 09/18/97 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICS9150-02 Preliminary Product Preview Pin Descriptions PIN NUMBER 2, 3 4, 10, 17, 23, 31, 34, 40, 47, 53 5 6 8 9, 11, 12, 13 14, 16 18, 19 21 27 28 29 30 1, 7, 15, 20, 26, 37, 43 50, 56 22, 24, 25, 32, 33, 35, 36, 38, 39, 41, 42, 44, 45 54, 55 46, 48, 49, 51, 52 PIN NAME TYPE DESCRIPTION REF (0:1) OUT 14.318 MHz reference clock outputs. GND PWR Ground. X1 IN X2 OUT PCICLK_F OUT 14.318MHz input. Has internal load cap, (33pF). Crystal output. Has internal load cap (33pF) and feedback resistor to X1 Free running BUS clock. PCICLK (0:5) OUT BUS clock outputs. 48MHz N/C SDATA SCLK OE SEL 66/60# VDD2, VDD1, VDD3, VDD4 VDDL2, VDDL1 OUT IN IN IN IN 48MHz clock outputs Pins are not internally connected. Serial data in for serial config port. Clock input for serial config port. Selects 60MHz or 66MHz for SDRAM and CPU. PWR Nominal 3.3V power supply. See power groups for function. PWR CPU and IOAPIC clock buffer power supply (2.5 - VDD) SDRAM (0:12) OUT SDRAM clocks (60/66.6MHz) IOAPIC (1:0) CPUCLK (0:4) OUT OUT IOAPIC clock output. (14.31818 MHz) Powered by VDDL1 CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz) Logic input for output enable, tristates all outputs when low. Power Groups VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = SDRAM (0:12), Supply for PLL core VDD4 = 48 MHz VDDL1 = IOAPIC (0:1) VDDL2 = CPUCLK (0:4) 2 ICS9150-02 Preliminary Product Preview Technical Pin Function Descriptions VDD(1,2,3,4) This is the power supply to the internal core logic of the device as well as the clock output buffers for REF(0:1), PCICLK, 48MHz (0:1) and SDRAM(0:7). IOAPIC (0:1) These Outputs are fixed frequency Output Clocks that run at the Reference Input (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL1 and may operate at 2.5 or 3.3volts. This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. REF (0:1) The REF Output is a fixed frequency Clock that runs at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2. VDDL1,2 This is the power supplies for the CPUCLK and IOAPCI output buffers. The voltage level for these outputs may be 2.5 or 3.3volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual Guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet. PCICLK_F This Output is equal to PCICLK(0:5). GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. FS0 This Input pin controls the frequency of the Clocks at the CPU, PCICLK and SDRAM output pins. If a logic 1 value is present on this pin, the 66.6 MHz Clock will be selected. If a logic 0 is used, the 60MHz frequency will be selected. PCICLK (0:5) These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 1/2 CPU frequency. X1 This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. With a nominal value of 33pF no external load cap is needed for a CL =17 to 18pF crystal. I2C The SDATA and SCLOCK Inputs are use to program the device. The clock generator is a slave-receiver device in the I2C protocol. It will allow read-back of the registers. See configuration map for register functions. The I2C specification in Philips I2C Peripherals Data Handbook (1996) should be followed. X2 This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor nominally 33pF. 48MHz This is a fixed frequency clock that is typically used to drive Super I/O peripheral device needs and USB. OE Output Enable tristates the outputs when held low. This pin will override the I2C Byte 0 function, so that the outputs will be tristated when the OE is low regardless of the I2C defined function. When OE is high, the I2 C function is in active control. CPUCLK (0:4) These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks are controlled by theVoltage level applied to theVDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them. SDRAM(0:12) These Output Clocks are use to drive Dynamic RAMs and are low skew copies of the CPU Clocks. The voltage swing of the SDRAMs output is controlled by the supply voltage that is applied to VDD3 of the device, operates at 3.3 volts. 3 ICS9150-02 Preliminary Product Preview General I2C serial interface information For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with an acknowledge bit between each byte. A. Clock Generator Address (7 bits) A(6:0) & R/W# D2(H) ACK + 8 bits dummy command code ACK + 8 bits dummy Byte count ACK Then Byte 0, 1, 2, etc in sequence until STOP. The clock generator is a slave/receiver I 2C component. It can "read back "(in Philips I2C protocol) the data stored in the latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB PIIX4 protocol. B. Clock Generator Address (7 bits) A(6:0) & R/W# D3(H) ACK Byte 0 ACK Byte 1 ACK Byte 0, 1, 2, etc in sequence until STOP. C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode) D. The input is operating at 3.3V logic levels. E. The data byte format is 8 bit bytes. F. To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. G. In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches maintain all prior programming information. H. At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default to a 1 (Enabled output state) Serial Configuration Command Bitmaps Byte 0: Functional and Frequency Select Clock Register (default = 0) BIT Bit 7 Bit 6 PIN# - Bit 5 Bit 4 Bit Bit Bit Bit 3 2 1 0 - - DESCRIPTION Reserved Must be 0 for normal operation Must be 0 for normal operation In Spread Spectrum, Controls type (0=centered, 1=down spread) Must be 0 for normal operation In Spread Spectrum, Controls Controls Spreading %(0=1.5%, 1=0.5%) Reserved Reserved Bit1 Bit0 1 1 - Tri-State 1 0 - Spread Spectrum Enable 0 1 - Testmode 0 0 - Normal operation 4 PWD 0 0 0 0 0 0 0 0 0 0 Note: PWD = Power-Up Default I2C is a trademark of Philips Corporation ICS9150-02 Preliminary Product Preview Select Functions OUTPUTS FUNCTION DESCRIPTION CPU Tri - State Test Mode Hi-Z TCLK/21 PCI, PCI_F Hi-Z TCLK/41 SDRAM REF IOAPIC Hi-Z TCLK/21 Hi-Z TCLK1 Hi-Z TCLK1 Notes: 1. REF is a test clock on the X1 inputs during test mode. Byte 2: PCICLK Clock Register Byte 1: CPU Clock Register BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BIT PIN# PWD DESCRIPTION Bit 7 1 Reserved Bit 6 8 1 PCICLK_F (Act/Inact) Bit 5 16 1 PCICLK5 (Act/Inact) Bit 4 14 1 PCICLK4 (Act/Inact) Bit 3 13 1 PCICLK3 (Act/Inact) Bit 2 12 1 PCICLK2 (Act/Inact) Bit 1 11 1 PCICLK1 (Act/Inact) Bit 0 9 1 PCICLK0 (Act/Inact) PIN# PWD DESCRIPTION 1 Reserved 1 Reserved 1 Reserved 46 1 CPUCLK4 (Act/Inact) 48 1 CPUCLK3 (Act/Inact) 49 1 CPUCLK2 (Act/Inact) 51 1 CPUCLK1 (Act/Inact) 52 1 CPUCLK0 (Act/Inact) Notes: 1 = Enabled; 0 = Disabled, outputs held low Notes: 1 = Enabled; 0 = Disabled, outputs held low Byte 3: SDRAM Clock Register Byte 4: SDRAM Clock Register BIT PIN# PWD DESCRIPTION Bit 7 35 1 SDRAM7 (Act/Inact) Bit 6 36 1 SDRAM6 (Act/Inact) Bit 5 38 1 SDRAM5 (Act/Inact) Bit 4 39 1 SDRAM4 (Act/Inact) Bit 3 41 1 SDRAM3 (Act/Inact) Bit 2 42 1 SDRAM2 (Act/Inact) Bit 1 44 1 SDRAM1 (Act/Inact) Bit 0 45 1 SDRAM0 (Act/Inact) BIT PIN# PWD DESCRIPTION Bit 7 18 1 48 MHz0 (Act/Inact) Bit 6 19 1 48 MHz1 (Act/Inact) Bit 5 1 Reserved Bit 4 22 1 SDRAM12 (Act/Inact) Bit 3 24 1 SDRAM11 (Act/Inact) Bit 2 25 1 SDRAM10 (Act/Inact) Bit 1 32 1 SDRAM9 (Act/Inact) Bit 0 33 1 SDRAM8 (Act/Inact) Notes: 1 = Enabled; 0 = Disabled, outputs held low Byte 6: Peripheral Clock Register Byte 5: Peripheral Clock Register BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BIT PIN# PWD DESCRIPTION Bit 7 1 Reserved Bit 6 2 1 REF0 (Act/Inact) Bit 5 54 1 IOAPIC1 (Act/Inact) Bit 4 55 1 IOAPIC0 (Act/Inact) Bit 3 1 Reserved Bit 2 1 Reserved Bit 1 1 Reserved Bit 0 3 1 REF1 (Act/Inact) PIN# PWD DESCRIPTION 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Reserved Notes: 1. Byte 6 is reserved by Integrated Circuit Systems for future applications. Notes: 1 = Enabled; 0 = Disabled, outputs held low 5 ICS9150-02 Preliminary Product Preview Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 3.7 V, TA = 0 70° C unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 6 TYP MAX UNITS ICS9150-02 Preliminary Product Preview Electrical Characteristics at 3.3V VDD = 3.0 3.7 V, TA = 0 70° C unless otherwise stated AC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 7 TYP MAX UNITS ICS9150-02 Preliminary Product Preview SSOP Package SYMBOL A A1 A2 B C D E e H h L N ∝ X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0° 5° 8° .085 .093 .100 VARIATIONS MIN. .620 .720 AC AD D NOM. .625 .725 N MAX. .630 .730 48 56 Ordering Information ICS9150F-02 Example: ICS XXXX F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 8 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.