IMP2 1 1 9 DATA COMMUNICATIONS Key Features 9-Line ULTRA3 LVD/SE SCSI Terminator The IMP2119 is a multimode SCSI terminator that conforms to the SCSI Parallel Interconnect-2 (SPI-2) specification developed by the T10 standards committee for low voltage differential (LVD) termination. Multimode compatibility permits the use of legacy devices on the bus without hardware alterations. Automatic mode selection is achieved through voltage detection on the diffsense line. The IMP2119 delivers the ultimate in SCSI bus performance while saving component cost and board area. Elimination of the external capacitors also mitigates the need for a lengthy capacitor selection process. The individual high bandwidth drivers also maximize channel separation and reduce channel to channel noise and cross talk. The high bandwidth architecture insures ULTRA3 performance. When the IMP2119 is enabled, the differential sense (DIFFSENSE) pin supplies a voltage between 1.2V and 1.4V. In application, this pin is tied to the DIFFSENSE input of the corresponding LVD transceivers. This action enables the LVD transceiver function. DIFFSENSE is capable of supplying a maximum of 15mA. Tying the DIFFSENSE pin HIGH places the IMP2119 in a high impedance state indicating the presence of an HVD device. Tying the pin LOW places the part in a single-ended mode while also signaling the multimode transceiver to operate in a singleended mode. Recognizing the needs of portable and configurable peripherals, the IMP2119 have a TTL compatible sleep/disable mode. During this sleep/disable mode, power dissipation is reduced to a meager 15µA while also placing all outputs in a high impedance state. Also during ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Auto-selectable LVD or single-ended termination 3.0pF maximum disabled output capacitance Fast response, no external capacitors required Compatible with active negation drivers 15µA supply current in disconnect mode Logic command disconnects all termination lines DIFFSENSE line driver Ground driver integrated for single-ended operation Current limit and thermal protection Hot-swap compatible (single-ended) Compatible with SCSI, SPI-2, SPI-3, SPI-4 ULTRA160 and ULTRA320 Pin compatible with DS2119 sleep/disable mode, the DIFFSENSE function is disabled and is placed in a high impedance state. Another key feature of the IMP2119 is the master/slave function. Driving this pin HIGH or floating the pin enables the 1.3V DIFFSENSE reference. Driving the pin LOW disables the on board DIFFSENSE reference and enables use of an external master reference device. Block Diagram Internal VREF 1.30V ISO Power ON SE 2.2V 1.07mA LVD 1.25V 200 52.5 SE DISC/HVD LVD(-) / SE SE LVD HVD 52.5 M/S 10mA 1.07mA DIFFSENSE 1 of 9 SE 2.85V, 22.5mA TPWR MODE Control & Delay SE HVD Window Comp. 20kΩ 20 LVD LVD(+) / SE (Pseudo-GND) Latch SE HVD LVD LVD DIFF_CAP Power ON Power ON & MODE Delay 5241/42 01 eps © 2002 IMP, Inc. Data Communications 1 IMP2 1 1 9 Pin Configuration TSSOP-28 NC 1 28 TPWR R1P 2 27 NC R1N 3 26 R 9 N R2P 4 25 R9P R2N 5 24 R 8 N HS GND 6 IMP2119 23 R8P R3P 7 22 HS GND R3N 8 21 R7N R4P 9 20 R7P R4N 10 19 R 6 N R5P 11 18 R6P R 5 N 12 ISO 17 DIFF_CAP 16 DIFFSENSE 13 15 MASTER/SLAVE GND 14 PW Package Ordering Information Part Number IMP2119CPW Note: Temperature Range Package 0°C to 70°C 28-pin Plastic TSSOP For Tape and Reel, append the letter “T” to part number. (i.e. IMP2119CPW/T) 5241/42_t02.eps Absolute Maximum Ratings1 TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . +7V Operating Junction Temperature Plastic (DB, PW Packages) . . . . . . . . . . . . . 150°C Storage Temperature Range . . . . . . . . . . . . . . –65°C to 150°C Lead Temperature (Soldering, 10 sec.) . . . . . . 300°C Note: 1. Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. Thermal Data PW Package: Thermal Resistance Junction-to-Ambient, θJA . . . . . . 100°C/W 2 Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. No ambient airflow is assumed. 408-432-9100/www.impweb.com © 2002 IMP, Inc. IMP2 1 1 9 Pin Description Pin Name R(1,2,3,4,5,6,7,8)N , R(1,2,3,4,5,6,7,8)P TPWR IS O GND MASTER / SLAVE D IFFSENSE DIFF_CAP N.C. © 2002 IMP, Inc. Function Negative signal termination lines for LVD mode. Signal termination lines for SE mode. Positive signal termination lines for LVD mode. Pseudo-ground lines for SE mod e. Power supply pin for terminator. Connect to SCSI bus TermPwr. Must be decoupled by one 4.7µF low-ESR capacitor for every three terminator devices. It is absolutely necessary to connect this pin to the decoupling capacitor through a very low impedance (big traces on PCB). Keeping distances very short from the decoupling capacitors to the TPWR pin is also critical. The value of the decoupling capacitor is somewhat layout dependant and some applications may benefit from an additional 0.1µF decoupling capacitor at the TPWR pin. Enables / disables terminator. See Table 2 for logic lev els Terminator ground pin. Connect to gro.und Sometimes referred to as M/S pin. Used to select which terminator is the controlling device. MASTER/SLAVE pin HIGH or Open enables the DIFFSENSE output drive. See Table 1. This is a dual function pin. It drives the SCSI bus DIFFSENS line. It is also the sense pin to detect the SCSI bus mode (LVD, SE or HVD). DIFFSENSE output drive can be disabled with a LOW level on the MASTER/SLAVE pin. See Table 1 and Table 2. Internally connected to DIFF _CAP pin trough 20Kohms resistor. Internally connected to DIFFSENSE pin through 20kΩ resistor. It can be used as a mode sense pin when the device is a non-controlling terminator (MASTER/SLAVE pin is LOW). An RC filter (20kΩ / 0.1µF) is not required on the IMP2119 , as it has an internal timer. No Connect. Pins should be left open. Data Communications 3 IMP2 1 1 9 Recommended Operating Conditions2 Parameter Max Units 3.0 5.25 V 3.5 5.25 Signal Line Voltage 0 5.0 V Disconnect Input Voltage 0 VTERM V Operating Virtual Junction Temperature Range 0 70 TermPwr Voltage LVD Symbol Min VTERM SE Note: Typ °C 5241/42_t03.eps 2. Range over which the device is functional. Electrical Characteristics Unless otherwise specified, these specifications apply over the operating ambient temperature range of 0°C ≤ TA ≤ 70°C. TermPwr = 4.75V. ISO : IMP2119 = LOW. Low duty cycle pulse testing techniques are used which maintain junction and case temperatures equal to the ambient temperature. Parameter Symbol Condition Min Typ Max Units LVD Terminator Section TermPwr Supply Current Common Mode Voltage Offset Voltage Differential Terminator Impedance Common Mode Impedance Output Capacitance Output Leakage Mode Change Delay DIFFSENSE Section DIFFSENSE Output Voltage DIFFSENSE Output Source Current DIFFSENSE Sink Current DIFFSENSE Output Leakage LVD ICC VCM VFSB ZD ZCM CO ILEAK tDF All terminator lines = Open ISO> 2.0 V Open circuit between – and + (see Note 3) VOUT differential = –1V to 1V 0V to 2.5V ISO > 2.0 .0 V ISO > 2.0V VLINE = 0V to 4V, TA = 25°C ISO > 2.0 V TPWR = 0V, V LINE = 2.7V DIFFSENSE = 1.4V to 0V VDIFF IDIFF VDIFF = 0V ISINK (DIFF) VDIFF = 2.75V ISO > 2.0V ILEAK (DIFF) TA = 25°C 1.125 100 100 100 25 1 1.25 11 2 105 200 2.5 30 35 1.375 125 110 300 2 mA µA V mV Ω Ω pF µA 1 115 1.2 5.0 ms 1. 3 1.4 15.0 200 10 V mA µA µA 7 214 15 2.85 23 65 2. 5 10 226 35 mA Single-Ended Terminator Section TermPwr Supply Current Terminator Output High Voltage Output Current Sink Current Output Capacitance Leakage Current Ground Driver Impedance SE ICC VO IO ISINK CO ILEAK ZG All terminator lines = Open, MASTER/SLAVE = 0V All terminator lines = 0.2V, MASTER/SLAVE = 0V DISCONNECT > 2.0V VOUT = 0.2V VOUT = 4V, all lines ISO > 2.0V ISO > 2.0V VOUT = 0V to 4V, TA = 25°C ISO > 2.0 V TPWR = 0V, LINE = 2.7V, TA = 25°C 2.6 21 45 2 I I = 1mA Thermal Shutdown 24 µA V mA mA pF µA 100 150 Ω °C Note: 3. Open circuit fallsafe voltage. 4 408-432-9100/www.impweb.com © 2002 IMP, Inc. IMP2 1 1 9 Electrical Characteristics Parameter Symbol Condition Min Typ Max Units ISO Section ISO Thresholds Input Current 0.8 VTH IIL ISO = 0 V IIH ISO = 2.4V 2.0 V 10 µA 10 0 nA MASTER/SLAVE Section MASTER/SLAVE Thresholds Input Current 0.8 VTH (MS) IIL (MS) MASTER/SLAVE = 0V IIL (MS) MASTER/SLAVE = 2.4V 100 2.0 V 10 µA nA 5241/42_t05.at3 © 2002 IMP, Inc. Data Communications 5 IMP2 1 1 9 Application Information VOD = V(–) – V(+), Logic = 0 NEGATED V(+) VCM 100mV 0V V(–) –100mV 5241/42_05.eps 5241/42_04.eps Figure 1. Bus Voltage Figure 2. VOD – IMP2119 – + IMP2119 + 5241/42_06.eps Figure 3. Table 1. MASTER/SLAVE Function Table MASTER/SLAVE DIFFSENSE Status Output Current L* HiZ 0mA H 1.3V 15mA Source Open (Pull-up) 1.3V 15mA Source 5241/42_t06.at3 * When in the LOW state, the terminator will detect the DIFFSENSE line state. Table 2. DIFFSENSE/Power Up/Power Down Function Table IMP2119 DISCONNECT Outputs DIFFSENSE Status Type L L < 0.5V Enable SE 7mA L 0.7V to 1.9V Enable LVD 21mA L H > 2.4V Disable Hi Z 1mA H X Disable Hi Z 10µA Open X Disable Hi Z 10µA Current 5241/42_t07.eps 6 408-432-9100/www.impweb.com © 2002 IMP, Inc. IMP2 1 1 9 Application Information HOST TPWR PERIPHERAL TPWR 1– 1– 1+ IMP2119 Data Lines (9) 9– 9– 9+ 9+ DIFFSENSE DIFFSENSE ISO ISO 20k 20k M/S GND NC* DIFF_CAP* + Pin 1 4.7µF* 0.1µF TPWR + + + DIFF_CAP* NC* + Pin 1 0.1µF 4.7µF* 1– 1– 1+ 1+ IMP2119 TPWR + IMP2119 Data Lines (9) 9– 9– 9+ 9+ 4.7µF DIFFSENSE DIFFSENSE ISO ISO M/S M/S GND GND DIFF_CAP* NC* + Pin 1 4.7µF* NC* DIFF_CAP* Pin 1 + 4.7µF* TPWR 1– 1– 1+ 1+ IMP2119 9– 9+ 9+ ISO TPWR IMP2119 Data Lines (9) 9– DIFFSENSE DIFFSENSE ISO M/S M/S GND GND NC* DIFF_CAP* + Pin 1 4.7µF* ISO M/S GND 4.7µF TPWR 1+ IMP2119 ISO TPWR DIFF_CAP* NC* + Pin 1 4.7µF* * The capacitor on pin 1 can be placed on the IMP2119CPW. This capacitor is not required with IMP devices. Figure 5. Suggested IMP2119 Universal Application Schematic © 2002 IMP, Inc. Data Communications 7 IMP2 1 1 9 Package Dimensions Inches PW Min Thin Small Shrink Outline (TSSOP) (28-Pin) E 1 2 3 E F A H SEATING PLANE B G L Min Max Thin Small Shrink Outline (TSSOP) (28-Pin) P D Millimeters Max M C 24-Pin (TSSOP).eps A .032 .041 B 0.007 0.012 C 0.0035 0.0079 D 0.378 0.386 E 0.169 0.176 F 0.025 BSC G 0.002 0.005 H – 0.047 L 0.017 0.030 M 0° 8° P 0.246 0.256 *LC – 0.004 * Lead Coplanarity. 0.80 0.19 0.09 9.60 4.30 1.05 0.30 0.20 9.80 4.5 0.65 BSC 0.05 – 0.45 0° 6.25 – 0.15 1.20 0.75 8° 6.50 0.10 5241/42_t01.eps 8 408-432-9100/www.impweb.com © 2002 IMP, Inc. IMP2 1 1 9 IMP, Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Fax: 408-434-1085 e-mail: [email protected] http://www.impweb.com The IMP logo is a registered trademark of IMP, Inc. All other company and product names are trademarks of their respective owners. © 2002 IMP, Inc. Printed in USA Publication #: 7001 Revision: C Issue Date: 11/01/01 Type: Product