INTEGRAL IN74ACT574

IN74ACT574
OCTAL 3-STATE
NONINVERTING D FLIP-FLOP
High-Performance Silicon-Gate CMOS
•
•
•
•
The IN74ACT574 is identical in pinout to the LS/ALS574,
HC/HCT574. The IN74ACT574 may be used as a level converter
for interfacing TTL or NMOS outputs to High Speed CMOS inputs.
Data meeting the setup time is clocked to the outputs with the
rising edge of the Clock. The Output Enable input does not affect
the states of the flip-flops, but when Output Enable is high, all
device outputs are forced to the high-impedance state; thus, data
may be stored even when the outputs are not enabled.
• TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74ACT574N Plastic
IN74ACT574DW SOIC
TA = -40° to 85° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
PIN 20=VCC
PIN 10 = GND
Output
Enable
L
L
L
H
Inputs
Clock
D
H
L
X
L,H,
X
X
X
=
don’t
Z = high impedance
1
Output
Q
H
L
no
change
Z
care
IN74ACT574
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
VOUT
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
mA
±20
IOUT
DC Output Sink/Source Current, per Pin
mA
±50
ICC
DC Supply Current, VCC and GND Pins
mA
±50
PD
Power Dissipation in Still Air, Plastic DIP+
750
mW
SOIC Package+
500
Tstg
Storage Temperature
-65 to +150
°C
260
TL
Lead Temperature, 1 mm from Case for 10
°C
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage (Referenced to GND)
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to
GND)
TJ
Junction Temperature (PDIP)
TA
Operating Temperature, All Package Types
IOH
Output Current - High
IOL
Output Current - Low
t r, tf
Input Rise and Fall Time * VCC =4.5 V
VCC =5.5 V
(except Schmitt Inputs)
*
VIN from 0.8 V to 2.0 V
Min
4.5
0
-40
0
0
Max
5.5
VCC
Unit
V
V
140
+85
-24
24
10
8.0
°C
°C
mA
mA
ns/V
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and
VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
VCC). Unused outputs must be left open.
2
IN74ACT574
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VC Guaranteed Limits
C
Symbol
VIH
VIL
VOH
VOL
IIN
V
25 °C
VOUT=0.1 V or VCC-0.1 V
4.5
5.5
VOUT=0.1 V or VCC-0.1 V
IOUT ≤ -50 µA
Parameter
Test Conditions
Minimum HighLevel Input
Voltage
Maximum Low Level Input
Voltage
Minimum HighLevel Output
Voltage
Maximum LowLevel Output
Voltage
Unit
2.0
2.0
-40°C to
85°C
2.0
2.0
4.5
5.5
0.8
0.8
0.8
0.8
V
4.5
5.5
4.4
5.4
4.4
5.4
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
0.1
3.76
4.76
0.1
0.1
4.5
5.5
5.5
0.36
0.36
±0.1
0.44
0.44
±1.0
µA
1.5
mA
±5.0
µA
75
mA
-75
mA
80
µA
V
*
VIN=VIH or VIL
IOH=-24 mA
IOH=-24 mA
IOUT ≤ 50 µA
V
*
VIN=VIH or VIL
IOL=24 mA
IOL=24 mA
VIN=VCC or GND
Maximum Input
Leakage Current
5.5
Additional Max.
VIN=VCC - 2.1 V
∆ICCT
ICC/Input
5.5
IOZ
Maximum Three- VIN (OE)= VIH or VIL
±0.5
State Leakage
VIN =VCC or GND
Current
VOUT =VCC or GND
VOLD=1.65 V Max
IOLD
+Minimum
5.5
Dynamic Output
Current
VOHD=3.85 V Min
IOHD
+Minimum
5.5
Dynamic Output
Current
VIN=VCC or GND
ICC
Maximum
5.5
8.0
Quiescent Supply
Current
(per Package)
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
3
IN74ACT574
AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)
Guaranteed Limits
Unit
Symbol
Parameter
25 °C
-40°C to
85°C
Min Max Min
Max
fmax
Maximum Clock Frequency (50% Duty 100
85
MHz
Cycle) (Figure 1)
tPLH
Propagation Delay, Clock to Q (Figure 1)
2.5
11
2.0
12
ns
tPHL
Propagation Delay, Clock to Q (Figure 1)
2.0
10
1.5
11
ns
tPZH
Propagation Delay, Output Enable to Q 2.0
9.5
1.5
10
ns
(Figure 2)
tPZL
Propagation Delay, Output Enable to Q 2.0
9.0
1.5
10
ns
(Figure 2)
tPHZ
Propagation Delay, Output Enable to Q 2.0 10.5 1.5
11.5
ns
(Figure 2)
tPLZ
Propagation Delay, Output Enable to Q 2.0
8.5
1.5
9.0
ns
(Figure 2)
CIN
Maximum Input Capacitance
4.5
4.5
pF
CPD
Typical @25°C,VCC=5.0 V
40
Power Dissipation Capacitance
TIMING REQUIREMENTS (VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)
Guaranteed Limit
Symbol
Parameter
25°C
-40°C to 85°C
tSU
Minimum Setup Time, Data to Clock
2.5
2.5
(Figure 3)
th
Minimum Hold Time, Clock to Data
1.0
1.0
(Figure 3)
tw
Minimum Pulse Width, Clock (Figure
3.0
4.0
1)
4
pF
Unit
ns
ns
ns
IN74ACT574
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
EXPANDED LOGIC DIAGRAM
5