INTEGRAL IN74HC05A

TECHNICAL DATA
IN74HC05A
Hex Inverter
with Open-Drain Outputs
High-Performance Silicon-Gate CMOS
The IN74HC05A is identical in pinout to the LS/ALS05. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device contains six independent gates, each of which performs
the logic INVERT function. The open-drain outputs require external
pull-up resistors for proper logical operation. They may be connected
to other open-drain outputs to implement active-high wired-AND
functions.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
ORDERING INFORMATION
IN74HC05AN Plastic
IN74HC05AD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
FUNCTION TABLE
PIN 14 =VCC
PIN 7 = GND
Inputs
Output
A
Y
L
Z
H
L
Z = High Impedance
31
IN74HC05A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
-55
+125
°C
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
32
IN74HC05A
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC
Guaranteed Limit
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
VOUT=0.1 V
IOUT≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
Maximum Low Level Input Voltage
VOUT= VCC-0.1 V or 0.1 V
IOUT ≤ 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
Maximum Low-Level
Output Voltage
VIN=VIH
IOUT ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Symbol
Parameter
VIH
Minimum High-Level
Input Voltage
VIL
VOL
Test Conditions
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
6.0
1.0
10
40
µA
IOZ
Maximum ThreeState Leakage
Current
Output in High-Impedance
State
VIN= VIL or VIH
IOUT= VCC or GND
6.0
±0.5
±5.0
±10
µA
33
IN74HC05A
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
V
25 °C
to
-55°C
≤85°C
≤125°C
Unit
Maximum Propagation Delay, Input A to
Output Y (Figures 1 and 2)
2.0
4.5
6.0
125
24
20
150
30
26
180
36
31
ns
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN
Maximum Input Capacitance
-
10
10
10
pF
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
-
10
10
10
pF
Symbol
tPLZ, tPZL
COUT
Parameter
Power Dissipation Capacitance (Per Gate)
CPD
Typical @25°C,VCC=5.0 V
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Figure 1. Switching Waveforms
8.0
Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/6 of the Device)
*
34
Denotes open-drain outputs
pF