IN74HCT126A QUAD 3-STATE NONINVERTING BUFFERS High-Performance Silicon-Gate CMOS The IN74HCT126A is identical in pinout to the LS/ALS126. The IN74HCT126A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The IN74HCT126A noninverting buffers are designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The devices have four separate output enables that are active-high. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION IN74HCT126AN Plastic IN74HCT126AD SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs Output A OE Y H H H L H L X L Z X = don’t care Z = high impedance PIN 14 =VCC PIN 7 = GND 1 IN74HCT126A MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA ±20 IOUT DC Output Current, per Pin mA ±35 ICC DC Supply Current, VCC and GND Pins mA ±75 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 °C 260 TL Lead Temperature, 1 mm from Case for 10 °C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types t r, tf Input Rise and Fall Time (Figure 1) Min 4.5 0 Max 5.5 VCC Unit V V -55 0 +125 500 °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74HCT126A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V ≤85 ≤125 25 °C to °C °C -55°C VOUT= VCC-0.1 V VIH Minimum High4.5 2.0 2.0 2.0 Level Input 5.5 2.0 2.0 2.0 IOUT≤ 20 µA Voltage VOUT=0.1 V VIL Maximum Low 4.5 0.8 0.8 0.8 Level Input 5.5 0.8 0.8 0.8 IOUT ≤ 20 µA Voltage VIN=VIH VOH Minimum High4.5 4.4 4.4 4.4 Level Output 5.5 5.4 5.4 5.4 IOUT ≤ 20 µA Voltage VIN=VIH 4.5 3.98 3.84 3.7 IOUT ≤ 6.0 mA VIN=VIL VOL Maximum Low4.5 0.1 0.1 0.1 Level Output 5.5 0.1 0.1 0.1 IOUT ≤ 20 µA Voltage VIN=VIL 4.5 0.26 0.33 0.4 IOUT ≤ 6.0 mA IIN Maximum Input VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 Leakage Current IOZ Maximum Three- Output in High5.5 ±0.5 ±5.0 ±10 Impedance State State Leakage VIN=VIL or VIH Current VOUT=VCC or GND VIN=VCC or GND ICC Maximum 5.5 8.0 80 160 Quiescent Supply IOUT=0µA Current (per Package) VIN = 2.4 V, Any One Additional ≥-55°C 25°C to ∆ICC Quiescent Supply Input 125°C VIN=VCC or GND, Other Current Inputs 5.5 2.9 2.4 IOUT=0µA 3 Unit V V V V µA µA µA mA IN74HCT126A AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Symbol Parameter 25 °C ≤85°C ≤125° Unit C to -55°C tPLH, Maximum Propagation Delay, Input A to 23 30 35 ns tPHL Output Y (Figures 1 and 3) tPLZ, Maximum Propagation Delay, Output 32 38 48 ns tPHZ Enable toY (Figures 2 and 4) tPZL, Maximum Propagation Delay, Output 22 28 34 ns tPZH Enable toY (Figures 2 and 4) 12 15 18 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) CIN Maximum Input Capacitance 10 10 10 pF 15 15 15 pF COUT Maximum Three-State Output Capacitance (Output in High-Impedance State) CPD Power Dissipation Capacitance (Per Buffer) Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms Typical @25°C,VCC=5.0 V 55 pF Figure 2. Switching Waveforms 4 IN74HCT126A Figure 3. Test Circuit Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM (1/4 of the Device) 5