TI SN74LVC2T45DCTRE4

SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
FEATURES
•
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.65-V to
5.5-V Power-Supply Range
VCC Isolation Feature – If Either VCC Input Is at
GND, Both Ports Are in the High-Impedance
State
DIR Input Circuit Referenced to VCCA
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode
Operation
Max Data Rates
– 420 Mbps (3.3-V to 5-V Translation)
– 210 Mbps (Translate to 3.3 V)
– 140 Mbps (Translate to 2.5 V)
– 75 Mbps (Translate to 1.8 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCT OR DCU PACKAGE
(TOP VIEW)
VCCA
A1
A2
GND
1
8
2
7
3
6
4
5
VCCB
B1
B2
DIR
YZP PACKAGE
(BOTTOM VIEW)
GND
D1
4 5
D2
A2
A1
C1
3
6
C2
B1
2 7
B2
VCCA
A1
1 8
A2
DIR
B2
B1
VCCB
DESCRIPTION/ORDERING INFORMATION
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track
VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional
translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
ORDERING INFORMATION
PACKAGE (1)
TA
NanoFree – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
–40°C to 85°C
SSOP – DCT
VSSOP – DCU
(1)
(2)
ORDERABLE PART NUMBER
Reel of 3000
SN74LVC2T45YZPR
Reel of 3000
SN74LVC2T45DCTR
Reel of 250
SN74LVC2T45DCTT
Reel of 3000
SN74LVC2T45DCUR
Reel of 250
SN74LVC2T45DCUT
TOP-SIDE MARKING (2)
_ _ _TB_
CT2_ _ _
CT2_
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated
SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits
data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when
the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic
HIGH or LOW level applied to prevent excess ICC and ICCZ.
The SN74LVC2T45 is designed so that the DIR input circuit is supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
FUNCTION TABLE (1)
(EACH TRANSCEIVER)
(1)
INPUT
DIR
OPERATION
L
B data to A bus
H
A data to B bus
Input circuits of the data I/Os
always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
DIR
A1
5
2
7
A2
3
6
VCCA
2
B1
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VCCB
B2
SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
VCCA
VCCB
UNIT
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
DCT package
220
DCU package
227
YZP package
(1)
(2)
(3)
(4)
V
°C/W
102
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
Recommended Operating Conditions (1) (2) (3)
VCCI
VCCA
VCCB
VCCO
Supply voltage
High-level
input voltage
2.3 V to 2.7 V
Data inputs (4)
MAX
1.65
5.5
1.65
5.5
1.7
3 V to 3.6 V
VCCI × 0.7
VCCI × 0.35
1.65 V to 1.95 V
VIL
Data inputs (4)
2.3 V to 2.7 V
0.7
3 V to 3.6 V
0.8
VCCA × 0.65
1.65 V to 1.95 V
High-level
input voltage
DIR
(referenced to VCCA) (5)
2.3 V to 2.7 V
1.7
3 V to 3.6 V
VCCA × 0.7
4.5 V to 5.5 V
VCCA × 0.35
2.3 V to 2.7 V
0.7
3 V to 3.6 V
0.8
VIL
Low-level
input voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCCO
V
1.65 V to 1.95 V
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition
rise or fall rate
Data inputs
Control input
TA
(1)
(2)
(3)
(4)
(5)
V
VCCA × 0.3
4.5 V to 5.5 V
4
V
2
1.65 V to 1.95 V
DIR
(referenced to VCCA) (5)
V
VCCI × 0.3
4.5 V to 5.5 V
VIH
V
V
2
4.5 V to 5.5 V
Low-level
input voltage
UNIT
VCCI × 0.65
1.65 V to 1.95 V
VIH
MIN
–4
2.3 V to 2.7 V
–8
3 V to 3.6 V
–24
4.5 V to 5.5 V
–32
1.65 V to 1.95 V
4
2.3 V to 2.7 V
8
3 V to 3.6 V
24
4.5 V to 5.5 V
32
1.65 V to 1.95 V
20
2.3 V to 2.7 V
20
3 V to 3.6 V
10
4.5 V to 5.5 V
5
1.65 V to 5.5 V
5
Operating free-air temperature
–40
85
mA
mA
ns/V
°C
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
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SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
Electrical Characteristics
(1) (2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –8 mA
1.65 V to 4.5 V
1.65 V to 4.5 V
1.65 V
1.65 V
1.2
2.3 V
2.3 V
1.9
3V
3V
2.4
3.8
VI = VIH
IOH = –24 mA
A port
B port
A or B
port
IOZ
ICCA
0.1
1.65 V
0.45
2.3 V
2.3 V
0.3
3V
3V
0.55
VI = VCCA or GND
VO = VCCO or GND
VI = VCCI or GND, IO = 0
One A port at VCCA – 0.6 V,
DIR at VCCA,
B port = open
DIR
DIR at VCCA – 0.6 V,
B port = open,
A port at VCCA or GND
∆ICCB
B port
One B port at VCCB – 0.6 V,
DIR at GND, A port = open
CI
DIR
Cio
A or B
port
(1)
(2)
4.5 V
4.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
±1
±2
V
0.55
0V
0 to 5.5 V
±1
±2
0 to 5.5 V
0V
±1
±2
1.65 V to 5.5 V
1.65 V to 5.5 V
±1
±2
1.65 V to 5.5 V
1.65 V to 5.5 V
5V
0V
2
0V
5V
–2
1.65 V to 5.5 V
1.65 V to 5.5 V
3
5V
0V
–2
0V
5V
2
1.65 V to 5.5 V
1.65 V to 5.5 V
4
VI or VO = 0 to 5.5 V
A port
∆ICCA
V
1.65 V
VI = VIL
UNIT
VCCO – 0.1
4.5 V
VI = VCCI or GND, IO = 0
ICCA + ICCB
(see Table 1)
MAX
1.65 V to 4.5 V
VI = VCCI or GND, IO = 0
ICCB
MIN
4.5 V
IOL = 32 mA
Ioff
MAX
1.65 V to 4.5 V
IOL = 24 mA
DIR
TYP
IOL = 100 µA
IOL = 8 mA
II
MIN
IOH = –32 mA
IOL = 4 mA
VOL
–40°C to 85°C
VCCB
IOH = –4 mA
VOH
TA = 25°C
VCCA
µA
µA
µA
3
µA
µA
µA
50
3 V to 5.5 V
µA
3 V to 5.5 V
50
50
µA
3 V to 5.5 V
3 V to 5.5 V
VI = VCCA or GND
3.3 V
3.3 V
2.5
pF
VO = VCCA/B or GND
3.3 V
3.3 V
6
pF
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
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SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL (1)
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3
17.7
2.2
10.3
1.7
8.3
1.4
7.2
2.8
14.3
2.2
8.5
1.8
7.1
1.7
7
3
17.7
2.3
16
2.1
15.5
1.9
15.1
2.8
14.3
2.1
12.9
2
12.6
1.8
12.2
10.6
30.9
10.3
30.5
10.5
30.5
10.7
29.3
7.3
19.7
7.5
19.6
7.5
19.5
7
19.4
10
27.9
8.4
14.9
6.5
11.3
4.1
8.6
6.5
19.5
7.2
12.6
4.3
9.7
2.1
7.1
37.2
28.6
25.2
22.2
42.2
27.8
23.9
20.8
37.4
29.9
27.8
26.6
45.2
39
37.6
36.3
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL
(1)
6
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.3
16
1.5
8.5
1.3
6.4
1.1
5.1
2.1
12.9
1.4
7.5
1.3
5.4
0.9
4.6
2.2
10.3
1.5
8.5
1.4
8
1
7.5
2.2
8.5
1.4
7.5
1.3
7
0.9
6.2
6.6
17.1
7.1
16.8
6.8
16.8
5.2
16.5
5.3
12.6
5.2
12.5
4.9
12.3
4.8
12.3
10.7
27.9
8.1
13.9
5.8
10.5
3.5
7.6
7.8
18.9
6.2
11.2
3.6
8.9
1.4
6.2
29.2
19.7
16.9
13.7
36.4
21.4
17.5
13.8
28.6
21
18.7
17.4
30
24.3
22.2
21.1
The enable time is a calculated value, derived using the formula shown in the enable times section.
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ns
ns
ns
ns
ns
ns
SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL (1)
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.1
15.5
1.4
8
0.7
5.6
0.7
4.4
2
12.6
1.3
7
0.8
5
0.7
4
1.7
8.3
1.3
6.4
0.7
5.8
0.6
5.4
1.8
7.1
1.3
5.4
0.8
5
0.7
4.5
5
10.9
5.1
10.8
5
10.8
5
10.4
3.4
8.4
3.7
8.4
3.9
8.1
3.3
7.8
11.2
27.3
8
13.7
5.8
10.4
2.9
7.4
9.4
17.7
5.6
11.3
4.3
8.3
1
5.6
26
17.7
14.1
11
34.4
19.1
15.4
11.9
23.9
16.4
13.9
12.2
23.5
17.8
15.8
14.4
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL
(1)
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.9
15.1
1
7.5
0.6
5.4
0.5
3.9
1.8
12.2
0.9
6.2
0.7
4.5
0.5
3.5
1.4
7.2
1
5.1
0.7
4.4
0.5
3.9
1.7
7
0.9
4.6
0.7
4
0.5
3.5
2.9
8.2
2.9
7.9
2.8
7.9
2.2
7.8
1.4
6.9
1.3
6.7
0.7
6.7
0.7
6.6
11.2
26.1
7.2
13.9
5.8
10.1
1.3
7.3
8.4
16.9
5
11
4
7.7
1
5.6
24.1
16.1
12.1
9.5
33.1
18.5
14.1
10.8
22
14.2
12.1
10.5
20.4
14.1
12.4
11.3
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
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SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
Operating Characteristics
TA = 25°C
PARAMETER
CpdA
CpdB
(1)
8
(1)
A-port input,
B-port output
B-port input,
A-port output
(1)
A-port input,
B-port output
B-port input,
A-port output
TEST
CONDITIONS
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
VCCA =
VCCB = 5 V
TYP
TYP
TYP
TYP
3
4
4
4
18
19
20
21
18
19
20
21
3
4
4
4
UNIT
pF
pF
Power dissipation capacitance per transceiver
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SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
Power-Up Considerations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up VCCA.
3. VCCB can be ramped up along with or after VCCA.
Table 1. Typical Total Static Power Consumption (ICCA + ICCB)
VCCB
VCCA
0V
1.8 V
2.5 V
3.3 V
5V
<1
0V
0
<1
<1
<1
1.8 V
<1
<2
<2
<2
2
2.5 V
<1
<2
<2
<2
<2
3.3 V
<1
<2
<2
<2
<2
5V
<1
2
<2
<2
<2
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UNIT
µA
9
SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS
abc
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 1.8 V
10
10
9
9
VCCB = 1.8 V
8
8
7
7
6
6
t PLH− ns
t PHL − ns
VCCB = 1.8 V
VCCB = 2.5 V
5
VCCB = 2.5 V
5
VCCB = 3.3 V
4
4
VCCB = 5 V
VCCB = 3.3 V
3
3
VCCB = 5 V
2
2
1
1
0
0
0
5
10
15
20
25
30
0
35
5
10
15
20
25
30
35
CL − pF
CL − pF
TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 1.8 V
10
10
9
9
8
VCCB = 1.8 V
8
VCCB = 2.5 V
7
7
6
6
5
VCCB = 2.5 V
VCCB = 3.3 V
4
VCCB = 5 V
t PLH − ns
t PHL − ns
VCCB = 1.8 V
VCCB = 3.3 V
VCCB = 5 V
5
4
3
3
2
2
1
1
0
0
0
5
10
15
20
25
30
35
0
5
CL − pF
10
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10
15
20
CL − pF
25
30
35
SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS
abc
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 2.5 V
10
10
9
9
8
8
7
VCCB = 1.8 V
6
t PLH − ns
t PHL − ns
7
VCCB = 1.8 V
6
5
VCCB = 2.5 V
4
4
VCCB = 3.3 V
3
3
VCCB = 5 V
5
VCCB = 2.5 V
VCCB = 3.3 V
2
2
VCCB = 5 V
1
1
0
0
0
10
5
15
20
25
30
0
35
10
5
15
20
25
30
35
CL − pF
CL − pF
10
10
9
9
8
8
7
7
6
6
t PLH − ns
t PHL − ns
TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 2.5 V
VCCB = 1.8 V
5
4
5
4
3
VCCB = 3.3 V
VCCB = 5 V
2
VCCB = 2.5 V
VCCB = 3.3 V
3
VCCB = 2.5 V
VCCB = 5 V
2
1
0
VCCB = 1.8 V
1
0
5
10
15
20
CL − pF
25
30
35
0
0
5
10
15
20
25
30
35
CL − pF
Submit Documentation Feedback
11
SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS
abc
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 3.3 V
10
10
9
9
8
8
7
7
VCCB = 1.8 V
6
6
t PLH − ns
t PHL − ns
VCCB = 1.8 V
5
VCCB = 2.5 V
4
3
VCCB = 2.5 V
5
4
VCCB = 3.3 V
3
VCCB = 5 V
2
2
VCCB = 3.3 V
1
1
VCCB = 5 V
0
0
0
5
10
15
20
25
30
0
35
5
10
15
20
25
30
35
CL − pF
CL − pF
10
10
9
9
8
8
7
7
6
6
t PLH − ns
t PHL − ns
TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 3.3 V
5
VCCB = 1.8 V
4
3
VCCB = 1.8 V
5
4
3
2
VCCB = 3.3 V
VCCB = 3.3 V
1
VCCB = 2.5 V
2
VCCB = 2.5 V
1
VCCB = 5 V
0
VCCB = 5 V
0
0
5
10
15
20
25
30
35
0
5
12
10
15
CL − pF
CL − pF
Submit Documentation Feedback
20
25
30
35
SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS
abc
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 5 V
10
10
9
9
8
8
7
7
VCCB = 1.8 V
VCCB = 1.8 V
t PLH − ns
t PHL − ns
6
5
4
6
5
VCCB = 2.5 V
4
VCCB = 2.5 V
VCCB = 3.3 V
3
3
2
2
VCCB = 5 V
VCCB = 3.3 V
1
0
1
VCCB = 5 V
0
0
5
10
15
20
25
30
35
0
5
10
CL − pF
15
20
25
30
35
25
30
35
CL − pF
10
10
9
9
8
8
7
7
6
6
t PLH − ns
t PHL− ns
TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 5 V
5
4
VCCB = 1.8 V
3
VCCB = 2.5 V
5
VCCB = 1.8 V
4
VCCB = 2.5 V
3
2
2
VCCB = 3.3 V
VCCB = 3.3 V
VCCB = 5 V
1
0
0
5
10
VCCB = 5 V
1
15
20
25
30
35
0
0
5
CL − pF
10
15
20
CL − pF
Submit Documentation Feedback
13
SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.15 V
0.15 V
0.3 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
tPLZ
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPHZ
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
14
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SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
APPLICATION INFORMATION
The following shows an example of the SN74LVC2T45 being used in a unidirectional logic level-shifting
application.
VCC1
VCC2
VCC1
VCC2
1
8
2
7
3
6
4
5
VCC2
VCC1
SYSTEM-1
SYSTEM-2
PIN
NAME
FUNCTION
1
VCCA
VCC1
SYSTEM-1 supply voltage (1.65 V to 5.5 V)
DESCRIPTION
2
A1
OUT1
Output level depends on VCC1 voltage.
3
A2
OUT2
Output level depends on VCC1 voltage.
4
GND
GND
Device GND
5
DIR
DIR
GND (low level) determines B-port to A-port direction.
6
B2
IN2
Input threshold value depends on VCC2 voltage.
7
B1
IN1
Input threshold value depends on VCC2 voltage.
8
VCCB
VCC2
SYSTEM-2 supply voltage (1.65 V to 5.5 V)
Figure 2. Unidirectional Logic Level-Shifting Application
Submit Documentation Feedback
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SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
APPLICATION INFORMATION
Figure 3 shows the SN74LVC2T45 being used in a bidirectional logic level-shifting application. Since the
SN74LVC2T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
VCC1
VCC1
VCC2
Pullup/Down
or Bus Hold(1)
Pullup/Down
or Bus Hold(1)
I/O-1
VCC2
1
8
2
7
3
6
4
5
I/O-2
DIR CTRL
SYSTEM-1
SYSTEM-2
The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to
SYSTEM-1.
STATE
DIR CTRL
I/O-1
I/O-2
1
H
Out
In
2
H
Hi-Z
Hi-Z
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The
bus-line state depends on pullup or pulldown. (1)
3
L
Hi-Z
Hi-Z
DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or
pulldown. (1)
4
L
In
Out
SYSTEM-2 data to SYSTEM-1
(1)
DESCRIPTION
SYSTEM-1 data to SYSTEM-2
SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 3. Bidirectional Logic Level-Shifting Application
Enable Times
Calculate the enable times for the SN74LVC2T45 using the following formulas:
• tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
• tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
• tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
• tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74LVC2T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC2T45DCTR
ACTIVE
SM8
DCT
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2T45DCTRE4
ACTIVE
SM8
DCT
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2T45DCTRG4
ACTIVE
SM8
DCT
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2T45DCTT
ACTIVE
SM8
DCT
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2T45DCTTE4
ACTIVE
SM8
DCT
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2T45DCTTG4
ACTIVE
SM8
DCT
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2T45DCUR
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2T45DCURE4
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2T45DCURG4
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2T45DCUT
ACTIVE
US8
DCU
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2T45DCUTE4
ACTIVE
US8
DCU
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2T45DCUTG4
ACTIVE
US8
DCU
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC2T45YZPR
ACTIVE
DSBGA
YZP
8
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2008
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC2T45 :
• Enhanced Product: SN74LVC2T45-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVC2T45DCUR
US8
DCU
8
3000
180.0
9.2
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC2T45YZPR
DSBGA
YZP
8
3000
180.0
8.4
1.1
2.1
0.56
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jul-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC2T45DCUR
US8
DCU
8
3000
202.0
201.0
28.0
SN74LVC2T45YZPR
DSBGA
YZP
8
3000
220.0
220.0
34.0
Pack Materials-Page 2
X: Max = 930 µm, Min = 870 µm
Y: Max = 1930 µm, Min = 1870 µm
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
X: Max = 930 µm, Min = 870 µm
Y: Max = 1930 µm, Min = 1870 µm
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