TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 TMS320C5504 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5504 1 Fixed-Point Digital Signal Processor 1.1 TMS320C5504 Features • HIGHLIGHTS: • High-Perf/Low-Power, C55x™ Fixed-Point DSP – 16.67/13.33/10/8.33-ns Instruction Cycle Time – 60-, 75-, 100-, 120-MHz Clock Rate • 256K Bytes On-Chip RAM • 16-/8-Bit External Memory Interface (EMIF) • Two MultiMedia Card/Secure Digital I/Fs • Serial-Port I/F (SPI) With Four Chip-Selects • Four Inter-IC Sound (I2S Bus™) • USB 2.0 Full- and High-Speed Device • Real-Time Clock (RTC) With Crystal Input • Four Core Isolated Power Supply Domains • Four I/O Isolated Power Supply Domains • One integrated LDO • Industrial Temperature Devices Available • 1.05-V Core, 1.8/2.5/2.8/3.3-V I/Os • 1.3-V Core, 1.8/2.5/2.8/3.3-V I/Os • FEATURES: • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor – 16.67-, 13.33, 10-, 8.33-ns Instruction Cycle Time – 60-, 75-, 100-, 120-MHz Clock Rate – One/Two Instruction(s) Executed per Cycle – Dual Multipliers [Up to 200 or 240 Million Multiply-Accumulates per Second (MMACS)] – Two Arithmetic/Logic Units (ALUs) – Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses – Fully Software-Compatible With C55x Devices – Industrial Temperature Devices Available • 256 K Bytes Zero-Wait State On-Chip RAM, Composed of: – 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit – 192K Bytes of Single-Access RAM (SARAM), 24 Blocks of 4K x 16-Bit • 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit) • 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM) • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to: – 8-/16-Bit NAND Flash, 1- and 4-Bit ECC – 8-/16-Bit NOR Flash – Asynchronous Static RAM (SRAM) – 16-bit SDRAM/mSDRAM (1.8-, 2.5-, and 3.3-V) • Direct Memory Access (DMA) Controller – Four DMA With 4 Channels Each (16-Channels Total) • Three 32-Bit General-Purpose Timers – One Selectable as a Watchdog and/or GP • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces • Universal Asynchronous Receiver/Transmitter (UART) • Serial-Port Interface (SPI) With Four Chip-Selects • Master/Slave Inter-Integrated Circuit (I2C Bus™) • Four Inter-IC Sound (I2S Bus™) for Data Transport • Device USB Port With Integrated 2.0 High-Speed PHY that Supports: – USB 2.0 Full- and High-Speed Device • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain, Separate Power Supply • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO • One integrated LDO (ANA_LDO) to power DSP PLL (VDDA_PLL) • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible • Up to 26 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2010, Texas Instruments Incorporated PRODUCT PREVIEW 1 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com • 1.05-V Core (60 or 75MHz), 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/Os • 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/Os • Applications: – Wireless Audio Devices (e.g., Headsets, Microphones, Speakerphones, etc.) – Echo Cancellation Headphones – Portable Medical Devices – Voice Applications – Industrial Controls – Fingerprint Biometrics – Software Defined Radio • Community Resources – TI E2E Community – TI Embedded Processors Wiki PRODUCT PREVIEW 2 Fixed-Point Digital Signal Processor Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com 1.2 SPRS659 – JANUARY 2010 Description The TMS320C5504 is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. The TMS320C5504 fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The TMS320C5504 also includes four DMA controllers, each with 4 channels, providing data movements for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity. The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface. The C5504 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator. The device includes one integrated LDO (ANA_LDO) to provide regulated 1.3 V to the DSP PLL (VDDA_PLL). The C5504 is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The C5504 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, and various math functions) as well as chip support libraries. Fixed-Point Digital Signal Processor Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 3 PRODUCT PREVIEW The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. TMS320C5504 SPRS659 – JANUARY 2010 1.3 www.ti.com Functional Block Diagram Figure 1-1 shows the functional block diagram of the C5504 device. DSP System JTAG Interface Input Clock(s) C55x™ DSP CPU PLL/Clock Generator 64 KB DARAM Power Management 192 KB SARAM Pin Multiplexing 128 KB ROM Switched Central Resource (SCR) Peripherals Serial Interfaces PRODUCT PREVIEW I2S (x4) I2C SPI Interconnect Connectivity DMA (x4) USB 2.0 PHY (HS) [DEVICE] Program/Data Storage UART NAND, NOR, SRAM, SDRAM/mSDRAM MMC/SD (x2) System RTC GP Timer (x2) GP Timer or WD LDO Figure 1-1. TMS320C5504 Functional Block Diagram 4 Fixed-Point Digital Signal Processor Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com 2 3 4 ............... 1 1.1 TMS320C5504 Features ............................. 1 1.2 Description ........................................... 3 1.3 Functional Block Diagram ............................ 4 Device Overview ........................................ 6 2.1 Device Characteristics ............................... 6 2.2 C55x CPU ............................................ 8 2.3 Memory Map Summary ............................. 13 2.4 Pin Assignments .................................... 14 2.5 Terminal Functions ................................. 15 2.6 Device Support ..................................... 36 Device Configuration ................................. 39 3.1 System Registers ................................... 39 3.2 Power Considerations .............................. 40 3.3 Clock Considerations ............................... 41 3.4 Boot Sequence ..................................... 43 3.5 Configurations at Reset ............................ 46 3.6 Configurations After Reset ......................... 46 3.7 Multiplexed Pin Configurations ..................... 50 3.8 Debugging Considerations ......................... 53 Device Operating Conditions ....................... 55 Fixed-Point Digital Signal Processor 4.1 4.2 4.3 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) .... 55 Recommended Operating Conditions .............. 56 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) ............ 57 5 Peripheral Information and Electrical Specifications .......................................... 58 5.1 5.2 Parameter Information .............................. 58 Recommended Clock and Control Signal Transition Behavior ............................................ 59 5.3 5.4 Power Supplies ..................................... 59 External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins ...................................... 62 5.5 ......................................... ........... Reset ............................................... Interrupts and XF ................................... External Memory Interface (EMIF) ................. Multimedia Card/Secure Digital (MMC/SD) ........ Real-Time Clock (RTC) ............................. Inter-Integrated Circuit (I2C) ........................ 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 6 Clock PLLs 66 Direct Memory Access (DMA) Controller 69 70 72 73 87 92 94 Universal Asynchronous Receiver/Transmitter (UART) .............................................. 99 ............................... Serial Port Interface (SPI) ......................... Universal Serial Bus (USB) 2.0 Controller ........ General-Purpose Timers .......................... General-Purpose Input/Output .................... IEEE 1149.1 JTAG ................................ Inter-IC Sound (I2S) 101 107 110 117 119 123 Mechanical Packaging and Orderable Information ............................................ 125 6.1 Thermal Data for ZCH 6.2 Packaging Information ............................. ............................ Contents Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 125 125 5 PRODUCT PREVIEW 1 SPRS659 – JANUARY 2010 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com 2 Device Overview 2.1 Device Characteristics Table 2-1, provides an overview of the TMS320C5504 DSP. The tables show significant features of the C5504 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. For more detailed information on the actual device P/N and maximum device operating frequency, see Section 2.6.2, Device and Development-Support Tool Nomenclature. Table 2-1. Characteristics of the C5504 Processor HARDWARE FEATURES C5504 Asynchronous (8/16-bit bus width) SRAM, Flash (NOR, NAND), SDRAM and Mobile SDRAM (16-bit bus width) (1) Peripherals External Memory Interface (EMIF) Not all peripheral pins are available at the same time Flash Cards (for more detail, see the Device Configurations DMA section). 2 MMC/SD Four DMA controllers each with four channels, for a total of 16 channels PRODUCT PREVIEW Timers 2 32-Bit General-Purpose (GP) Timers 1 Additional Configurable as a 32-Bit GP Timer and/or a Watchdog UART 1 (with RTS/CTS flow control) SPI 1 with 4 chip selects I2C 1 (Master/Slave) I2S 4 (Two Channel, Full Duplex Communication) USB 2.0 (Device only) High- and Full-Speed Device 256 byte read/write buffer, max 50-MHz clock for SD cards, and signaling for DMA transfers MMC/SD Real-Time Clock (RTC) 1 (Crystal Input, Separate Clock Domain and Power Supply) General-Purpose Input/Output Port (GPIO) Up to 26 pins (with 1 Additional General-Purpose Output (XF)) Size (Bytes) On-Chip Memory • • • Organization JTAG BSDL_ID JTAGID Register (Value is: 0009_702F) CPU Frequency MHz Cycle Time ns Voltage 256 KB RAM, 128KB ROM 64KB On-Chip Dual-Access RAM (DARAM) 192 KB On-Chip Single-Access RAM (SARAM) 128KB On-Chip Single-Access ROM (SAROM) see Figure 5-33 1.05-V Core 60 or 75 MHz 1.3-V Core 100, 120 MHz 1.05-V Core 16.67, 13.3 ns 1.3-V Core 10, 8.33 ns 1.05 V (60, 75 MHz) Core (V) 1.3 V (100, 120 MHz) I/O (V) 1.8 V, 2.5 V, 2.8 V, 3.3 V 1.3 V, TBD mA max current for PLL (VDDA_PLL) and power management circuits (VDDA_ANA) LDO ANA_LDO Power Characterization Active @ Room Temp 25°C, 75% DMAC + 25% ADD (Typical Sine Wave Data Switching) 0.15 mW/MHz @ 1.05 V, 60 or 75 MHz 0.22 mW/MHz @ 1.3 V, 100 or 120 MHz Active @ Room Temp 25°C, 75% DMAC + 25% NOP (Typical Sine Wave Data Switching) 0.14 mW/MHz @ 1.05 V, 60 or 75MHz 0.22 mW/MHz @ 1.3 V, 100 or 120 MHz Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) 0.26 mW @ 1.05 V 0.44 mW @ 1.3 V (1) 6 For more compatibility with SDRAM devices, see Section 5.9 , External Memory Interface (EMIF). Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 2-1. Characteristics of the C5504 Processor (continued) HARDWARE FEATURES C5504 Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) 0.23 mW @ 1.05 V 0.40 mW @ 1.3 V Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) 0.15 mW @ 1.05 V 0.28 mW @ 1.3 V PLL Options Software Programmable Multiplier BGA Package 10 x 10 mm Process Technology mm Product Status 196-Pin BGA (ZCH) 0.09 mm Product Preview (PP), Advance Information (AI), or Production Data (PD) PP PRODUCT PREVIEW information concerns experimental products (designated as TMX) that are in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. PRODUCT PREVIEW (2) (2) x4 to x4099 multiplier Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 7 TMS320C5504 SPRS659 – JANUARY 2010 2.2 www.ti.com C55x CPU The TMS320C5504 fixed-point digital signal processor (DSP) is based on the C55x CPU 3.3 generation processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, three data read buses (one 32-bit data read bus and two 16-bit data read buses), two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four data reads and two data writes in a single cycle. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory, stores them in a 128-byte Instruction Buffer Queue, and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions calls. PRODUCT PREVIEW For more detailed information on the CPU, see the TMS320C55x CPU 3.0 CPU Reference Guide (literature number SWPU073). The C55x core of the C5504 can address 16M bytes of unified data and program space. It also addresses 64K words of I/O space. The C5504 includes three types of on-chip memory: 128 KB read-only memory (ROM), 192 KB single-access random access memory (SARAM), 64 KB dual-access random access memory (DARAM). The memory map is shown in Figure 2-1 . 8 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com 2.2.1 SPRS659 – JANUARY 2010 On-Chip Dual-Access RAM (DARAM) The DARAM is located in the byte address range 000000h − 00FFFFh and is composed of eight blocks of 4K words each (see Table 2-2). Each DARAM block can perform two accesses per cycle (two reads, two writes, or a read and a write). The DARAM can be accessed by the internal program, data, or DMA buses. (1) 2.2.2 CPU BYTE ADDRESS RANGE DMA CONTROLLER BYTE ADDRESS RANGE MEMORY BLOCK 000000h – 001FFFh 0001 0000h – 0001 1FFFh DARAM 0 (1) 002000h – 003FFFh 0001 2000h – 0001 3FFFh DARAM 1 004000h – 005FFFh 0001 4000h – 0001 5FFFh DARAM 2 006000h – 007FFFh 0001 6000h – 0001 7FFFh DARAM 3 008000h – 009FFFh 0001 8000h – 0001 9FFFh DARAM 4 00A000h – 00BFFFh 0001 A000h – 0001 BFFFh DARAM 5 00C000h – 00DFFFh 0001 C000h – 0001 DFFFh DARAM 6 00E000h – 00FFFFh 0001 E000h – 0001 FFFFh DARAM 7 The first 192 bytes are reserved for memory-mapped registers (MMRs). See Figure 2-1 , TMS320C5504 Memory Map Summary. On-Chip Single-Access RAM (SARAM) The SARAM is located at the byte address range 010000h – 03FFFF h and is composed of 24 blocks of 4K words each (see Table 2-3). Each SARAM block can perform one access per cycle (one read or one write). SARAM can be accessed by the internal program, data, or DMA buses. SARAM is also accessed by the USB DMA bus. Table 2-3. SARAM Blocks CPU BYTE ADDRESS RANGE DMA/USB CONTROLLER BYTE ADDRESS RANGE MEMORY BLOCK 010000h − 011FFFh 0009 0000h – 0009 1FFFh SARAM 0 012000h − 013FFFh 0009 2000h – 0009 3FFFh SARAM 1 014000h − 015FFFh 0009 4000h – 0009 5FFFh SARAM 2 016000h − 017FFFh 0009 6000h – 0009 7FFFh SARAM 3 018000h − 019FFFh 0009 8000h – 0009 9FFFh SARAM 4 01A000h − 01BFFFh 0009 A000h – 0009 BFFFh SARAM 5 01C000h − 01DFFFh 0009 C000h – 0009 DFFFh SARAM 6 01E000h − 01FFFFh 0009 E000h – 0009 FFFFh SARAM 7 020000h − 021FFFh 000A 0000h – 000A 1FFFh SARAM 8 022000h − 023FFFh 000A 2000h – 000A 3FFFh SARAM 9 024000h − 025FFFh 000A 4000h – 000A 5FFFh SARAM 10 026000h − 027FFFh 000A 6000h – 000A 7FFFh SARAM 11 028000h − 029FFFh 000A 8000h – 000A 9FFFh SARAM 12 02A000h − 02BFFFh 000A A000h – 000A BFFFh SARAM 13 02C000h − 02DFFFh 000A C000h – 000A DFFFh SARAM 14 02E000h − 02FFFFh 000A E000h – 000A FFFFh SARAM 15 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 9 PRODUCT PREVIEW Table 2-2. DARAM Blocks TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 2-3. SARAM Blocks (continued) 2.2.3 CPU BYTE ADDRESS RANGE DMA/USB CONTROLLER BYTE ADDRESS RANGE MEMORY BLOCK 030000h − 031FFFh 000B 0000h – 000B 1FFFh SARAM 16 032000h − 033FFFh 000B 2000h – 000B 3FFFh SARAM 17 034000h − 035FFFh 000B 4000h – 000B 5FFFh SARAM 18 036000h − 037FFFh 000B 6000h – 000B 7FFFh SARAM 19 038000h − 039FFFh 000B 8000h – 000B 9FFFh SARAM 20 03A000h − 03BFFFh 000B A000h – 000B BFFFh SARAM 21 03C000h − 03DFFFh 000B C000h – 000B DFFFh SARAM 22 03E000h − 03FFFFh 000B E000h – 000B FFFFh SARAM 23 040000h – 04FFFFh 000C 0000h – 000C FFFFh Reserved On-Chip Read-Only Memory (ROM) PRODUCT PREVIEW The zero-wait-state ROM is located at the byte address range FE0000h – FFFFFFh. The ROM is composed of four 16K-word blocks, for a total of 128K bytes of ROM. The ROM address space can be mapped by software to the external memory or to the internal ROM. The standard C5504 device includes a Bootloader program resident in the ROM. When the MPNMC bit field of the ST3 status register is cleared (by default), the byte address range FE0000h – FFFFFFh is reserved for the on-chip ROM. When the MPNMC bit field of the ST3 status register is set through software, the on-chip ROM is disabled and not present in the memory map, and byte address range FE0000h – FFFFFFh is directed to external memory space. A hardware reset always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the software reset instruction does not affect the MPNMC bit. The ROM can be accessed by the program and data buses. Each on-chip ROM block is a one cycle per word access memory. 2.2.4 External Memory The external memory space of the device is located at the byte address range 050000h – FFFFFFh. The external memory space is divided into five chip select spaces: one dedicated to SDRAM and mobile SDRAM (EMIF CS0 or CS[1:0] space), and the remainder (EMIF CS2 through CS5 space) dedicated to asynchronous devices including flash. Each chip select space has a corresponding chip select pin (called EMIF_CSx) that is activated during an access to the chip select space. The external memory interface (EMIF) provides the means for the DSP to access external memories and other devices including: mobile single data rate (SDR) synchronous dynamic RAM (SDRAM and mSDRAM), NOR Flash, NAND Flash, and asynchronous static RAM (SRAM). Before accessing external memory, you must configure the EMIF through its memory-mapped registers. The EMIF provides a configurable 16- or 8-bit data bus, an address bus width of up to 21-bits, and 5 dedicated chip selects, along with memory control signals. To maximize power savings, the I/O pin of the EMIF can be operated at an independent voltage from the rest of other I/O pins on the device. 10 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com 2.2.5 SPRS659 – JANUARY 2010 I/O Memory The C5504 DSP includes a 64K byte I/O space for the memory-mapped registers of the DSP peripherals and system registers used for idle control, status monitoring and system configuration. I/O space is separate from program/memory space and is accessed with separate instruction opcodes or via the DMA's. Table 2-4 lists the memory-mapped registers of the device. Note that not all addresses in the 64K byte I/O space are used; these addresses should be treated as RESERVED and not accessed by the CPU nor DMA. For the expanded tables of each peripheral, see Section 5, Peripheral Information and Electrical Specifications of this document. Some DMA controllers have access to the I/O-Space memory-mapped registers of the following peripherals registers: I2C, UART, I2S, MMC/SD, EMIF, and USB. Before accessing any peripheral memory-mapped register, make sure the peripheral being accessed is not held in reset via the Peripheral Reset Control Register (PRCR) and its internal clock is enabled via the Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2). WORD ADDRESS PERIPHERAL 0x0000 – 0x0004 Idle Control 0x0005 – 0x000D through 0x0803 – 0x0BFF Reserved 0x0C00 – 0x0C7F DMA0 0x0C80 – 0x0CFF Reserved 0x0D00 – 0x0D7F DMA1 0x0D80 – 0x0DFF Reserved 0x0E00 – 0x0E7F DMA2 0x0E80 – 0x0EFF Reserved 0x0F00 – 0x0F7F DMA3 0x0F80 – 0x0FFF Reserved 0x1000 – 0x10DD EMIF 0x10EE – 0x10FF through 0x1300 – 0x17FF Reserved 0x1800 – 0x181F Timer0 0x1820 – 0x183F Reserved 0x1840 – 0x185F Timer1 0x1860 – 0x187F Reserved 0x1880 – 0x189F Timer2 0x1900 – 0x197F RTC 0x1980 – 0x19FF Reserved 0x1A00 – 0x1A6C I2C 0x1A6D – 0x1AFF Reserved 0x1B00 – 0x1B1F UART 0x1B80 – 0x1BFF Reserved 0x1C00 – 0x1CFF System Control 0x1D00 – 0x1FFF through 0x2600 – 0x27FF Reserved 0x2800 – 0x2840 I2S0 0x2900 – 0x2940 I2S1 0x2A00 – 0x2A40 I2S2 0x2B00 – 0x2B40 I2S3 0x2C41 – 0x2FFF Reserved 0x3000 – 0x300F SPI PRODUCT PREVIEW Table 2-4. Peripheral I/O-Space Control Registers Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 11 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 2-4. Peripheral I/O-Space Control Registers (continued) WORD ADDRESS PERIPHERAL 0x3010 – 0x39FF Reserved 0x3A00 – 0x3A1F MMC/SD0 0x3A20 – 0x3AFF Reserved 0x3B00 – 0x3B1F MMC/SD1 0x3B2F – 0x6FFF Reserved 0x7000 – 0x70FF Analog Control Registers 0x7100 – 0x7FFF Reserved 0x8000 – 0xFFFF USB PRODUCT PREVIEW 12 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com 2.3 SPRS659 – JANUARY 2010 Memory Map Summary The C5504 provides 16M bytes of total memory space composed of on-chip RAM, on-chip ROM, and external memory space supporting a variety of memory types. The on-chip, dual-access RAM allows two accesses to a given block during the same cycle. The C5504 supports 8 blocks of 4K words of dual-access RAM. The on-chip, single-access RAM allows one access to a given block per cycle. The C5504 supports 24 blocks of 4K words of single-access RAM. The remainder of the memory map is divided into five external spaces, and on-chip ROM. Each external space has a chip select decode signal (called CS0, CS[2:5]) that indicates an access to the selected space. The external memory interface (EMIF) supports access to asynchronous memories such as SRAM, NAND, or NOR and Flash, and mobile single data rate (mSDR) and single data rate (SDR) SDRAM. The DSP memory is accessible by different master modules within the DSP, including the C55x CPU, the four DMA controllers, and USB (see Figure 2-1 ). DMA/USB BYTE ADDRESS(A) ADDRESS(A) 000000h 0001 0000h 0000C0h 0001 00C0h MEMORY BLOCKS MMR (Reserved) DARAM 010000h 0009 0000h 042000h 050000h 000C 2000h 0100 0000h (B) (D) C00000h E00000h F00000h FE0000h 200K Bytes Reserved 56K Bytes A. B. C. D. E. (C)(E) 8M Minus 264K Bytes SDRAM/mSDRAM 0200 0000h External-CS2 Space (C) External-CS3 Space (C) 2M Bytes Asynchronous External-CS4 Space (C) 1M Bytes Asynchronous External-CS5 Space (C) 1M Minus 128K Bytes Asynchronous 4M Bytes Asynchronous 0300 0000h 0400 0000h 0500 0000h 050E 0000h ROM (if MPNMC=0) FFFFFFh 64K Minus 192 Bytes SARAM External-CS0 Space 800000h BLOCK SIZE PRODUCT PREVIEW CPU BYTE External-CS5 Space (if MPNMC=1) (C) 128K Bytes Asynchronous (if MPNMC=1) 128K Bytes ROM (if MPNMC=0) 050F FFFFh Address shown represents the first byte address in each block. The first 192 bytes are reserved for memory-mapped registers (MMRs). Out of the four DMA controllers, only DMA controller 3 has access to the external memory space. The USB controller does not have access to DARAM. The CS0 space can be accessed by CS0 only or by CS0 and CS1. Figure 2-1. TMS320C5504 Memory Map Summary Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 13 TMS320C5504 SPRS659 – JANUARY 2010 2.4 www.ti.com Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using software programmable register settings. For more information on pin muxing, see Section 3.7, Multiplexed Pin Configurations of this document. 2.4.1 Pin Map (Bottom View) Figure 2-2 shows the bottom view of the package pin assignments. PRODUCT PREVIEW P EM_DQM1 DVDDEMIF DVDDIO SPI_CS0 SPI_CS2 SPI_RX GP[12] DVDDIO GP[15] GP[17] I2S2_FS/ GP[19]/ SPI_CS0 I2S2_DX/ GP[27]/ SPI_TX UART_CTS/ GP[29]/ I2S3_FS UART_TXD/ GP[31]/ I2S3_DX N EM_A[15]/ GP[21] EM_SDCKE SPI_CLK SPI_CS1 SPI_CS3 SPI_TX GP[13] GP[14] GP[16] I2S2_CLK/ GP[18]/ SPI_CLK I2S2_RX/ GP[20]/ SPI_RX UART_RTS/ GP[28]/ I2S3_CLK UART_RXD/ GP[30]/ I2S3_RX DVDDIO M EM_A[14] EM_D[5] EM_SDCLK EM_CS3 EMU1 TCK TDO XF TRST MMC0_D1/ I2S0_RX/ GP[3] MMC0_CMD/ I2S0_FS/ GP[1] MMC1_D1/ I2S1_RX/ GP[9] MMC1_CLK/ I2S1_CLK/ GP[6] MMC1_D0/ I2S1_DX/ GP[8] L EM_A[13] EM_A[10] EM_D[12] EM_D[4] CVDD EMU0 TDI TMS MMC0_D0/ I2S0_DX/ GP[2] MMC0_CLK/ I2S0_CLK/ GP[0] MMC0_D3/ GP[5] MMC0_D2/ GP[4] MMC1_D3/ GP[11] MMC1_CMD/ I2S1_FS/ GP[7] K EM_A[12]/ (CLE) EM_A[11]/ (ALE) EM_D[14] EM_D[13] EM_D[6] EM_WAIT3 DVDDIO VSS VSS CVDD VSS DVDDIO VSS MMC1_D2/ GP[10] J EM_A[8] EM_A[9] EM_A[20]/ GP[26] EM_D[15] DVDDEMIF CVDD VSS VSS VSS RSV1 RSV2 USB_VBUS USB_VDD1P3 USB_DM H EM_WE EM_A[7] EM_D[7] EM_WAIT5 DVDDEMIF VSS DVDDEMIF CVDD USB_ VSSA1P3 USB_ VDDA1P3 USB_ VSSA3P3 USB_ VDDA3P3 USB_VSS1P3 USB_DP G EM_WAIT4 EM_A[18]/ GP[24] EM_D[0] EM_A[19]/ GP[25] DVDDEMIF VSS VSS USB_VDDPLL USB_R1 F EM_A[6] EM_A[17]/ GP[23] EM_D[2] EM_D[9] DVDDEMIF CVDD DVDDIO DVDDRTC VSS VSS USB_VSSOSC USB_LDOO LDOI LDOI E EM_A[2] EM_A[16]/ GP[22] EM_D[8] EM_OE EM_D[1] DVDDEMIF INT1 WAKEUP VSS DSP_LDOO VSS VSS VSS VSS D EM_A[5] EM_A[3] EM_D[10] EM_D[3] EM_WAIT2 RESET VSS RTC_ CLKOUT VSSA_PLL RSV6 VSS DSP_ LDO_EN RSV16 RSV3 C EM_A[4] EM_A[1] EM_CS4 EM_D[11] EM_CS2 INT0 CLK_SEL CVDDRTC VSSRTC VDDA_PLL RSV9 RSV0 RSV5 RSV4 B EM_BA[1] EM_A[0] EM_CS0 EM_SDCAS EM_DQM0 EM_R/W SCL SDA RTC_XI VSSA_ANA RSV8 LDOI BG_CAP VSSA_ANA A EM_BA[0] DVDDEMIF EM_CS5 EM_CS1 DVDDEMIF EM_SDRAS CLKOUT CLKIN RTC_XO VDDA_ANA RSV7 ANA_LDOO VSS VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A. USB_VSSREF USB_VSSPLL USB_VDDOSC USB_M12XI USB_M12XO Shading denotes pins not supported on this device. To ensure proper device operation, these pins must be hooked up properly, see Table 2-17, Regulators and Power Management Terminal Functions. Figure 2-2. C5504 Pin Map(A) 14 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com 2.5 SPRS659 – JANUARY 2010 Terminal Functions The terminal functions tables (Table 2-5 through Table 2-20) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors or bus-holders, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device Configuration section of this data manual. For proper device operation, external pullup/pulldown resistors may be required on some pins. Section 3.8.1, Pullup/Pulldown Resistors discusses situations where external pullup/pulldown resistors are required. Table 2-5. Oscillator/PLL Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION CLKOUT A7 O/Z – DVDDIO BH The CLKOUT pin is enabled/disabled through the CLKOFF bit in the CPU ST3_55 register. When disabled, the CLKOUT pin is placed in high-impedance (Hi-Z). At reset the CLKOUT pin is enabled until the beginning of the boot sequence, when the on-chip Bootloader sets CLKOFF = 1 and the CLKOUT pin is disabled (Hi-Z). For more information on the ST3_55 register, see the TMS320C55x 3.0 CPU Reference Guide (literature number: SWPU073). Input clock. This signal is used to input an external clock when the 32-KHz on-chip oscillator is not used as the DSP clock (pin CLK_SEL = 1). For boot purposes, the CLKIN frequency is assumed to be either 11.2896, 12, or 12.288 MHz. The CLK_SEL pin (C7) selects between the 32-KHz crystal clock or CLKIN. CLKIN A8 I – DVDDIO BH When the CLK_SEL pin is low, this pin should be tied to ground (VSS). When CLK_SEL is high, this pin should be driven by an external clock source. If CLK_SEL is high, this pin is used as the reference clock for the clock generator and during bootup the bootloader bypasses the PLL and assumes the CLKIN frequency is one of the following frequencies: 11.2896-, 12-, or 12.288-MHz. With these frequencies in mind, the bootloader sets the SPI clock rates at 500 KHz and the I2C clock rate at 400 KHz. CLK_SEL C7 I – DVDDIO BH Clock input select. This pin selects between the 32-KHz crystal clock or CLKIN. 0 = 32-KHz on-chip oscillator drives the RTC timer and the DSP clock generator while CLKIN is ignored. 1 = CLKIN drives the DSP clock generator and the 32-KHz on-chip oscillator drives only the RTC timer. This pin is not allowed to change during device operation; it must be tied high or low at the board. (1) (2) (3) VDDA_PLL C10 PWR see Section 4.2, 1.3-V Analog PLL power supply for the system clock generator. ROC VSSA_PLL D9 GND see Section 4.2, Analog PLL ground for the system clock generator. ROC I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 15 PRODUCT PREVIEW DSP clock output signal. For debug purposes, the CLKOUT pin can be used to tap different clocks within the DSP clock generator. The SRC bits in the CLKOUT Control Source Register (CCSSR) can be used to specify the CLKOUT pin source. Additionally, the slew rate of the CLKOUT pin can be controlled by the Output Slew Rate Control Register (OSRCR) [0x1C16]. TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 2-6. Real-Time Clock (RTC) Terminal Functions SIGNAL NAME RTC_XO NO. A9 TYPE (1) I OTHER (2) (3) – CVDDRTC DESCRIPTION Real-time clock oscillator output. This pin operates at the RTC core voltage, CVDDRTC, and supports a 32.768-kHz crystal. If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to CVDDRTC and RTC_XO to ground (VSS). A voltage must still be applied to CVDDRTC (see Section 4.2, Recommended Operating Conditions). Note: When RTC oscillator is disabled, the RTC registers (I/O address range 1900h – 197Fh) are not accessible. RTC_XI B9 I – CVDDRTC Real-time clock oscillator input. If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to CVDDRTC and RTC_XO to ground (VSS). A voltage must still be applied to CVDDRTC (see Section 4.2, Recommended Operating Conditions). Note: When RTC oscillator is disabled, the RTC registers (I/O address range 1900h – 197Fh) are not accessible. PRODUCT PREVIEW RTC_CLKOUT D8 O/Z WAKEUP E8 I/O/Z (1) (2) (3) 16 – DVDDRTC – DVDDRTC Real-time clock output pin. This pin operates at DVDDRTC voltage. The RTC_CLKOUT pin is enabled/disabled through the RTCCLKOUTEN bit in the RTC Power Management Register (RTCPMGT). At reset, the RTC_CLKOUT pin is disabled (high-impedance [Hi-Z]). The pin is used to WAKEUP the CPU from idle instruction. This pin defaults to an input at reset, but can also be configured as an active-low open-drain output signal to wakeup an external device from an RTC alarm by setting the WU_DIR bit in the RTCPMGT [1930h]. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 2-7. RESET, Interrupts, and JTAG Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION RESET External Flag Output. XF is used for signaling other processors in multiprocessor configurations or XF can be used as a fast general-purpose output pin. XF RESET M8 O/Z D6 I – DVDDIO BH IPU DVDDIO BH XF is set high by the BSET XF instruction and XF is set low by the BCLR XF instruction or by writing to bit 13 of the ST1_55 register. At reset, the XF pin will be high. For more information on the ST1_55 register, see the TMS320C55x 3.0 CPU Reference Guide (literature number: SWPU073). Device reset. RESET causes the DSP to terminate execution and loads the program counter with the contents of the reset vector. When RESET is brought to a high level, the reset vector in ROM at FFFF00h forces the program execution to branch to the location of the on-chip ROM bootloader. RESET affects the various registers and status bits. The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register but will be forced ON when RESET is asserted. TMS TDO TDI TCK (1) (2) (3) L8 M7 I O/Z L7 M6 I I IPU DVDDIO BH IEEE standard 1149.1 test mode select. This serial control input is clocked into the TAP controller on the rising edge of TCK. If the emulation header is located greater than 6 inches from the device, TMS must be buffered. In this case, the input buffer for TMS needs a pullup resistor connected to DVDDIO to hold these signals at a known value when the emulator is not connected. A resistor value of 4.7 kΩ or greater is suggested. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register. – DVDDIO BH IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance (Hi-Z) state except when the scanning of data is in progress. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). If the emulation header is located greater than 6 inches from the device, TDO must be buffered. IPU DVDDIO BH IEEE standard 1149.1 test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. If the emulation header is located greater than 6 inches from the device, TDI must be buffered. In this case, the input buffer for TDI needs a pullup resistor connected to DVDDIO to hold this signal at a known value when the emulator is not connected. A resistor value of 4.7 kΩ or greater is suggested. The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register. IPU DVDDIO BH IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. If the emulation header is located greater than 6 inches from the device, TCK must be buffered. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 17 PRODUCT PREVIEW JTAG [For more detailed information on emulation header design guidelines, see the XDS560 Emulator Technical Reference (literature number: SPRU589).] TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 2-7. RESET, Interrupts, and JTAG Terminal Functions (continued) SIGNAL NAME TRST EMU1 PRODUCT PREVIEW EMU0 NO. M9 M5 L6 TYPE (1) I I/O/Z I/O/Z OTHER (2) (3) DESCRIPTION IPD DVDDIO BH IEEE standard 1149.1 reset signal for test and emulation logic. TRST, when high, allows the IEEE standard 1149.1 scan and emulation logic to take control of the operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. The C5504 will not operate properly if this reset pin is never asserted low. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). It is recommended that an external pulldown resistor be used in addition to the IPD -- especially if there is a long trace to an emulation header. IPU DVDDIO BH Emulator 1 pin. EMU1 is used as an interrupt to or from the emulator system and is defined as input/output by way of the emulation logic. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). An external pullup to DVDDIO is required to provide a signal rise time of less than 10 msec. A 4.7-kΩ resistor is suggested for most applications. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register. IPU DVDDIO BH Emulator 0 pin. When TRST is driven low and then high, the state of the EMU0 pin is latched and used to connect the JTAG pins (TCK, TMS, TDI, TDO) to either the IEEE1149.1 Boundary-Scan TAP (when the latched value of EMU0 = 0) or to the DSP Emulation TAP (when the latched value of EMU0 = 1). Once TRST is high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the emulation logic. An external pullup to DVDDIO is required to provide a signal rise time of less than 10 msec. A 4.7-kΩ resistor is suggested for most applications. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register. EXTERNAL INTERRRUPTS 18 INT1 E7 I IPU DVDDIO BH INT0 C6 I IPU DVDDIO BH External interrupt inputs (INT1 and INT0). These pins are maskable via their specific Interrupt Mask Register (IMR1, IMR0) and the interrupt mode bit. The pins can be polled and reset by their specific Interrupt Flag Register (IFR1, IFR0). The IPU resistor on these pins can be enabled or disabled via the PDINHIBR2 register. Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 2-8. External Memory Interface (EMIF) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION EMIF FUNCTIONAL PINS: ASYNC (NOR, SRAM, and NAND) EM_A[20]/GP[26] J3 I/O/Z IPD DVDDEMIF BH This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF external address pin 20. Mux control via the A20_MODE bit in the EBSR (see Figure 3-2). The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register. This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF external address pin 19. Mux control via the A19_MODE bit in the EBSR (see Figure 3-2). The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register. EM_A[19]/GP[25] G4 I/O/Z IPD DVDDEMIF BH EM_A[18]/GP[24] G2 I/O/Z IPD DVDDEMIF BH This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF external address pin 18. Mux control via the A18_MODE bit in the EBSR (see Figure 3-2). The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register. EM_A[17]/GP[23] F2 I/O/Z IPD DVDDEMIF BH This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF external address pin 17. Mux control via the A17_MODE bit in the EBSR (see Figure 3-2). The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register. EM_A[16]/GP[22] E2 I/O/Z IPD DVDDEMIF BH This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF external address pin 16. Mux control via the A16_MODE bit in the EBSR (see Figure 3-2). The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register. EM_A[15]/GP[21] N1 I/O/Z IPD DVDDEMIF BH This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF external address pin 15. Mux control via the A15_MODE bit in the EBSR (see Figure 3-2). The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register. EM_A[14] M1 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 14. EM_A[13] L1 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 13. EM_A[12]/(CLE) K1 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 12. When interfacing with NAND Flash, this pin also acts as Command Latch Enable (CLE). EM_A[11]/(ALE) K2 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 11. When interfacing with NAND Flash, this pin also acts as Address Latch Enable (ALE). EM_A[10] L2 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 10. EM_A[9] J2 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 9. EM_A[8] J1 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 8. EM_A[7] H2 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 7. EM_A[6] F1 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 6. EM_A[5] D1 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 5. EM_A[4] C1 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 4. EM_A[3] D2 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 3. (1) (2) (3) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 19 PRODUCT PREVIEW Note: When accessing 8-bit Asynchronous memory, pins EM_A[20:0] should be connected to memory address pins [22:2] and EM_BA[1:0] should be connected to memory addresss pins [1:0]. For 16-bit Asynchronous memory, pins EM_A[20:0] should be connected to memory address pins [20:1] and EM_BA[1] should be connected to memory addresss pin [0]. TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 2-8. External Memory Interface (EMIF) Terminal Functions (continued) SIGNAL PRODUCT PREVIEW 20 TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. EM_A[2] E1 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 2. EM_A[1] C2 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 1. EM_A[0] B2 I/O/Z DVDDEMIF BH This pin is the EMIF external address pin 0. I/O/Z DVDDEMIF BH EMIF 16-bit bi-directional bus. EM_D[15] J4 EM_D[14] K3 EM_D[13] K4 EM_D[12] L3 EM_D[11] C4 EM_D[10] D3 EM_D[9] F4 EM_D[8] E3 EM_D[7] H3 EM_D[6] K5 EM_D[5] M2 EM_D[4] L4 EM_D[3] D4 EM_D[2] F3 EM_D[1] E5 EM_D[0] G3 EM_CS5 A3 O/Z DVDDEMIF BH EMIF chip select 5 output for use with asynchronous memories (i.e., NOR flash, NAND flash, or SRAM). EM_CS4 C3 O/Z DVDDEMIF BH EMIF chip select 4 output for use with asynchronous memories (i.e., NOR flash, NAND flash, or SRAM). EM_CS3 M4 O/Z DVDDEMIF BH EMIF NAND chip select 3 output for use with asynchronous memories (i.e., NOR flash, NAND flash, or SRAM). EM_CS2 C5 O/Z DVDDEMIF BH EMIF NAND chip select 2 output for use with asynchronous memories (i.e., NOR flash, NAND flash, or SRAM). EM_WE H1 O/Z DVDDEMIF BH EMIF asynchronous memory write enable output EM_OE E4 O/Z DVDDEMIF BH EMIF asynchronous memory read enable output EM_R/W B6 O/Z DVDDEMIF BH EMIF asynchronous read/write output EM_DQM1 P1 O/Z DVDDEMIF BH EMIF asynchronous data write strobes and byte enables or EMIF SDRAM and mSDRAM data mask bits. EM_DQM0 B5 O/Z DVDDEMIF BH EM_BA[1] B1 O/Z DVDDEMIF BH EM_BA[0] A1 O/Z DVDDEMIF BH EM_WAIT5 H4 I DVDDEMIF BH EMIF wait state extension input 5 for EM_CS5 EM_WAIT4 G1 I DVDDEMIF BH EMIF wait state extension input 4 for EM_CS4 EM_WAIT3 K6 I DVDDEMIF BH EMIF wait state extension input 3 for EM_CS3 EMIF asynchronous bank address 16-bit wide memory: EM_BA[1] forms the device address[0] and BA[0] forms device address [23]. 8-bit wide memory: EM_BA[1] forms the device address[1] and BA[0] forms device address [0]. EMIF SDRAM and mSDRAM bank address. Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 2-8. External Memory Interface (EMIF) Terminal Functions (continued) SIGNAL NAME NO. EM_WAIT2 D5 TYPE (1) I OTHER (2) (3) DVDDEMIF BH DESCRIPTION EMIF wait state extension input 2 for EM_CS2 EMIF FUNCTIONAL PINS: SDRAM and mSDRAM ONLY A4 O/Z DVDDEMIF BH EMIF SDRAM/mSDRAM chip select 1 output EM_CS0 B3 O/Z DVDDEMIF BH EMIF SDRAM/mSDRAM chip select 0 output EM_SDCLK M3 O/Z DVDDEMIF BH EMIF SDRAM/mSDRAM clock EM_SDCKE N2 O/Z DVDDEMIF BH EMIF SDRAM/mSDRAM clock enable EM_SDRAS A6 O/Z DVDDEMIF BH EMIF SDRAM/mSDRAM row address strobe EM_SDCAS B4 O/Z DVDDEMIF BH EMIF SDRAM/mSDRAM column strobe PRODUCT PREVIEW EM_CS1 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 21 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 2-9. Inter-Integrated Circuit (I2C) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION I2C (1) (2) (3) SCL B7 I/O/Z DVDDIO BH SDA B8 I/O/Z DVDDIO BH This pin is the I2C clock output. Per the I2C standard, an external pullup is required on this pin. This pin is the I2C bidirectional data signal. Per the I2C standard, an external pullup is required on this pin. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Table 2-10. Inter-IC Sound (I2S0 – I2S3) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION Interface 0 (I2S0) PRODUCT PREVIEW MMC0_D0/ I2S0_DX/ GP[2] L9 I/O/Z IPD DVDDIO BH This pin is multiplexed between MMC0, I2S0, and GPIO. For I2S, it is I2S0 transmit data output I2S0_DX. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. MMC0_CLK/ I2S0_CLK/ GP[0] L10 I/O/Z IPD DVDDIO BH This pin is multiplexed between MMC0, I2S0, and GPIO. For I2S, it is I2S0 clock input/output I2S0_CLK. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. MMC0_D1/ I2S0_RX/ GP[3] M10 I/O/Z IPD DVDDIO BH This pin is multiplexed between MMC0, I2S0, and GPIO. For I2S, it is I2S0 receive data input I2S0_RX. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. MMC0_CMD/ I2S0_FS/ GP[1] M11 I/O/Z IPD DVDDIO BH This pin is multiplexed between MMC0, I2S0, and GPIO. For I2S, it is I2S0 frame synchronization input/output I2S0_FS. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between MMC1, I2S1 , and GPIO. For I2S, it is I2S1 transmit data output I2S1_DX. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between MMC1, I2S1 , and GPIO. For I2S, it is I2S1 clock input/output I2S1_CLK. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between MMC1, I2S1 , and GPIO. For I2S, it is I2S1 receive data input I2S1_RX. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. I/O/Z IPD DVDDIO BH This pin is multiplexed betweenn MMC1, I2S2 , and GPIO. For I2S, it is I2S1 frame synchronization input/output I2S1_FS. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. Interface 1 (I2S1) MMC1_D0/ I2S1_DX/ GP[8] MMC1_CLK/ I2S1_CLK/ GP[6] MMC1_D1/ I2S1_RX/ GP[9] MMC1_CMD/ I2S1_FS/ GP[7] (1) (2) (3) 22 M14 M13 M12 L14 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 2-10. Inter-IC Sound (I2S0 – I2S3) Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION Interface 2 (I2S2) I2S2_DX/ GP[27]/ SPI_TX I2S2_CLK/ GP[18]/ SPI_CLK P12 N10 I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S2, GPIO, and SPI. For I2S, it is I2S2 transmit data output I2S2_DX. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S2, GPIO, and SPI. For I2S, it is I2S2 clock input/output I2S2_CLK. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between I2S2, GPIO, and SPI. For I2S, it is I2S2 receive data input I2S2_RX. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I2S2_RX/ GP[20]/ SPI_RX N11 I/O/Z IPD DVDDIO BH I2S2_FS/ GP[19]/ SPI_CS0 P11 I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S2 and GPIO. For I2S, it is I2S2 frame synchronization input/output I2S2_FS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. UART_TXD/ GP[31]/ I2S3_DX P14 I/O/Z IPD DVDDIO BH UART_RTS/ GP[28]/ I2S3_CLK N12 I/O/Z IPD DVDDIO BH This pin is multiplexed between UART, GPIO, and I2S3. For I2S, it is I2S3 clock input/output I2S3_CLK. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. UART_RXD/ GP[30]/ I2S3_RX N13 I/O/Z IPD DVDDIO BH This pin is multiplexed between UART, GPIO, and I2S3. For I2S, it is I2S3 receive data input I2S3_RX. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. UART_CTS/ GP[29]/ I2S3_FS P13 I/O/Z IPD DVDDIO BH This pin is multiplexed between UART, GPIO, and I2S3. For I2S, it is I2S3 frame synchronization input/output I2S3_FS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 PRODUCT PREVIEW Interface 3 (I2S3) This pin is multiplexed between UART, GPIO, and I2S3. For I2S, it is I2S3 transmit data output I2S3_DX. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. 23 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 2-11. Serial Peripheral Interface (SPI) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION Serial Port Interface (SPI) PRODUCT PREVIEW (1) (2) (3) 24 SPI_CS0 P4 I/O/Z DVDDIO BH I2S2_FS/ GP[19]/ SPI_CS0 P11 I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S2, GPIO, and SPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI chip select SPI_CS0. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. SPI_CS1 N4 I/O/Z DVDDIO BH For SPI, this pin is SPI chip select SPI_CS1. SPI_CS2 P5 I/O/Z DVDDIO BH For SPI, this pin is SPI chip select SPI_CS2. SPI_CS3 N5 I/O/Z DVDDIO BH For SPI, this pin is SPI chip select SPI_CS3. SPI_CLK N3 O/Z DVDDIO BH For SPI, this pin is clock output SPI_CLK. I2S2_CLK/ GP[18]/ SPI_CLK N10 I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S2, GPIO, and SPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is clock output SPI_CLK. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. SPI_TX N6 I/O/Z DVDDIO BH For SPI, this pin is SPI transmit data output. I2S2_DX/ GP[27]/ SPI_TX P12 I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S2, GPIO, and SPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI transmit data output. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. SPI_RX P6 I/O/Z DVDDIO BH For SPI this pin is SPI receive data input. I2S2_RX/ GP[20]/ SPI_RX N11 I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S2, GPIO, and SPI. Mux control via the PPMODE bits in the EBSR. For SPI this pin is SPI receive data input. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. For SPI, this pin is SPI chip select SPI_CS0. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 2-12. UART Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION UART_RXD/ GP[30]/ I2S3_RX UART_TXD/ GP[31]/ I2S3_DX UART_CTS/ GP[29]/ I2S3_FS UART_RTS/ GP[28]/ I2S3_CLK (1) (2) (3) N13 P14 P13 N12 I/O/Z IPD DVDDIO BH I/O/Z IPD DVDDIO BH This pin is multiplexed between UART, GPIO, and I2S3. In UART mode, it is the transmit data output UART_TXD. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between UART, GPIO, and I2S3. In UART mode, it is the clear to send input UART_CTS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between UART, GPIO, and I2S3. In UART mode, it is the ready to send output UART_RTS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 25 PRODUCT PREVIEW UART This pin is multiplexed between UART, GPIO, and I2S3. When used by UART, it is the receive data input UART_RXD. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 2-13. USB2.0 Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION USB 2.0 12-MHz crystal oscillator input. USB_MXI G13 I USB_VDDOSC USB_MXO G14 O USB_VDDOSC When the USB peripheral is not used, USB_MXI should be connected to ground (VSS). 12-MHz crystal oscillator output. When the USB peripheral is not used, USB_MXO should be left unconnected. 3.3-V power supply for USB oscillator. PRODUCT PREVIEW USB_VDDOSC G12 S see Section 4.2, ROC USB_VSSOSC F11 S see Section 4.2, ROC Ground for USB oscillator. USB_VBUS J12 A I/O see Section 4.2, ROC USB power detect. 5-V input that signifies that VBUS is connected. When the USB peripheral is not used, the USB_VBUS signal should be connected to ground (VSS). USB_DP H14 A I/O USB_VDDA3P3 USB bi-directional Data Differential signal pair [positive/negative]. USB_DM J14 A I/O USB_VDDA3P3 When the USB peripheral is not used, the USB_DP and USB_DM signals should both be tied to ground (VSS). USB_R1 G9 A I/O USB_VDDA3P3 When the USB peripheral is not used, USB_VDDOSC should be connected to ground (VSS). External resistor connect. Reference current output. This must be connected via a 10-kΩ ±1% resistor to USB_VSSREF and be placed as close to the device as possible. When the USB peripheral is not used, the USB_R1 signal should be connected via a 10-kΩ resistor to USB_VSSREF. (1) (2) (3) 26 Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to USB_R1. When the USB peripheral is not used, the USB_VSSREF signal should be connected directly to ground (Vss). USB_VSSREF G10 GND see Section 4.2, ROC USB_VDDA3P3 H12 S see Section 4.2, ROC USB_VSSA3P3 H11 GND see Section 4.2, ROC USB_VDDA1P3 H10 S see Section 4.2, ROC USB_VSSA1P3 H9 GND see Section 4.2, ROC USB_VDD1P3 J13 S see Section 4.2, ROC USB_VSS1P3 H13 GND see Section 4.2, ROC Digital core ground for USB phy. USB_VDDPLL G8 S see Section 4.2, ROC 3.3 V USB Analog PLL power supply. When the USB peripheral is not used, the USB_VDDPLL signal should be connected to ground (VSS). Analog 3.3 V power supply for USB PHY. When the USB peripheral is not used, the USB_VDDA3P3 signal should be connected to ground (VSS). Analog ground for USB PHY. Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits] When the USB peripheral is not used, the USB_VDDA1P3 signal should be connected to ground (VSS). Analog ground for USB PHY [For high speed sensitive analog circuits]. 1.3-V digital core power supply for USB PHY. When the USB peripheral is not used, the USB_VDD1P3 signal should be connected to ground (VSS). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 2-13. USB2.0 Terminal Functions (continued) SIGNAL NO. USB_VSSPLL G11 TYPE (1) GND OTHER (2) (3) see Section 4.2, ROC DESCRIPTION USB Analog PLL ground. PRODUCT PREVIEW NAME Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 27 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 2-14. MMC1/SD Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION MMC/SD MMC1_CLK/ I2S1_CLK/ GP[6] PRODUCT PREVIEW (1) (2) (3) M13 O IPD DVDDIO BH This pin is multiplexed between MMC1, I2S1, and GPIO. For MMC/SD, this is the MMC1 data clock output MMC1_CLK. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between MMC1, I2S1, and GPIO. For MMC/SD, this is the MMC1 command I/O output MMC1_CMD. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. MMC1_CMD/ I2S1_FS/ GP[7] L14 O IPD DVDDIO BH MMC1_D3/ GP[11] L13 I/O/Z IPD DVDDIO BH MMC1_D2/ GP[10] K14 I/O/Z IPD DVDDIO BH MMC1_D1/ I2S1_RX/ GP[9] M12 I/O/Z IPD DVDDIO BH MMC1_D0/ I2S1_DX/ GP[8] M14 I/O/Z IPD DVDDIO BH The MMC1_D3 and MMC1_D2 pins are multiplexed between MMC1 and GPIO. The MMC1_D1 and MMC1_D0 pins are multiplexed between MMC1, I2S1, and GPIO. In MMC/SD mode, all these pins are the MMC1 nibble wide bi-directional data bus. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on these pins can be enabled or disabled via the PDINHIBR1 register. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Table 2-15. MMC0/SD Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION MMC/SD (1) (2) (3) 28 MMC0_CLK/ I2S0_CLK/ GP[0] L10 O IPD DVDDIO BH This pin is multiplexed between MMC0, I2S0, and GPIO. For MMC/SD, this is the MMC0 data clock output MMC0_CLK. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. MMC0_CMD/ I2S0_FS/ GP[1] M11 O IPD DVDDIO BH This pin is multiplexed between MMC0, I2S0, and GPIO. For MMC/SD, this is the MMC0 command I/O output MMC0_CMD. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. MMC0_D3/ GP[5] L11 I/O/Z IPD DVDDIO BH MMC0_D2/ GP[4] L12 I/O/Z IPD DVDDIO BH MMC0_D1/ I2S0_RX/ GP[3] M10 I/O/Z IPD DVDDIO BH MMC0_D0/ I2S0_DX/ GP[2] L9 I/O/Z IPD DVDDIO BH The MMC0_D3 and MMC0_D2 pins are multiplexed between MMC0 and GPIO. The MMC0_D1 and MMC0_D0 pins are multiplexed between MMC0, I2S0, and GPIO. In MMC/SD mode, these pins are the MMC0 nibble wide bi-directional data bus. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on these pins can be enabled or disabled via the PDINHIBR1 register. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 2-16. GPIO Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION General-Purpose Input/Output External Flag Output. XF is used for signalling other processors in multiprocessor configurations or XF can be used as a fast general-purpose output pin. MMC0_CLK/ I2S0_CLK/ GP[0] MMC0_CMD/ I2S0_FS/ GP[1] MMC0_D0/ I2S0_DX/ GP[2] MMC0_D1/ I2S0_RX/ GP[3] MMC0_D2/ GP[4] M11 L9 M10 L12 – DVDDIO BH I/O/Z IPD DVDDIO BH This pin is multiplexed between MMC0, I2S0, and GPIO. For GPIO, it is general-purpose input/output pin 0 (GP[0]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between MMC0, I2S0, and GPIO. For GPIO, it is general-purpose input/output pin 1 (GP[1]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between MMC0, I2S0, and GPIO. For GPIO, it is general-purpose input/output pin 2 (GP[2]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between MMC0, I2S0, and GPIO. For GPIO, it is general-purpose input/output pin 3 (GP[3]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between MMC0 and GPIO. For GPIO, it is general-purpose input/output pin 4 (GP[4]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between MMC0 and GPIO. For GPIO, it is general-purpose input/output pin 5 (GP[5]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. XF is set high by the BSET XF instruction and XF is set low by the BCLR XF instruction or by writing to bit 13 of the ST1_55 register. At reset, the XF pin will be high. For more information on the ST1_55 register, see the TMS320C55x 3.0 CPU Reference Guide (literature number: SWPU073). L11 I/O/Z IPD DVDDIO BH I2S1_CLK/ GP[6] M13 I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S1 and GPIO. For GPIO, it is general-purpose input/output pin 6 (GP[6]). Mux control via the SP1MODE bits in the EBSR. I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S1 and GPIO. For GPIO, it is general-purpose input/output pin 7 (GP[7]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S1 and GPIO. For GPIO, it is general-purpose input/output pin 8 (GP[8]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between I2S1 and GPIO. For GPIO, it is general-purpose input/output pin 9 (GP[9]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. I2S1_DX/ GP[8] (3) L10 O/Z MMC0_D3/ GP[5] I2S1_FS/ GP[7] (1) (2) M8 L14 M14 I2S1_RX/ GP[9] M12 I/O/Z IPD DVDDIO BH GP[10] K14 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 10 (GP[10]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. GP[11] L13 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 11 (GP[11]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. GP[12] P7 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 12 (GP[12]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 29 PRODUCT PREVIEW XF TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 2-16. GPIO Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) (3) DESCRIPTION PRODUCT PREVIEW NAME NO. GP[13] N7 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 13 (GP[13]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. GP[14] N8 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 14 (GP[14]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. GP[15] P9 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 15 (GP[15]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. GP[16] N9 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 16 (GP[16]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. GP[17] P10 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 17 (GP[17]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I2S2_CLK/ GP[18]/ SPI_CLK N10 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 18 (GP[18]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I2S2_FS/ GP[19]/ SPI_CS0 P11 I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S2 and GPIO. For GPIO, it is general-purpose input/output pin 19 (GP[19]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I2S2_RX/ GP[20]/ SPI_RX N11 I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S2, GPIOand SPI. For GPIO, it is general-purpose input/output pin 20 (GP[20]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. EM_A[15]/GP[21] N1 I/O/Z IPD DVDDEMIF BH This pin is multiplexed between EMIF and GPIO. For GPIO, it is general-purpose input/output pin 21 (GP[21]). Mux control via the A15_MODE bit in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register. EM_A[16]/GP[22] E2 I/O/Z IPD DVDDEMIF BH This pin is multiplexed between EMIF and GPIO. For GPIO, it is general-purpose input/output pin 22 (GP[22]). Mux control via the A16_MODE bit in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register. EM_A[17]/GP[23] F2 I/O/Z IPD DVDDEMIF BH This pin is multiplexed between EMIF and GPIO. For GPIO, it is general-purpose input/output pin 23 (GP[23]). Mux control via the A17_MODE bit in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register. EM_A[18]/GP[24] G2 I/O/Z IPD DVDDEMIF BH This pin is multiplexed between EMIF and GPIO. For GPIO, it is general-purpose input/output pin 24 (GP[24]). Mux control via the A18_MODE bit in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register. I/O/Z IPD DVDDEMIF BH This pin is multiplexed between EMIF and GPIO. For GPIO, it is general-purpose input/output pin 25 (GP[25]). Mux control via the A19_MODE bit in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register. I/O/Z IPD DVDDEMIF BH This pin is multiplexed between EMIF and GPIO. For GPIO, it is general-purpose input/output pin 26 (GP[26]). Mux control via the A20_MODE bit in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between I2S2, GPIO, and SPI. For GPIO, it is general-purpose input/output pin 27 (GP[27]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between UART, GPIO, and I2S3. For GPIO, it is general-purpose input/output pin 28 (GP[28]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. EM_A[19]/GP[25] EM_A[20]/GP[26] I2S2_DX/ GP[27]/ SPI_TX UART_RTS/ GP[28]/ I2S3_CLK 30 G4 J3 P12 N12 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 2-16. GPIO Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. UART_CTS/ GP[29]/ I2S3_FS P13 I/O/Z IPD DVDDIO BH This pin is multiplexed between UART, GPIO, and I2S3. For GPIO, it is general-purpose input/output pin 29 (GP[29]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. UART_RXD/ GP[30]/ I2S3_RX N13 I/O/Z IPD DVDDIO BH This pin is multiplexed between UART, GPIO, and I2S3. For GPIO, it is general-purpose input/output pin 30 (GP[30]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I/O/Z IPD DVDDIO BH This pin is multiplexed between UART, GPIO, and I2S3. For GPIO, it is general-purpose input/output pin 31 (GP[31]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. P14 PRODUCT PREVIEW UART_TXD/ GP[31]/ I2S3_DX Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 31 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 2-17. Regulators and Power Management Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION Regulators S DSP_LDO output. [Not supported on this device] For proper device operation, DSP_LDO output must be disabled by pulling the DSP_LDO_EN pin up to LDOI. When disabled, this pin is in high-impedance (Hi-Z) state and should be left unconnected. LDOI F14, F13, B12 S LDO inputs. The LDOI pins must be connected to the same power supply source with a voltage range of 1.8 V to 3.6 V. These pins supply power to the internal LDO, the bandgap reference generator circuits, and serve as the I/O supply for some input pins. DSP_LDO_EN D12 I USB_LDOO F12 S USB_LDO output. [Not supported on this device] For proper device operation, this pin must be left unconnected. S ANA_LDO output. This output provides a regulated 1.3 V output and up to TBD mA of current (see the ISD parameter in Section 4.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature). For proper device operation, this pin must be connected to an ~ 1.0 mF decoupling capacitor to VSS. For more detailed information, see Section 5.3.4, Power-Supply Decoupling. This LDO is intended to supply power to the VDDA_ANA and VDDA_PLL pins and not external devices. O Bandgap reference filter signal. For proper device operation, this pin needs to be bypassed with a 0.1 mF capacitor to analog ground (VSSA_ANA). This external capacitor provides filtering for stable reference voltages & currents generated by the bandgap circuit. The bandgap produces the references for use by the System PLL and POR circuits. DSP_LDOO E10 ANA_LDOO PRODUCT PREVIEW BG_CAP (1) (2) (3) 32 A12 B13 – LDOI DSP_LDO enable input. [Not supported on this device] For proper device operation, this pin must be tied to LDOI, via 2-kΩ resistor to disable the DSP_LDOO pin. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 2-18. Reserved and No Connects Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION Reserved C12 I RSV1 J10 PWR RSV2 J11 PWR (3) Reserved. For proper device operation, this pin must be tied directly to CVDD. Reserved. For proper device operation, this pin must be tied directly to CVDD. RSV3 D14 I – LDOI RSV4 C14 I – LDOI Reserved. For proper device operation, this pin must be tied directly to VSS. RSV5 C13 I – LDOI Reserved. For proper device operation, this pin must be tied directly to VSS. RSV6 D10 I/O VDDA_ANA Reserved. (Leave unconnected, do not connect to power or ground). RSV7 A11 I/O VDDA_ANA Reserved. (Leave unconnected, do not connect to power or ground). RSV8 B11 I/O VDDA_ANA Reserved. (Leave unconnected, do not connect to power or ground). RSV9 C11 I/O VDDA_ANA Reseverd. (Leave unconnected, do not connect to power or ground). I – LDOI RSV16 (1) (2) Reserved. For proper device operation, this pin must be tied directly to VSS. D13 Reserved. For proper device operation, this pin must be tied directly to VSS. Reserved. For proper device operation, this pin must be directly tied to either VSS or LDOI or tied via a 10-kΩ resistor to either VSS or LDOI. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Table 2-19. Supply Voltage Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION SUPPLY VOLTAGES F6 H8 CVDD J6 PWR 1.05-V Digital Core supply voltage ( 60 or 75 MHz) 1.3-V Digital Core supply voltage (100 or 120 MHz) PWR 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/O power supply for non-EMIF and non-RTC I/Os PWR 1.8-V, 2.5-V, 2.8-V, or 3.3-V EMIF I/O power supply K10 L5 F7 K7 DVDDIO K12 N14 P3 P8 A2 A5 E6 F5 DVDDEMIF G5 H5 H7 J5 P2 (1) (2) (3) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 33 PRODUCT PREVIEW RSV0 – LDOI TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 2-19. Supply Voltage Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) (3) DESCRIPTION NO. CVDDRTC C8 PWR 1.05-V thru 1.3-V RTC digital core and RTC oscillator power supply. DVDDRTC F8 PWR 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/O power supply for RTC_CLOCKOUT and WAKEUP pins. VDDA_PLL C10 PWR see Section 4.2, ROC 1.3-V Analog PLL power supply for the system clock generator. USB_VDDPLL G8 S see Section 4.2, ROC 3.3 V USB Analog PLL power supply. When the USB peripheral is not used, the USB_VDDPLL signal should be connected to ground (VSS). J13 S see Section 4.2, ROC 1.3-V digital core power supply for USB PHY. USB_VDD1P3 H10 S see Section 4.2, ROC Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits] USB_VDDA1P3 H12 S see Section 4.2, ROC Analog 3.3 V power supply for USB PHY. USB_VDDA3P3 G12 S see Section 4.2, ROC 3.3-V power supply for USB oscillator. USB_VDDOSC VDDA_ANA A10 PWR PRODUCT PREVIEW NAME 34 When the USB peripheral is not used, the USB_VDD1P3 signal should be connected to ground (VSS). When the USB peripheral is not used, the USB_VDDA1P3 signal should be connected to ground (VSS). When the USB peripheral is not used, the USB_VDDA3P3 signal should be connected to ground (VSS). When the USB peripheral is not used, USB_VDDOSC should be connected to ground (VSS). 1.3-V supply for power management Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 2-20. Ground Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION A13 A14 D7 D11 E9 E11 E12 E13 E14 F9 VSS F10 GND Ground pins G6 G7 H6 PRODUCT PREVIEW J7 J8 J9 K8 K9 K11 K13 VSS_RTC Ground pin for RTC digital core and RTC oscillator power supply. VSSA_PLL D9 GND USB_VSSPLL G11 GND see Section 4.2, ROC USB Analog PLL ground. USB_VSS1P3 H13 GND see Section 4.2, ROC Digital core ground for USB phy. USB_VSSA1P3 H9 GND see Section 4.2, ROC Analog ground for USB PHY [For high speed sensitive analog circuits]. USB_VSSA3P3 H11 GND see Section 4.2, ROC Analog ground for USB PHY. USB_VSSOSC F11 S see Section 4.2, ROC Ground for USB oscillator. GND see Section 4.2, ROC Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to USB_R1. When the USB peripheral is not used, the USB_VSSREF signal should be connected directly to ground (Vss). VSSA_ANA (3) GND see Section 4.2, ROC USB_VSSREF (1) (2) C9 G10 B10 B14 GND Analog PLL ground for the system clock generator. Ground pins for power management (POR & Bandgap circuits) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 35 TMS320C5504 SPRS659 – JANUARY 2010 2.6 2.6.1 www.ti.com Device Support Development Support TI offers an extensive line of development tools for the TMS320C55x DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE). The following products support development of TMS320C55x fixed-point DSP-based applications: Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE): Version 3.3 or later C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS™ Version 5.33 or later), which provides the basic run-time target software needed to support any DSP application. PRODUCT PREVIEW Hardware Development Tools: Extended Development System (XDS™) Emulator For a complete listing of development-support tools for the TMS320C55x DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. 36 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com 2.6.2 SPRS659 – JANUARY 2010 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g.,TMS320C5504AZCHA12). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications. TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. TMS Fully-qualified production device. TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZCH), and the temperature range (for example, "Blank" is the commercial temperature range). Figure 2-3 provides a legend for reading the complete device name for any DSP platform member. Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 37 PRODUCT PREVIEW Support tool development evolutionary flow: TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com TMS 320 C 5505 A ZCH A 12 PREFIX TMX = Experimental device TMS = Qualified device DEVICE MAXIMUM OPERATING FREQUENCY 10 = 60 MHz at 1.05 V, 100 MHZ at 1.3 V 12 = 75 MHz at 1.05 V, 120 MHZ at 1.3 V DEVICE FAMILY 320 = TMS320™ DSP family TEMPERATURE RANGE Blank = 0 ° C to 70° C, Commercial Temperature A = –40° C to 85° C, Industrial Temperature TECHNOLOGY C = Dual-supply CMOS DEVICE C55x™ DSP: 5505 5504 PACKAGE TYPE ZCH = 196-pin plastic BGA, with Pb-Free soldered balls [Green] SILICON REVISION Revision 2.0 Figure 2-3. TMS320C5504 Device Nomenclature PRODUCT PREVIEW 38 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 3 Device Configuration 3.1 System Registers The system registers are used to configure the device and monitor its status. Brief descriptions of the various system registers are shown in Table 3-1. Table 3-1. Idle Control, Status, and System Registers CPU WORD ADDRESS ACRONYM 0001h ICR Idle Control Register Idle Status Register Register Description 0002h ISTR 1C00h EBSR 1C02h PCGCR1 Peripheral Clock Gating Control Register 1 1C03h PCGCR2 Peripheral Clock Gating Control Register 2 1C04h PSRCR Peripheral Software Reset Counter Register 1C05h PRCR Peripheral Reset Control Register 1C14h TIAFR Timer Interrupt Aggregation Flag Register 1C16h ODSCR 1C17h PDINHIBR1 Pull-Down Inhibit Register 1 1C18h PDINHIBR2 Pull-Down Inhibit Register 2 1C19h PDINHIBR3 Pull-Down Inhibit Register 3 1C1Ah DMA0CESR1 DMA0 Channel Event Source Register 1 External Bus Selection Register COMMENTS see Section 3.6.1 of this document. 1C1Bh DMA0CESR2 DMA0 Channel Event Source Register 2 1C1Ch DMA1CESR1 DMA1 Channel Event Source Register 1 1C1Dh DMA1CESR2 DMA1 Channel Event Source Register 2 1C26h ECDR PRODUCT PREVIEW Output Drive Strength Control Register EMIF Clock Divider Register 1C28h RAMSLPMDCNTLR1 RAM Sleep Mode Control Register 1 1C2Eh RAMSLPMDCNTLR2 RAM Sleep Mode Control Register 2 1C30h DMAIFR DMA Interrupt Flag Register 1C31h DMAIER DMA Interrupt Enable Register 1C32h USBSCR USB System Control Register 1C33h ESCR EMIF System Control Register 1C36h DMA2CESR1 DMA2 Channel Event Source Register 1 1C37h DMA2CESR2 DMA2 Channel Event Source Register 2 1C38h DMA3CESR1 DMA3 Channel Event Source Register 1 1C39h DMA3CESR2 DMA3 Channel Event Source Register 2 1C3Ah CLKSTOP Peripheral Clock Stop Request/Acknowledge Register Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 39 TMS320C5504 SPRS659 – JANUARY 2010 3.2 www.ti.com Power Considerations The C5504 provides several means of managing power consumption. To • • • • • • • • • 3.2.1 minimize power consumption, the C5504 divides its circuits into nine main isolated supply domains: LDOI (ANA_LDO and Bandgap Power Supply) Analog POR and PLL (VDDA_ANA and VDDA_PLL) RTC Core (CVDD_RTC) Digital Core (CVDD) USB Core (USB_ VDD1P3 and USB_VDDA1P3) USB PHY and USB PLL (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL) EMIF I/O (DVDDEMIF) RTC I/O (DVDDRTC) Rest of the I/O (DVDDIO) LDO Configuration The C5504 includes one Low-Dropout Regulator (LDO) which can be used to regulate the power supplies of the analog PLL and . PRODUCT PREVIEW 3.2.1.1 LDO Input The LDOI pins (B12, F13, F14) provide the power to the internal ANA_LDO, the bandgap reference generator, and some I/O input pins, and can range from 1.8 V to 3.6 V. The Bandgap provides accurate voltage and current references to the LDO and PLL ; therefore, for proper device operation, power must always be applied to the LDOI pins even if the LDO output is not used. 3.2.1.2 LDO Outputs The ANA_LDOO pin (A12) is the output of the internal ANA_LDO and can provide regulated 1.3 V power of up to TBD mA. The ANA_LDOO is intended to be connected, on the board, to the VDDA_ANA and VDDA_PLL pins to provide power to the and System PLL, respectively. VDDA_ANA and VDDA_PLL may be powered by this LDO output or by an external power supply. Note: The DSP_LDO is not supported on this device, so the DSP_LDO_EN pin must be tied high to LDOI, which will disable the DSP_LDO (2-kΩ resistor is recommended to be used as a pullup to LDOI). When the DSP_LDO is disabled, the DSP_LDOO pin is in a high-impedance (Hi-Z) state and the DSP_LDOO pin should be left unconnected. The USB_LDO is not supported on this device, so the USB_LDO must be left disabled. USB_LDO is disabled at reset, so it does not require any action to disable the USB_LDO. When the USB_LDO is disabled, the USB_LDOO pin is in a high-impedance (Hi-Z) state and should be left unconnected. 40 Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com 3.3 SPRS659 – JANUARY 2010 Clock Considerations The system clock, which is used by the CPU and most of the DSP peripherals, is controlled by the system clock generator. The system clock generator features a software-programmable PLL multiplier and several dividers. The clock generator accepts an input reference clock from the CLKIN pin or the output clock of the 32.768-KHz real-time clock (RTC) oscillator. The selection of the input reference clock is based on the state of the CLK_SEL pin. The CLK_SEL pins is required to be statically tied high or low and cannot change dynamically after reset. In addition, the DSP requires a reference clock for USB applications. The USB reference clock is generated using a dedicated on-chip oscillator with a 12-MHz external crystal connected to the USB_MXI and USB_MXO pins. The RTC oscillator generates a clock when a 32.768-KHz crystal is connected to the RTC_XI and RTC_XO pins. The 32.768-KHz crystal can be disabled if CLKIN is used as the clock source for the DSP. However, when the RTC oscillator is disabled, the RTC peripheral will not operate and the RTC registers (I/O address range 1900h – 197Fh) will not be accessible. This includes the RTC power management register (RTCPMGT) which controls the RTCLKOUT and WAKEUP pins. To disable the RTC oscillator, connect the RTC_XI pin to CVDDRTC and the RTC_XO pin to ground. For more information on crystal specifications for the RTC oscillator and the USB oscillator, see Section 5.4, External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins. 3.3.1 Clock Configurations After Device Reset After reset, the on-chip Bootloader programs the system clock generator based on the input clock selected via the CLK_SEL pin. If CLK_SEL = 0, the Bootloader programs the system clock generator and sets the system clock to 12.288 MHz (multiply the 32.768-kHz RTC oscillator clock by 375). If CLK_SEL = 1, the Bootloader bypasses the system clock generator altogether and the system clock is driven by the CLKIN pin. In this case, the CLKIN frequency is expected to be 11.2896 MHz, 12.0 MHz, or 12.288 MHz. While the bootloader tries to boot from the USB , the clock generator will be programmed to output approximately 36 MHz. For more information on USB boot, contact your local sales representative. 3.3.1.1 Device Clock Frequency After the boot process is complete, the user is allowed to re-program the system clock generator to bring the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not). The user must adhere to various clock requirements when programming the system clock generator. For more information, see Section 5.5, Clock PLLs. Note: The on-chip Bootloader allows for DSP registers to be configured during the boot process. However, this feature must not be used to change the output frequency of the system clock generator during the boot process. Timer0 is also used by the bootloader to allow for 200 ms of BG_CAP settling time. The bootloader register modification feature must not modify the Timer0 registers. 3.3.1.2 Peripheral Clock State The clock and reset state of each of peripheral is controlled through a set of system registers. The peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable peripheral clocks. The peripheral software reset counter register (PSRCR) and the peripheral reset control register (PRCR) are used to assert and de-assert peripheral reset signals. At hardware reset, all of the peripheral clocks are off to conserve power. After hardware reset, the DSP boots via the bootloader code in ROM. During the boot process, the bootloader queries each peripheral to Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 41 PRODUCT PREVIEW The USB reference clock is not required if the USB peripheral is not being used. To completely disable the USB oscillator, connect the USB_MXI pin to ground (VSS) and leave the USB_MXO pin unconnected. The USB oscillator power pins (USB_VDDOSC and USB_VSSOSC) should also be connected to ground. TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com determine if it can boot from that peripheral. In other words, it reads each peripheral looking for a valid boot image file. At that time, the individual peripheral clocks will be enabled for the query and then disabled again when the bootloader is finished with the peripheral. By the time the bootloader releases control to the user code, all peripheral clocks will be off and all domains in the ICR, except the CPU domain, will be idled. 3.3.1.3 USB Oscillator Control The USB oscillator is controlled through the USB system control register (USBSCR). To enable the oscillator, the USBOSCDIS and USBOSCBIASDIS bits must be cleared to 0. The user must wait until the USB oscillator stabilizes before proceeding with the USB configuration. The USB oscillator stabilization time is typically 100 ms, with a 10 ms maximum (Note: the startup time is highly dependent on the ESR and capacitive load on the crystal). PRODUCT PREVIEW 42 Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com 3.4 SPRS659 – JANUARY 2010 Boot Sequence The boot sequence is a process by which the device's on-chip memory is loaded with program and data sections from an external image file (in flash memory, for example). The boot sequence also allows, optionally, for some of the device's internal registers to be programmed with predetermined values. The boot sequence is started automatically after each device reset. For more details on device reset, see Section 5.7, Reset. The C5504 Bootloader follows the following steps as shown in Figure 3-1 1. Immediately after reset, the CPU fetches the reset vector from 0xFFFF00. MP/MC is 0 by default, so 0xFFFF00 is mapped to internal ROM. The PLL is in bypass mode. 2. Set CLKOUT slew rate control to slow slew rate. 3. Idle all peripherals, MPORT and HWA. 4. If CLK_SEL = 0, the Bootloader powers up the PLL and sets its output frequency to 12.288 MHz (with a 375x multiplier using VP = 749, VS = 0, input divider disabled, output divide-by-8 enabled, and output divider enabled with VO = 0). If CLK_SEL = 1, the Bootloader keeps the PLL bypassed. 5. Apply manufacturing trim to the bandgap references. 6. Disable CLKOUT. 7. Test for NOR boot on all asynchronous CS spaces (EM_CS[2:5]) with 16-bit access: (a) Check the first 2 bytes read from boot signature. (b) If the boot signature is not valid, go to step 8. (c) Set Register Configuration, if present in boot image. (d) Attempt NOR boot, go to step 15. 8. Test for NAND boot on all asynchronous CS spaces (EM_CS[2:5]) with 8-bit access: (a) Check the first 2 bytes read from boot table for a boot signature match. (b) If the boot signature is not valid, go to step 9. (c) Set Register Configuration, if present in boot image. (d) Attempt NAND boot, go to step 15. 9. Test for 16-bit and 24-bit SPI EEPROM boot on SPI_CS[0] with 500-KHz clock rate and for Parallel Port Mode on External bus Selection Register set to 5, then set to 6: (a) Check the first 2 bytes read from boot table for a boot signature match using 16-bit address mode. (b) If the boot signature is not valid, read the first 2 bytes again using 24-bit address mode. (c) If the boot signature is not valid from either case (16-bit and 24-bit address modes), go to step 10. (d) Set Register Configuration, if present in boot image. (e) Attempt SPI Serial Memory boot, go to step 15. 10. Test for I2C EEPROM boot with a 7-bit slave address 0x50 and 400-kHz clock rate. (a) Check the first 2 bytes read from boot table for a boot signature match. (b) If the boot signature is not valid, go to step 11. (c) Set Register Configuration, if present in boot image. (d) Attempt I2C EEPROM boot, go to step 15. 11. Test for MMC/SD boot --- For more information on MMC/SD boot, contact your local sales representative. 12. Set the PLL output to approximately 36 MHz. If CLK_SEL = 1, CLKIN multiplied by 3x, ; if CLK_SEL = 0, CLKIN is multiplied by 1125x. 13. Test for USB boot --- For more information on USB boot, contact your local sales representative. Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 43 PRODUCT PREVIEW There are several methods by which the memory and register initialization can take place. Each of these methods is referred to as a boot mode. At reset, the device cycles through different boot modes until an image is found with a valid boot signature. The on-chip Bootloader allows the DSP registers to be configured during the boot process, if the optional register configuration section is present in the boot image (see Figure 3-1 ). For more information on the boot modes supported, see Section 3.4.1, Boot Modes. TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com 14. If the boot signature is not valid, then go back to step 14 and repeat. 15. Enable TIMER0 to start counting 200 ms. 16. Ensure a minimum of 200 ms has elapsed since step 15 before proceeding to execute the bootloaded code. 17. Jump to the entry point specified in the boot image. CLK SEL = 1 ? No Setup PLL to x375 Yes Internal Configuration NOR Boot ? Yes No PRODUCT PREVIEW NAND Boot ? Yes No SPI Boot ? Yes No Set Register Configuration I2C Boot ? No MMC/SD0 Boot (Not Supported) ? Yes Copy Boot Image Sections to System Memory Start Timer0 to Count 200 ms USB Boot (Not Supported) ? Has Timer0 Counter Expired ? No Yes Jump to Stored Execution Point Figure 3-1. Bootloader Software Architecture 3.4.1 Boot Modes The C5504 DSP supports the following boot modes in the following device order: NOR Flash, NAND Flash, SPI 16-bit EEPROM, SPI 24-bit Flash, I2C EEPROM, and MMC/SD card. The boot mode is determined by checking for a valid boot signature on each supported boot device. The first boot device with a valid boot signature will be used to load and execute the user code. If none of the supported boot devices have a valid boot signature, the Bootloader goes into an endless loop checking the USB boot mode and the device must be reset to look for another valid boot image in the supported boot modes. Note: For detailed information on MMC/SD and USB boot modes, contact your local sales representative. 44 Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com 3.4.2 SPRS659 – JANUARY 2010 Boot Configuration After reset, the on-chip Bootloader programs the system clock generator based on the input clock selected via the CLK_SEL pin. If CLK_SEL = 0, the Bootloader programs the system clock generator and sets the system clock to 12.288 MHz (multiply the 32.768-KHz RTC oscillator clock by 375). If CLK_SEL = 1, the Bootloader bypasses the system clock generator altogether and the system clock is driven by the CLKIN pin. Note: • When CLK_SEL =1, the CLKIN frequency is expected to be 11.2896 MHz, 12.0 MHz, or 12.288 MHz. • The on-chip Bootloader allows for DSP registers to be configured during the boot process. However, this feature must not be used to change the output frequency of the system clock generator during the boot process. Timer0 is also used by the bootloader to allow for 200 ms of BG_CAP settling time. The bootloader register modification feature must not modify the Timer0 registers. PRODUCT PREVIEW After hardware reset, the DSP boots via the bootloader code in ROM. During the boot process, the bootloader queries each peripheral to determine if it can boot from that peripheral. At that time, the individual peripheral clocks will be enabled for the query and then disabled when the bootloader is finished with the peripheral. By the time the bootloader releases control to the user code, all peripheral clocks will be "off" and all domains in the ICR, except the CPU domain, will be idled. Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 45 TMS320C5504 SPRS659 – JANUARY 2010 3.5 www.ti.com Configurations at Reset Some device configurations are determined at reset. The following subsections give more details. 3.5.1 Device and Peripheral Configurations at Device Reset Table 3-2 summarizes the device boot and configuration pins that are required to be statically tied high, tied low, or left unconnected during device operation. For proper device operation, a device reset should be initiated after changing any of these pin functions. Table 3-2. Default Functions Affected by Device Configuration Pins SIGNAL NO. IPU/IPD FUNCTIONAL DESCRIPTION DSP_LDO_EN D12 – DSP_LDO enable input. [Not supported on this device] For proper device operation, this pin must be tied to LDOI via a 2-kΩ resistor to disable the DSP_LDOO pin. CLK_SEL C7 – Clock input select. 0 = 32-KHz on-chip oscillator drives the RTC timer and the DSP clock generator. CLKIN is ignored. 1 = CLKIN drives the DSP clock generator and the 32-KHz on-chip oscillator drives only the RTC timer. PRODUCT PREVIEW CONFIGURATION PINS This pin is not allowed to change during device operation; it must be tied to DVDDIO or GND at the board. For proper device operation, external pullup/pulldown resistors may be required on these device configuration pins. For discussion on situations where external pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors. This device also has RESERVED pins that need to be configured correctly for proper device operation (statically tied high, tied low, or left unconnected at all times). For more details on these pins, see Table 2-18, Reserved and No Connects Terminal Functions. 3.6 Configurations After Reset The following sections provide details on configuring the device after reset. Multiplexed pin functions are selected by software after reset. For more details on multiplexed pin function control, see Section 3.7, Multiplexed Pin Configurations. 3.6.1 External Bus Selection Register (EBSR) The External Bus Selection Register (EBSR) determines the mapping of the I2S2, I2S3, UART, SPI, and GPIO signals to 21 signals of the external parallel port pins. It also determines the mapping of the I2S or MMC/SD ports to serial port 1 pins and serial port 2 pins. The EBSR register is located at port address 0x1C00. Once the bit fields of this register are changed, the routing of the signals takes place on the next CPU clock cycle. Additionally, the EBSR controls the function of the upper bits of the EMIF address bus. Pins EM_A[20:15] can be individually configured as GPIO pins through the Axx_MODE bits. When Axx_MODE = 1, the EM_A[xx] pin functions as a GPIO pin. When Axx_MODE = 0, the EM_A[xx] pin retains its EMIF functionality. 46 Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Before modifying the values of the external bus selection register, you must clock gate all affected peripherals through the Peripheral Clock Gating Control Register . After the external bus selection register has been modified, you must reset the peripherals before using them through the Peripheral Software Reset Counter Register. After the boot process is complete, the external bus selection register must be modified only once, during device configuration. Continuously switching the EBSR configuration is not supported. 15 14 12 Reserved 11 R-0 6 Reserved R-0 R-0 4 A20_MODE R/W-0 A19_MODE R/W-0 3 R/W-00 2 A18_MODE R/W-0 8 SP0MODE R/W-00 5 Reserved 9 SP1MODE R/W-000 7 10 PPMODE 1 A17_MODE A16_MODE R/W-0 R/W-0 0 A15_MODE R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 3-2. External Bus Selection Register (EBSR) [1C00h] Table 3-3. EBSR Register Bit Descriptions NAME 15 RESERVED DESCRIPTION Reserved. Read-only, writes have no effect. PPMODE Parallel Port Mode Control Bits. These bits control the pin multiplexing of the SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] pins on the parallel port. For more details, see , SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] Pin Multiplexing. 000 = Mode 0 001 = Mode 1 (SPI, GPIO, UART, and I2S2). 7 signals of the SPI module, 6 GPIO signals, 4 signals of the UART module and 4 signals of the I2S2 module are routed to the 21 external signals of the parallel port. 010 = Mode 2 (GPIO). 8 GPIO are routed to the 21 external signals of the parallel port. 011 = Mode 3 (SPI and I2S3). 4 signals of the SPI module and 4 signals of the I2S3 module are routed to the 21 external signals of the parallel port. 100 = Mode 4 (I2S2 and UART). 4 siignals of the I2S2 module and 4 signals of the UART module are routed to the 21 external signals of the parallel port. 101 = Mode 5 (SPI and UART). 4 signals of the SPI module and 4 signals of the UART module are routed to the 21 external signals of the parallel port. 110 = Mode 6 (SPI, I2S2, I2S3, and GPIO). 7 signals of the SPI module, 4 signals of the I2S2 module, 4 signals of the I2S3 module, and 6 GPIO are routed to the 21 external signals of the parallel port. 111 = Reserved. SP1MODE Serial Port 1 Mode Control Bits. The bits control the pin multiplexing of the I2S1 and GPIO pins on serial port 1. For more details, see Table 3-5, MMC1, I2S1 , and GP[11:6] Pin Multiplexing. 00 = Mode 0 ( ). . 01 = Mode 1 (I2S1 and GP[11:10]). 4 signals of the I2S1 module and 2 GP[11:10] signals are routed to the 6 external signals of the serial port 1. 10 = Mode 2 (GP[11:6]). 6 GPIO signals (GP[11:6]) are routed to the 6 external signals of the serial port 1. 11 = Reserved. 9:8 SP0MODE Serial Port 0 Mode Control Bits. The bits control the pin multiplexing of the MMC0, I2S0, and GPIO pins on serial port 0. For more details, see Section 3.7.1.3, MMC0, I2S0, and GP[5:0] Pin Multiplexing. 00 = Mode 0 (MMC/SD0). All 6 signals of the MMC/SD0 module are routed to the 6 external signals of the serial port 0. 01 = Mode 1 (I2S0 and GP[5:0]). 4 signals of the I2S0 module and 2 GP[5:4] signals are routed to the 6 external signals of the serial port 0. 10 = Mode 2 (GP[5:0]). 6 GPIO signals (GP[5:0]) are routed to the 6 external signals of the serial port 0. 11 = Reserved. 7 RESERVED Reserved. Read-only, writes have no effect. 6 RESERVED Reserved. Read-only, writes have no effect. 14:12 11:10 Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 47 PRODUCT PREVIEW BIT TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 3-3. EBSR Register Bit Descriptions (continued) BIT NAME 5 A20_MODE A20 Pin Mode Bit. This bit controls the pin mulitplexing of the EMIF address 20 (EM_A[20]) and general-purpose input/output pin 26 (GP[26]) pin functions. 0 = Pin function is EMIF address pin 20 (EM_A[20]). 1 = Pin function is general-purpose input/output pin 26 (GP[26]). 4 A19_MODE A19 Pin Mode Bit. This bit controls the pin mulitplexing of the EMIF address 19 (EM_A[19]) and general-purpose input/output pin 25 (GP[25]) pin functions. 0 = Pin function is EMIF address pin 19 (EM_A[19]). 1 = Pin function is general-purpose input/output pin 25 (GP[25]). 3 A18_MODE A18 Pin Mode Bit. This bit controls the pin mulitplexing of the EMIF address 18 (EM_A[18]) and general-purpose input/output pin 24 (GP[24]) pin functions. 0 = Pin function is EMIF address pin 18 (EM_A[18]). 1 = Pin function is general-purpose input/output pin 24 (GP[24]). A17_MODE A17 Pin Mode Bit. This bit controls the pin mulitplexing of the EMIF address 17 (EM_A[17]) and general-purpose input/output pin 23 (GP[23]) pin functions. For more details, see Table 3-6, EM_A[20:16] and GP[26:21] Pin Multiplexing. 0 = Pin function is EMIF address pin 17 (EM_A[17]). 1 = Pin function is general-purpose input/output pin 23 (GP[23]). A16_MODE A16 Pin Mode Bit. This bit controls the pin mulitplexing of the EMIF address 16 (EM_A[16]) and general-purpose input/output pin 22 (GP[22]) pin functions. For more details, see Table 3-6, EM_A[20:16] and GP[26:21] Pin Multiplexing. 0 = Pin function is EMIF address pin 16 (EM_A[16]). 1 = Pin function is general-purpose input/output pin 22 (GP[22]). A15_MODE A15 Pin Mode Bit. This bit controls the pin mulitplexing of the EMIF address 15 (EM_A[15]) and general-purpose input/output pin 21 (GP[21]) pin functions. For more details, see Table 3-6, EM_A[20:16] and GP[26:21] Pin Multiplexing. 0 = Pin function is EMIF address pin 15 (EM_A[15]). 1 = Pin function is general-purpose input/output pin 21 (GP[21]). 2 1 PRODUCT PREVIEW 0 3.6.2 DESCRIPTION EMIF and USB System Control Registers (ESCR and USBSCR) [1C33h and 1C32h] After reset, by default, the CPU performs 16-bit accesses to the EMIF and USB registers and data space. To perform 8-bit accesses to the EMIF data space, the user must set the BYTEMODE bits to 01b for the "high byte" or 10b for the "low byte" in the EMIF System Control Register (ESCR). Similarly, the BYTEMODE bits in the USB System Control Register (USBSCR) must also be configured for byte access. 3.6.3 Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h] After hardware reset, the DSP executes the on-chip bootloader from ROM. As the bootloader executes, it selectively enables the clock of the peripheral being queried for a valid boot. If a valid boot source is not found, the bootloader disables the clock to that peripheral and moves on to the next peripheral in the boot order. After the boot process is complete, all of the peripheral clocks will be off and all domains in the ICR, except for the CPU domain, will be idled (this includes the MPORT and HWA). The user must enable the clocks to the peripherals and CPU ports that are going to be used. The peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable the peripheral clocks. 3.6.4 Pullup/Pulldown Inhibit Registers (PDINHIBR1/2/3) [1C17h, 1C18h, and 1C19h, respectively] Each internal pullup and pulldown (IPU/IPD) resistor on the C5504 DSP, except for the IPD on TRST, can be individually controlled through the IPU/IPD registers (PDINHIBR1 [1C17h] , PDINHIBR2 [1C18h], and PDINHIBR3 [1C19h]). To minimize power consumption, internal pullup or pulldown resistors should be disabled in the presence of an external pullup or pulldown resistor or external driver. Section 3.8.1, Pullup/Pulldown Resistors, describes other situations in which an pullup and pulldown resistors are required. When CVDD is powered down, pullup and pulldown resistors will be forced disabled and an internal bus-holder will be enabled. For more detailed information, see Section 5.3.2, Digital I/O Behavior When Core Power (CVDD) is Down. 48 Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com 3.6.5 SPRS659 – JANUARY 2010 Output Slew Rate Control Register (OSRCR) [1C16h] PRODUCT PREVIEW To provide the lowest power consumption setting, the DSP has configurable slew rate control on the EMIF and CLKOUT output pins. The output slew rate control register (OSRCR) is used to set a subset of the device I/O pins, namely CLKOUT and EMIF pins, to either fast or slow slew rate. The slew rate feature is implemented by staging/delaying turn-on times of the parallel p-channel drive transistors and parallel n-channel drive transistors of the output buffer. In the slow slew rate configuration, the delay is longer, but ultimately the same number of parallel transistors are used to drive the output high or low. Thus, the drive strength is ultimately the same. The slower slew rate control can be used for power savings and has the greatest effect at lower DVDDIO voltages. Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 49 TMS320C5504 SPRS659 – JANUARY 2010 3.7 www.ti.com Multiplexed Pin Configurations The C5504 DSP uses pin multiplexing to accommodate a larger number of peripheral functions in the smallest possible package, providing the ultimate flexibility for end applications. The external bus selection register (EBSR) controls all the pin multiplexing functions on the device. 3.7.1 Pin Multiplexing Details This section discusses how to program the external bus selection register (EBSR) to select the desired peripheral functions and pin muxing. See the individual pin mux sections for pin muxing details for a specific muxed pin. After changing any of the pin mux control registers, it will be necessary to reset the peripherals that are affected. 3.7.1.1 SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] Pin Multiplexing [EBSR.PPMODE Bits] The SPI, UART, I2S2, I2S3, and GPIO signal muxing is determined by the value of the PPMODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see Table 3-4 . PRODUCT PREVIEW 50 Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 3-4. SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] Pin Multiplexing (1) (2) PIN NAME MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 001 010 011 100 101 110 SPI_CLK SPI_CLK – – – – SPI_CLK SPI_RX SPI_RX – – – – SPI_RX SPI_TX SPI_TX – – – – SPI_TX P2PD GP[12] GP[12] – – – – GP[12] P3PD GP[13] GP[13] – – – – GP[13] P4PD GP[14] GP[14] – – – – GP[14] P5PD GP[15] GP[15] – – – – GP[15] P6PD GP[16] GP[16] – – – – GP[16] P7PD GP[17] GP[17] – – – – GP[17] P8PD I2S2_CLK/GP[18]/SPI_CLK I2S2_CLK GP[18] SPI_CLK I2S2_CLK SPI_CLK I2S2_CLK P9PD I2S2_FS/GP[19]/SPI_CS0 I2S2_FS GP[19] SPI_CS0 I2S2_FS SPI_CS0 I2S2_FS P10PD I2S2_RX/GP[20]/SPI_RX I2S2_RX GP[20] SPI_RX I2S2_RX SPI_RX I2S2_RX P11PD I2S2_DX/GP[27]/SPI_TX I2S2_DX GP[27] SPI_TX I2S2_DX SPI_TX I2S2_DX P12PD UART_RTS/GP[28]/I2S3_CLK UART_RTS GP[28] I2S3_CLK UART_RTS UART_RTS I2S3_CLK P13PD UART_CTS/GP[29]/I2S3_FS UART_CTS GP[29] I2S3_FS UART_CTS UART_CTS I2S3_FS P14PD UART_RXD/GP[30]/I2S3_RX UART_RXD GP[30] I2S3_RX UART_RXD UART_RXD I2S3_RX P15PD UART_TXD/GP[31]/I2S3_DX UART_TXD GP[31] I2S3_DX UART_TXD UART_TXD I2S3_DX SPI_CS0 SPI_CS0 – – – – SPI_CS0 SPI_CS1 SPI_CS1 – – – – SPI_CS1 SPI_CS2 SPI_CS2 – – – – SPI_CS2 SPI_CS3 SPI_CS3 – – – – SPI_CS3 PRODUCT PREVIEW EBSR PPMODE BITS (2) PDINHIBR3 REGISTER BIT FIELDS (1) The pin names with PDINHIBR3 register bit field references can have the pulldown resistor enabled or disabled via this register. MODE 0 is the default mode at reset [PMODE bits in the EBSR register] and is not supported on the C5504 device. The PMODE bits must be configured to a valid mode (Mode 1 through Mode 6). Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 51 TMS320C5504 SPRS659 – JANUARY 2010 3.7.1.2 www.ti.com MMC1, I2S1, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits] The MMC1, I2S1 , and GPIO signal muxing is determined by the value of the SP1MODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see . Table 3-5. MMC1, I2S1, and GP[11:6] Pin Multiplexing EBSR SP1MODE BITS PDINHIBR1 REGISTER BIT FIELDS (1) (1) PIN NAME MODE 0 MODE 1 MODE 2 00 01 10 S10PD MMC1_CLK/I2S1_CLK/GP[6] MMC1_CLK I2S1_CLK GP[6] S11PD MMC1_CMD/I2S1_FS/GP[7] MMC1_CMD I2S1_FS GP[7] S12PD MMC1_D0/I2S1_DX/GP[8] MMC1_D0 I2S1_DX GP[8] S13PD MMC1_D1/I2S1_RX/GP[9] MMC1_D1 I2S1_RX GP[9] S14PD MMC1_D2/GP[10] MMC1_D2 GP[10] GP[10] S15PD MMC1_D3/GP[11] MMC1_D3 GP[11] GP[11] The pin names with PDINHIBR1 register bit field references can have the pulldown register enabled or disabled via this register. 3.7.1.3 MMC0, I2S0, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits] PRODUCT PREVIEW The MMC0, I2S0, and GPIO signal muxing is determined by the value of the SP0MODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see Table 3-6. Table 3-6. MMC0, I2S0, and GP[5:0] Pin Multiplexing EBSR SP0MODE BITS PDINHIBR1 REGISTER BIT FIELDS (1) (1) PIN NAME MODE 0 MODE 1 MODE 2 00 01 10 S00PD MMC0_CLK/I2S0_CLK/GP[0] MMC0_CLK I2S0_CLK GP[0] S01PD MMC0_CMD/I2S0_FS/GP[1] MMC0_CMD I2S0_FS GP[1] S02PD MMC0_D0/I2S0_DX/GP[2] MMC0_D0 I2S0_DX GP[2] S03PD MMC0_D1/I2S0_RX/GP[3] MMC0_D1 I2S0_RX GP[3] S04PD MMC0_D2/GP[4] MMC0_D2 GP[4] GP[4] S05PD MMC0_D3/GP[5] MMC0_D3 GP[5] GP[5] The pin names with PDINHIBR1 register bit field references can have the pulldown register enabled or disabled via this register. 3.7.1.4 EMIF EM_A[20:15] and GP[26:21] Pin Multiplexing [EBSR.Axx_MODE bits] The EMIF Address and GPIO signal muxing is determined by the value of the A20_MODE, A19_MODE, A18_MODE, A17_MODE, A16_MODE, and A15_MODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see Table 3-7. Table 3-7. EM_A[20:16] and GP[26:21] Pin Multiplexing PIN NAME Axx_MODE BIT 0 1 EM_A[15]/GP[21] EM_A[15] GP[21] EM_A[16]/GP[22] EM_A[16] GP[22] EM_A[17]/GP[23] EM_A[17] GP[23] EM_A[18]/GP[24] EM_A[18] GP[24] EM_A[19]/GP[25] EM_A[19] GP[25] EM_A[20]/GP[26] EM_A[20] GP[26] 52 Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com 3.8 3.8.1 SPRS659 – JANUARY 2010 Debugging Considerations Pullup/Pulldown Resistors Proper board design should ensure that input pins to the C5504 DSP always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The DSP features internal pullup (IPU) and internal pulldown (IPD) resistors on many pins, including all GPIO pins, to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors. For the configuration pins (listed in Table 3-2, Default Functions Affected by Device Configuration Pins), if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be implemented. In addition, applying external pullup/pulldown resistors on the configuration pins adds convenience to the user in debugging and flexibility in switching operating modes. When an external pullup or pulldown resistor is used on a pin, the pin’s internal pullup or pulldown resistor should be disabled through the Pullup/Pulldown Inhibit Registers (PDINHIBR1/2/3) [1C17h, 1C18h, and 1C19h, respectively] to minimize power consumption. Tips for choosing an external pullup/pulldown resistor: • Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown (IPU/IPD) resistors. • Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which, by definition, have margin to the VIL and VIH levels. • Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net. • For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin). • Remember to include tolerances when selecting the resistor value. • For pullup resistors, also remember to include tolerances on the DVDD rail. For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application. For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application. For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH) for the C5504 DSP, see Section 4.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature. Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 53 PRODUCT PREVIEW An external pullup/pulldown resistor may need to be used in the following situations: • Configuration Pins: An external pullup/pulldown resistor is recommended to set the desired value/state (see the configuration pins listed in Table 3-2, Default Functions Affected by Device Configuration Pins). Note that some configuration pins must connected directly to ground or to a specific supply voltage. • Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail. TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functions table in this document. 3.8.2 Bus Holders The C5504 has special I/O bus-holder structures to ensure pins are not left floating when CVDD power is removed while I/O power is applied. When CVDD is "ON", the bus-holders are disabled and the internal pullups or pulldowns, if applicable, function normally. But when CVDD is "OFF" and the I/O supply is "ON", the bus-holders become enabled and any applicable internal pullups and pulldowns are disabled. The bus-holders are weak drivers on the pin and, for as long as CVDD is "OFF" and I/O power is "ON", they hold the last state on the pin. If an external device is strongly driving C5504 I/O pin to the opposite state then the bus-holder will flip state to match the external driver and DC current will stop. This bus-holder feature prevents unnecessary power consumption when CVDD is "OFF"and I/O supply is "ON". For example, current caused by undriven pins (input buffer oscillation) and/or DC current flowing through pullups or pulldowns. PRODUCT PREVIEW If external pullup or pulldown resistors are implemented, then care should be taken that those pullup/pulldown resistors can exceed the internal bus-holder's max current and thereby cause the bus-holder to flip state to match the state of the external pullup or pulldown. Otherwise, DC current will flow unnecessarily. When CVDD power is applied, the bus holders are disabled (for further details on bus holders, see Section 5.3.2,Digital I/O Behavior When Core Power (CVDD) is Down.. 3.8.3 CLKOUT Pin For debug purposes, the DSP includes a CLKOUT pin which can be used to tap different clocks within the clock generator. The SRC bits of the CLKOUT Control Source Register (CCSSR) can be used to specify the source for the CLKOUT pin. Note: the bootloader disables the CLKOUT pin via CLKOFF bit in the ST3_55 CPU register. For more information on the ST3_55 CPU register, see the TMS320C55x 3.0 CPU Reference Guide (literature number: SWPU073). 54 Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 4 Device Operating Conditions For the device maximum operating frequency, see Section 2.6.2, Device and Development-Support Tool Nomenclature. Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) (1) Supply voltage ranges: Input and Output voltage ranges: Digital Core (CVDD, CVDDRTC, USB_VDD1P3) (2) –0.5 V to 1.7 V I/O, 1.8 V, 2.5 V, 2.8 V, 3.3 V (DVDDIO, DVDDEMIF, DVDDRTC) 3.3V USB supplies USB PHY (USB_VDDOSC, USB_VDDPLL, USB_VDDA3P3) (2) –0.5 V to 4.2 V LDOI –0.5 V to 4.2 V Analog, 1.3 V (VDDA_PLL, USB_VDDA1P3, VDDA_ANA) (2) –0.5 V to 1.7 V VI I/O, All pins with DVDDIO or DVDDEMIF or USB_VDDOSC or USB_VDDPLLor USB_VDDA3P3 as supply source –0.5 V to 4.2 V VO I/O, All pins with DVDDIO or DVDDEMIF or USB_VDDOSCor USB_VDDPLLor USB_VDDA3P3 as supply source –0.5 V to 4.2 V RTC_XI and RTC_XO –0.5 V to 1.7 V VO, BG_CAP –0.5 V to 1.7 V ANA_LDOO Operating case temperature ranges, Tc: (3) Commercial Temperature (default) Industrial Temperature –0.5 V to 1.7 V 0°C to 70°C -40°C to 85°C Storage temperature range, Tstg (default) Device Operating Life Power-On Hours (POH) Commercial Temperature 100, 000 POH Industrial Temperature 100, 000 POH (1) (2) (3) –65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS. On this device DSP_LDOO and USB_LDOO are not supported and should be left unconnected. Device Operating Conditions Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 55 PRODUCT PREVIEW 4.1 TMS320C5504 SPRS659 – JANUARY 2010 4.2 www.ti.com Recommended Operating Conditions Core Supplies PRODUCT PREVIEW VIH VIL (1) Tc 56 UNIT 1.15 V 1.24 1.3 1.43 V 0.998 1.05 1.43 V Supply voltage, RTC and RTC OSC USB_VDD1P3 Supply voltage, Digital USB 1.24 1.3 1.43 V USB_VDDA1P3 Supply voltage, 1.3 V Analog USB 1.24 1.3 1.43 V VDDA_ANA Supply voltage, 1.3 V Pwr Mgmt 1.24 1.3 1.43 V VDDA_PLL Supply voltage, 1.3 V System PLL 1.24 1.3 1.43 V USB_VDDPLL Supply voltage, 3.3 V USB PLL 2.97 3.3 3.63 V Supply voltage, I/O, 3.3 V 2.97 3.3 3.63 V Supply voltage, I/O, 2.8 V 2.52 2.8 3.08 V Supply voltage, I/O, 2.5 V 2.25 2.5 2.75 V Supply voltage, I/O, 1.8 V 1.65 1.8 1.98 V USB_VDDOSC Supply voltage, I/O, 3.3 V USB OSC 2.97 3.3 3.63 V USB_VDDA3P3 Supply voltage, I/O, 3.3 V Analog USB PHY 2.97 3.3 3.63 V LDOI Supply voltage, Analog Pwr Mgmt and LDO Input 3.6 V VSS Supply ground, Digital I/O VSSRTC Supply ground, RTC USB_VSSOSC Supply ground, USB OSC USB_VSSPLL Supply ground, USB PLL USB_VSSA3P3 Supply ground, 3.3 V Analog USB PHY USB_VSSA1P3 Supply ground, USB 1.3 V Analog USB PHY 0 V USB_VSSREF Supply ground, USB Reference Current VSSA_PLL Supply ground, System PLL USB_VSS1P3 Supply ground, 1.3 V Digital USB PHY VSSA_ANA Supply ground, Pwr Mgmt 0.7 * DVDD DVDD + 0.3 V -0.3 0.3 * DVDD V 0 70 °C 100 or 120 MHz 32.768 KHz High-level input voltage, 3.3, 2.8, 2.5, 1.8 V I/O Low-level input voltage, 3.3, 2.8, 2.5, 1.8 V I/O DSP Operating Frequency (SYSCLK1) 1.8 0 (2) (2) Default (Commercial) (Industrial) (1) (2) MAX 1.05 CVDDRTC Operating case temperature FSYSCLK1 NOM Supply voltage, Digital Core I/O Supplies (1) MIN 0.998 CVDD DVDDIO DVDDEMIF DVDDRTC GND 60 or 75 MHz 0 -40 85 1.05 V 0 60 or 75 MHz °C 1.3 V 0 100 or 120 MHz DVDD refers to the pin I/O supply voltage. To determine the I/O supply voltage for each pin, see Section 2.5 , Terminal Functions. The I2C pin SDA and SCL do not feature fail-safe I/O buffers. These pin could potentially draw current when the DVDDIO is powered down. Due to the fact that different voltage devices can be connected to I2C bus and the I2C inputs are LVCMOS, the level of logic 0 (low) and logic 1 (high) are not fixed and depend on DVDDIO. Device Operating Conditions Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) (1) PARAMETER VOH 360 440 IO = IOH 0.8 * DVDD High speed: USB_DN and USB_DP (3) –10 10 mV Low-level output voltage, 3.3, 2.8, 2.5, 1.8V I/O IO = IOL Low-level output voltage, I2C pins (4) VDD > 2 V, IO L = 3 mA 0 Input current [DC], ALL pins High-level output current [DC] mV mV DVDD = 1.8 V 122 mV TBD LDOI = VMIN -5 +5 mA mA -31 to -93 mA DVDD = 1.8 V with internal pullup enabled (8) -14 to -44 -5 mA +5 mA DVDD = 3.3 V with internal pulldown enabled (8) 52 to 158 mA DVDD = 2.5 V with internal pulldown enabled (8) 27 to 83 mA DVDD = 1.8 V with internal pulldown enabled (8) 11 to 35 mA VI = VSS to DVDD with internal pullups and pulldowns disabled. -5 All Pins (except EMIF, and CLKOUT pins) EMIF pins EMIF pins Bus Holder pull high current when CVDD is powered "OFF" +5 mA -4 mA DVDD = 3.3 V -6 mA DVDD = 1.8 V -5 mA DVDD = 3.3 V -6 mA DVDD = 1.8 V -4 mA +4 mA DVDD = 3.3 V +6 mA DVDD = 1.8 V +5 mA DVDD = 3.3 V +6 mA +4 mA DVDD = 1.8 V All Pins (except USB) IOHBH (8) (9) V mA DVDD = 2.5 V with internal pullup enabled (8) Bus Holder pull low current when CVDD is powered "OFF" (7) 1.43 -59 to -161 IOLBH (1) (2) (3) (4) (5) (6) 1.3 TBD DVDD = 3.3 V with internal pullup enabled (8) CLKOUT pin I/O Off-state output current V 141 All Pins (except USB, EMIF, and CLKOUT pins) (9) 0.4 162 CLKOUT pin Low-level output current [DC] V DVDD = 2.5 V Input only pin, internal pulldown or pullup disabled Input current [DC] (except WAKEUP, and I2C pins 0.2 * DVDD DVDD = 3.3 V Input only pin, internal pulldown or pullup disabled IOZ V V Input current [DC] (except WAKEUP, and I2C pins) IOL (7) mV 0.3 IILPU IOH (7) V 0.0 ANA_LDO shutdown current IIH/ IIL (7) UNIT Full speed: USB_DN and USB_DP (3) ANA_LDOO voltage (6) (7) MAX High speed: USB_DN and USB_DP (3) ISD IIHPD TYP USB_VDDA3P3 VLDO (6) (7) MIN 2.8 Input hysteresis (5) VHYS (2) Full speed: USB_DN and USB_DP (3) High-level output voltage, 3.3, 2.8, 2.5, 1.8 V I/O VOL TEST CONDITIONS -10 PRODUCT PREVIEW 4.3 SPRS659 – JANUARY 2010 +10 -TBD mA mA +TBD mA Shading denotes parameters not supported on this device. For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table. The USB I/Os adhere to the Universal Bus Specification Revision 2.0 (USB2.0 spec). VDD is the voltage to which the I2C bus pullup resistors are connected. Applies to all input pins except WAKEUP, I2C pins, and USB_MXI. II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II indicates the input leakage current and off-state (Hi-Z) output leakage current. When CVDD power is "ON", the pin bus-holders are disabled. For more detailed information, see Section 5.3.2 , Digital I/O Behavior When Core Power (CVDD) is Down) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current. Device Operating Conditions Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 57 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) (1) (continued) PARAMETER TEST CONDITIONS Core (CVDD) supply current ICDD PRODUCT PREVIEW Analog PLL (VDDA_PLL) supply current (2) MIN TYP MAX UNIT Active, CVDD = 1.3 V, DSP clock = 100 or 120 MHz Room Temp (25 °C), 75% DMAC + 25% ADD (typical sine wave data switching) 0.22 mW/MHz Active, CVDD = 1.05 V, DSP clock = 60 or 75 MHz Room Temp (25 °C) , 75% DMAC + 25% ADD (typical data switching) 0.15 mW/MHz Active, CVDD = 1.3 V, DSP clock = 100 of 120 MHz Room Temp (25 °C), 75% DMAC + 25% NOP (typical sine wave data switching) 0.22 mW/MHz Active, CVDD = 1.05 V, DSP clock = 60 or 75 MHz Room Temp (25 °C) , 75% DMAC + 25% NOP (typical data switching) 0.14 mW/MHz Standby, CVDD = 1.3 V, Master clock disabled, Room Temp (25 °C), DARAM and SARAM in active mode 0.44 mW Standby, CVDD = 1.05 V, Master clock disabled, Room Temp (25 °C), DARAM and SARAM in active mode 0.26 mW Standby, CVDD = 1.3 V, Master clock disabled, Room Temp (25 °C), DARAM in retention and SARAM in active mode 0.40 mW Standby, CVDD = 1.05 V, Master clock disabled, Room Temp (25 °C), DARAM in retention and SARAM in active mode 0.23 mW Standby, CVDD = 1.3 V, Master clock disabled, Room Temp (25 °C), DARAM in active mode and SARAM in retention 0.28 mW Standby, CVDD = 1.05 V, Master clock disabled, Room Temp (25 °C), DARAM in active mode and SARAM in retention 0.15 mW VDDA_PLL = 1.37 V Room Temp (25 °C), Phase detector = 170 kHz, VCO = 120 MHz 0.7 1.2 mA CI Input capacitance 4 pF Co Output capacitance 4 pF 5 Peripheral Information and Electrical Specifications 5.1 Parameter Information Tester Pin Electronics 42 Ω 3.5 nH Transmission Line Z0 = 50 Ω (see Note) 4.0 pF 1.85 pF Data Sheet Timing Reference Point Output Under Test Device Pin (see Note) NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 5-1. 3.3-V Test Load Circuit for AC Timing Measurements 58 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 5.1.1 1.8-V, 2.5-V, 2.8-V, and 3.3-V Signal Transition Levels All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 5-2. Rise and Fall Transition Time Voltage Reference Levels 5.1.2 3.3-V Signal Transition Rates All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns). Timing Parameters and Board Routing Analysis The timing parameter values specified in this data manual do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. 5.2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 5.3 Power Supplies The C5504 includes four core voltage-level supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3), and several I/O supplies (DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3), as well as several analog supplies (LDOI, VDDA_PLL, VDDA_ANA, and USB_VDDPLL). Some TI power-supply devices include features that facilitate power sequencing—for example, Auto-Track and Slow-Start/Enable features. For more information regarding TI's power management products and suggested devices to power TI DSPs, visit www.ti.com/processorpower. 5.3.1 Power-Supply Sequencing The C5504 includes four core voltage-level supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3), and several I/O supplies including—LDOI, DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3 The C5504 does not require a specific power-up sequence. The I/O design allows either the core supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3) or the I/O supplies (LDOI, DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3) to be powered up for an indefinite period of time while the other supply is not powered if the following constraints are met: 1. All maximum ratings and recommended operating conditions are satisfied. 2. All warnings about exposure to maximum rated and recommended conditions, particularly junction temperature are satisfied. These apply to power transitions as well as normal operation. 3. Bus contention while core supplies are powered must be limited to 100 hours over the projected lifetime of the device. Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 59 PRODUCT PREVIEW 5.1.3 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com 4. Bus contention while core supplies are powered down does not violate the absolute maximum ratings. If the USB subsystem is not used, the USB Core (USB_VDD1P3, USB_VDDA1P3) and USB PHY and I/O level supplies (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL) can be powered off. Note: If the device is powered up with the USB cable connected to an active USB host and the USB PHY (USB_VDDA3P3) is powered up before the USB Core (USB_VDD1P3,USB_VDDA1P3), the USB Core must be powered within 100 msec after the USB host detects the device has been attached. A supply bus is powered up when the voltage is within the recommended operating range. It is powered down when the voltage is below that range, either stable or while in transition. PRODUCT PREVIEW 60 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com 5.3.2 SPRS659 – JANUARY 2010 Digital I/O Behavior When Core Power (CVDD) is Down With some exceptions (listed below), all digital I/O pins on the C5504 have special features to allow powering down of the Digital Core Domain (CVDD) without causing I/O contentions or floating inputs at the pins (see Figure 5-3). The C5504 device asserts the internal signal called HHV high when power has been removed from the Digital Core Domain (CVDD). Asserting the internal HHV signal causes the following conditions to occur in any order: • All output pin strong drivers to go to the high-impedance (Hi-Z) state • Weak bus holders to be enabled to hold the pin at a valid high or low • The internal pullups or pulldowns (IPUs/IPDs) on the I/O pins will be disabled PRODUCT PREVIEW The exception pins that do not have this special feature are: • Pins driven by the CVDD_RTC Power Domain [This power domain is "Always On"; therefore, the pins driven by CVDD_RTC do not need these special features]: – RTC_XI, RTC_XO, RTC_CLKOUT, and WAKEUP • USB Pins: – USB_DP, USB_DM, USB_R1, USB_VBUS, USB_MXI, and USB_MXO • Pins for the Analog Block: – DSP_LDO_EN and BG_CAP DVDD Y PAD A GZ hhvgz HHV OR HHV PI OR hhvpi HHV Figure 5-3. Bus Holder I/O Circuit Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 61 TMS320C5504 SPRS659 – JANUARY 2010 5.3.3 www.ti.com Power-Supply Design Considerations Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C5504 device, the PC board should include separate power planes for core, I/O, VDDA_ANA and VDDA_PLL (which can share the same PCB power plane), and ground; all bypassed with high-quality low-ESL/ESR capacitors. 5.3.4 Power-Supply Decoupling In order to properly decouple the supply planes from system noise, place capacitors (caps) as close as possible to the C5504 . These caps need to be no more than 1.25 cm maximum distance from the C5504 power pins to be effective. Physically smaller caps, such as 0402, are better but need to be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 10 mF) should be furthest away, but still as close as possible. Large caps for each supply should be placed outside of the BGA footprint. PRODUCT PREVIEW As with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered. On the C5504 the recommended decoupling capacitance for the DSP core supplies should be 1 mF in parallel with 0.01-mF capacitor per supply pin. 5.3.5 LDO Input Decoupling The LDO inputs should follow the same decoupling guidelines as other power-supply pins above. 5.3.6 LDO Output Decoupling The LDO circuits implement a voltage feedback control system which has been designed to optimize gain and stability tradeoffs. As such, there are design assumptions for the amount of capacitance on the LDO output. For proper device operation, the following external decoupling capacitor should be used when the on-chip LDO is enabled: • ANA_LDOO– 1mF 5.4 External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins The C5504 DSP includes two options to provide an external clock input to the system clock generator: • Use the on-chip real-time clock (RTC) oscillator with an external 32.768-kHz crystal connected to the RTC_XI and RTC_XO pins. • Use an external 11.2896-, 12.0-, or 12.288-MHz LVCMOS clock input fed into the CLKIN pin that operates at the same voltage as the DVDDIO supply (1.8-, 2.5-, 2.8-, or 3.3-V). The CLK_SEL pin determines which input is used as the clock source for the system clock generator, For more details, see Section 3.5.1, Device and Peripheral Configurations at Device Reset. The crystal for the RTC oscillator is not required if CLKIN is used as the system reference clock; however, the RTC must still be powered. The RTC registers starting at I/O address 1900h will not be accessible without an RTC clock. This includes the RTC Power Management Register which provides control to WAKEUP and RTC_CLKOUT pins. Section 5.4.1, Real-Time Clock (RTC) On-Chip Oscillator With External Crystal provides more details on using the RTC on-chip oscillator with an external crystal. Section 5.4.2, CLKIN Pin With LVCMOS-Compatible Clock Input provides details on using an external LVCMOS-compatible clock input fed into the CLKIN pin. 62 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Additionally, the USB requires a reference clock generated using a dedicated on-chip oscillator with a 12-MHz external crystal connected to the USB_MXI and USB_MXO pins. The USB reference clock is not required if the USB peripheral is not being used. Section 5.4.3, USB On-Chip Oscillator With External Crystal provides details on using the USB on-chip oscillator with an external crystal. 5.4.1 Real-Time Clock (RTC) On-Chip Oscillator With External Crystal RTC_XI RTC_XO VSSRTC VSS CVDDRTC CVDD Crystal 32.768 kHz C1 C2 0.998-1.43 V 1.05/1.3 V Figure 5-4. 32.768-kHz RTC Oscillator The crystal should be in fundamental-mode function, and parallel resonant, with a maximum effective series resistance (ESR) specified in Table 5-1. The load capacitors, C1 and C2, are the total capacitance of the circuit board and components, excluding the IC and crystal. The load capacitors values are usually approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal manufacturer's datasheet and should be chosen such that the equation is satisfied. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (RTC_XI and RTC_XO) and to the VSSRTC pin. CL = C1 C2 (C1 + C2 ) Table 5-1. Input Requirements for Crystal on the 32.768-kHz RTC Oscillator PARAMETER MIN Start-up time (from power up until oscillating at stable frequency of 32.768-kHz) (1) Oscillation frequency (1) NOM 0.2 MAX UNIT 2 32.768 sec kHz ESR 100 Maximum shunt capacitance 1.6 kΩ pF Maximum crystal drive 1.0 mW The startup time is highly dependent on the ESR and the capacitive load of the crystal. Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 63 PRODUCT PREVIEW The on-chip oscillator requires an external 32.768-kHz crystal connected across the RTC_XI and RTC_XO pins, along with two load capacitors, as shown in Figure 5-4. The external crystal load capacitors must be connected only to the RTC oscillator ground pin (VSSRTC). Do not connect to board ground (VSS). Position the VSS lead on the board between RTC_XI and RTC_XO as a shield to reduce direct capacitance between RTC_XI and RTC_XO leads on the board. The CVDDRTC pin can be connected to the same power supply as CVDD , or may be connected to a different supply that meets the recommended operating conditions (see Section 4.2), if desired. TMS320C5504 SPRS659 – JANUARY 2010 5.4.2 www.ti.com CLKIN Pin With LVCMOS-Compatible Clock Input (Optional) Note: If CLKIN is not used, the pin must be tied low. A LVCMOS-compatible clock input of a frequency less than 24 MHz can be fed into the CLKIN pin for use by the DSP system clock generator. The external connections are shown in Figure 5-5 and Figure 5-6. The bootloader assumes that the CLKIN pin is connected to the LVCMOS-compatible clock source with a frequency of 11.2896-, 12.0-, or 12.288-MHz. These frequencies were selected to support boot mode peripheral speeds of 500 KHz for SPI and 400 KHz for I2C. These clock frequencies are achieved by dividing the CLKIN value by 25 for SPI and by 32 for I2C. If a faster external clock is input, then these boot modes will run at faster clock speeds. If the system design utilizes faster peripherals or these boot modes are not used, CLKIN values higher than 12.288 MHz can be used. Note: the CLKIN pin operates at the same voltage as the DVDDIO supply (1.8-, 2.5-, 2.8-, or 3.3-V). In this configuration the RTC oscillator can be optionally disabled by connecting RTC_XI to CVDDRTC and RTC_XO to ground (VSS). However, when the RTC oscillator is disabled the RTC registers starting at I/O address 1900h will not be accessible. This includes the RTC Power Management Register which provides control to WAKEUP and RTC_CLKOUT pins. Note: the RTC must still be powered even if the RTC oscillator is disabled. For more details on the RTC on-chip oscillator, see Section 5.4.1, Real-Time Clock (RTC) On-Chip Oscillator With External Crystal. PRODUCT PREVIEW CLKIN RTC_XI RTC_XO VSSRTC CVDDRTC VSS CVDD Crystal 32.768 kHz C1 C2 0.998-1.43 V 1.05/1.3 V Figure 5-5. LVCMOS-Compatible Clock Input With RTC Oscillator Enabled CLKIN RTC_XI CVDDRTC RTC_XO VSS VSSRTC 0.998-1.43 V CVDD 1.05/1.3 V Figure 5-6. LVCMOS-Compatible Clock Input With RTC Oscillator Disabled 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com 5.4.3 SPRS659 – JANUARY 2010 USB On-Chip Oscillator With External Crystal (Optional) When using the USB, the USB on-chip oscillator requires an external 12-MHz crystal connected across the USB_MXI and USB_MXO pins, along with two load capacitors, as shown in Figure 5-7. The external crystal load capacitors must be connected only to the USB oscillator ground pin (USB_VSSOSC). Do not connect to board ground (VSS). The USB_VDDOSC pin can be connected to the same power supply as USB_VDDA3P3. The USB on-chip oscillator can be permanently disabled, via tie-offs, if the USB peripheral is not being used. To permanently disable the USB oscillator, connect the USB_MXI pin to ground (VSS) and leave the USB_MXO pin unconnected. The USB oscillator power pins (USB_VDDOSC and USB_VSSOSC) should also be connected to ground. USB_MXI USB_MXO USB_VSSOSC USB_VDDOSC VSS USB_VDDA3P3 C1 C2 3.3 V PRODUCT PREVIEW Crystal 12 MHz 3.3 V Figure 5-7. 12-MHz USB Oscillator Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 65 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective series resistance (ESR) specified in Table 5-2. The load capacitors, C1 and C2 are the total capacitance of the circuit board and components, excluding the IC and crystal. The load capacitor value is usually approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal manufacturer's datasheet and should be chosen such that the equation below is satisfied. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (USB_MXI and USB_MXO) and to the USB_VSSOSC pin. CL = C1 C2 (C1 + C2 ) Table 5-2. Input Requirements for Crystal on the 12-MHz USB Oscillator PARAMETER MIN Start-up time (from power up until oscillating at stable frequency of 12 MHz) (1) Oscillation frequency NOM MAX 0.100 10 12 ms MHz ESR (2) Frequency stability Maximum shunt capacitance Maximum crystal drive PRODUCT PREVIEW (1) (2) UNIT 100 Ω ±100 ppm 5 pF 330 mW The startup time is highly dependent on the ESR and the capacitive load of the crystal. If the USB is used, a 12-MHz, ±100-ppm crystal is recommended. 5.5 Clock PLLs The C5504 DSP uses a software-programmable PLL to generate frequencies required by the CPU, DMA, and peripherals. The reference clock for the PLL is taken from either the CLKIN pin or the RTC on-chip oscillator (as specified through the CLK_SEL pin). 5.5.1 PLL Device-Specific Information There is a minimum and maximum operating frequency for CLKIN, PLLOUT, and the system clock (SYSCLK). The system clock generator must be configured not to exceed any of these constraints documented in this section (certain combinations of external clock inputs, internal dividers, and PLL multiply ratios are not supported). Table 5-3. PLLC1 Clock Frequency Ranges CLOCK SIGNAL NAME CVDD = 1.3 V MAX MIN MAX UNIT CLKIN (1) 11.2896 12 12.288 11.2896 12 12.288 MHz RTC Clock 32.768 32.768 KHz PLLIN 32.768 170 32.768 170 KHz PLLOUT 60 120 60 120 MHz SYSCLK 0.032768 60 or 75 0.032768 100 or 120 MHz PLL_LOCKTIME (1) 66 CVDD = 1.05 V MIN 4 4 ms These CLKIN values are used when the CLK_SEL pin = 1. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 The PLL has lock time requirements that must be followed. The PLL lock time is the amount of time needed for the PLL to complete its phase-locking sequence. 5.5.2 Clock PLL Considerations With External Clock Sources If the CLKIN pin is used to provide the reference clock to the PLL, to minimize the clock jitter a single clean power supply should power both the C5504 device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see Section 5.5.3, Clock PLL Electrical Data/Timing (Input and Output Clocks). Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the device requirements in this data manual (see Section 4.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature, and Section 5.5.3, Clock PLL Electrical Data/Timing (Input and Output Clocks). Clock PLL Electrical Data/Timing (Input and Output Clocks) Table 5-4. Timing Requirements for CLKIN (1) (2) (see Figure 5-8) CVDD = 1.05 V NO. MIN CVDD = 1.3 V NOM MAX MIN 88.577, 83.333, or 81.380 NOM MAX 88.577, 83.333, or 81.380 UNIT 1 tc(CLKIN) Cycle time, external clock driven on CLKIN 2 tw(CLKINH) Pulse width, CLKIN high 0.466 * tc(CLKIN) 0.466 * tc(CLKIN) ns 3 tw(CLKINL) Pulse width, CLKIN low 0.466 * tc(CLKIN) 0.466 * tc(CLKIN) ns 4 tt(CLKIN) Transition time, CLKIN (1) (2) 4 ns 4 ns The CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range for CPU operating frequency. The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 1 4 1 2 CLKIN 3 4 Figure 5-8. CLKIN Timing Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 67 PRODUCT PREVIEW 5.5.3 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 5-5. Switching Characteristics Over Recommended Operating Conditions for CLKOUT (1) (see Figure 5-9) NO . CVDD = 1.05 V PARAMETER (2) CVDD = 1.3 V MIN MAX MIN MAX P 16.67 or 13.33 (3) P 10 or 8.3 (3) UNIT 1 tc(CLKOUT) Cycle time, CLKOUT 2 tw(CLKOUTH) Pulse duration, CLKOUT high 0.466 * tc(CLKOUT) 0.466 * tc(CLKOUT) ns 3 tw(CLKOUTL) Pulse duration, CLKOUT low 0.466 * tc(CLKOUT) 0.466 * tc(CLKOUT) ns (4) 4 tt(CLKOUTR) Transition time (rise), CLKOUT 5 tt(CLKOUTF) Transition time (fall), CLKOUT (4) (1) (2) (3) (4) ns 5 5 ns 5 5 ns The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. P = 1/SYSCLK clock frequency in nanoseconds (ns). For example, when SYSCLK frequency is 100 MHz, use P = 10 ns. Value is maximum device frequency dependant (for more information, see Section 2.6.2 , Device and Development-Support Tool Nomenclature). Transition time is measured with the slew rate set to FAST and DVDDIO = 1.65 V. (For more detailed information, see the Section 3.6.5 , Output Slew Rate Control Register (OSRCR) [1C16h].). 2 5 1 PRODUCT PREVIEW CLKOUT 3 4 Figure 5-9. CLKOUT Timing 68 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com 5.6 SPRS659 – JANUARY 2010 Direct Memory Access (DMA) Controller The DMA controller is used to move data among internal memory, external memory, and peripherals without intervention from the CPU and in the background of CPU operation. The DSP includes a total of four DMA controllers. Aside from the DSP resources they can access, all four DMA controllers are identical. 5.6.1 DMA Channel Synchronization Events The DMA controllers allow activity in their channels to be synchronized to selected events. The DSP supports 20 separate synchronization events and each channel can be tied to separate sync events independent of the other channels. Synchronization events are selected by programming the CHnEVT field in the DMAn channel event source registers (DMAnCESR1 and DMAnCESR2). Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 69 PRODUCT PREVIEW The DMA controller has the following features: • Operation that is independent of the CPU. • Four channels, which allow the DMA controller to keep track of the context of four independent block transfers. • Event synchronization. DMA transfers in each channel can be made dependent on the occurrence of selected events. • An interrupt for each channel. Each channel can send an interrupt to the CPU on completion of the programmed transfer. • Ping-Pong mode allows the DMA controller to keep track of double buffering context without CPU intervention. • A dedicated clock idle domain. The four device DMA controllers can be put into a low-power state by independently turning off their input clocks. TMS320C5504 SPRS659 – JANUARY 2010 5.7 www.ti.com Reset The C5504 has two main types of reset: hardware reset and software reset. Hardware reset is responsible for initializing all key states of the device. It occurs whenever the RESET pin is asserted. There are two types of software reset: the CPU's software reset instruction and the software control of the peripheral reset signals. For more information on the CPU's software reset instruction, see the TMS320C55x CPU 3.0 CPU Reference Guide (literature number: SWPU073). In all C5504 documentation, all references to "reset" refer to hardware reset. Any references to software reset will explicitly state software reset. The C5504 RTC has one additional type of reset, a power-on-reset (POR) for the registers in the RTC core. This POR monitors the voltage of CVDD_RTC and resets the RTC registers when power is first applied to the RTC core. 5.7.0.1 RTC Power-On Reset (POR) The RTC POR ensures that the flip-flops in the CVDD_RTC power domain have an initial state upon powerup. In particular, the RTCNOPWR register is reset by this POR and is used to indicate that the RTC time registers need to be initialized with the current time and date when power is first applied. PRODUCT PREVIEW 5.7.0.2 Reset Pin (RESET) The C5504 can receive an external reset signal on the RESET pin. Once the hardware reset is applied, the DSP clock generator is enabled and the DSP starts the boot sequence. For more information on the boot sequence, see Section 3.4, Boot Sequence. 5.7.1 Pin Behaviors at Reset During normal operation, pins are controlled by the respective peripheral selected in the External Bus Selection Register (EBSR) register. During power-on reset and reset, the behavior of the output pins changes and is categorized as follows: • High Group: EM_CS4, EM_CS5, EM_CS2, EM_CS3, EM_DQM0, EM_DQM1, EM_OE, EM_WE, SPI_CS3, EM_SDCAS, EM_SDRAS, XF • Low Group: SPI_CLK, EM_R/W, MMC0_CLK/I2S0_CLK/GP[0], MMC1_CLK/I2S1_CLK/GP[6], EM_SDCLK • Z Group: EM_D[15:0], EMU[1:0], SCL, SDA, SPI_RX, SPI_TX, I2S2_RX/GP[20]/SPI_RX, I2S2_DX/GP[27]/SPI_TX, I2S2_RTS/GP[28]/I2S3_CLK, I2S2_CTS/GP[29]/I2S3_RS, I2S2_RXD/GP[30]/I2S3_RX, I2S2_TXD/GP[31]/I2S3_DX, GP[12], GP[13], GP[14], GP[15], GP[16], GP[17], I2S2_CLK/GP[18]/SPI_CLK,/I2S2_FS/GP[19]/SPI_CS0, RTC_CLKOUT, MMC0_CMD/I2S0_FS/GP[1], MMC0_D0/I2S0_DX/GP[2], MMC0_D1/I2S0_RX/GP[3], MMC0_D2/GP[4], MMC0_D3/GP[5], MMC1_CMD/I2S1_FS/GP[7], MMC1_D0/I2S1_DX/GP[8],MMC1_D1/I2S1_RX/GP[9],MMC1_D2/GP[10], MMC1_D3/GP[11], TDO, WAKEUP • CLKOUT Group: CLKOUT, SPI_CS1 • SYNCH 0→1 Group: SPI_CS0, SPI_CS2, SDCKE • SYNCH 1→0 Group: EM_CS0, EM_CS1 • SYNCH X→1 Group: EM_BA[1:0] • SYNCH X→0 Group: EM_A[20:0] 70 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com 5.7.2 SPRS659 – JANUARY 2010 Reset Electrical Data/Timing Table 5-6. Timing Requirements for Reset (1) (see Figure 5-10) CVDD = 1.05 V NO. 1 (1) MIN tw(RSTL) Pulse duration, RESET low MAX 3P CVDD = 1.3 V MIN MAX 3P UNIT ns (1)P = 1/SYSCLK clock frequency in ns. For example, if SYSCLK = 12 MHz, use P = 83.3 ns. In IDLE3 mode the system clock generator is bypassed and the SYSCLK frequency is equal to either CLKIN or the RTC clock frequency depending on CLK_SEL. RESET LOW Group PRODUCT PREVIEW HIGH Group Z Group SYNCH X ® 0 Group SYNCH X ® 1 Group SYNCH 0 ® 1 Group SYNCH 1 ® 0 Group CLKOUT 64k + 8 clocks if CLK_SEL = 1, 32 + 8 clocks if CLK_SEL = 0 Figure 5-10. Reset Timing Requirements Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 71 TMS320C5504 SPRS659 – JANUARY 2010 5.8 www.ti.com Interrupts and XF The C5504 device has a number of interrupts to service the needs of its peripherals. The interrupts can be selectively enabled or disabled. 5.8.1 Interrupts Electrical Data/Timing Table 5-7. Timing Requirements for Interrupts (1) (see Figure 5-11) CVDD = 1.05 V CVDD = 1.3 V NO. MIN (1) UNIT MAX 1 tw(INTH) Pulse duration, interrupt high CPU active 2P ns 2 tw(INTL) Pulse duration, interrupt low CPU active 2P ns P = 1/SYSCLK clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. For example, when running parts at 120 MHz, use P = 8.3 ns. 1 PRODUCT PREVIEW INTx 2 Figure 5-11. External Interrupt Timings 5.8.2 XF Electrical Data/Timing Table 5-8. Switching Characteristics Over Recommended Operating Conditions For XF (see Figure 5-12) NO. 1 CVDD = 1.05 V CVDD = 1.3 V PARAMETER td(XF) Delay time, CLKOUT high to XF high MIN MAX 0 10.2 UNIT ns (A) CLKOUT 1 XF A. CLKOUT reflects either the CPU clock, USB PHY, or PLL clock dependent on the setting of the CLOCKOUT Clock Source Register. For this diagram, CLKOUT refers to the CPU clock. Figure 5-12. XF Timings 72 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com 5.9 SPRS659 – JANUARY 2010 External Memory Interface (EMIF) C5504 supports several memories and external device interfaces, including: NOR Flash, NAND Flash, SRAM, Non-Mobile SDRAM, and Mobile SDRAM (mSDRAM). Note: The C5504 can support non-mobile SDRAM under certain circumstances. The C5504 always uses mobile SDRAM initialization but it is able to support SDRAM memories that ignore the BA0 and BA1 pins for the 'load mode register' command. During the mobile SDRAM initialization, the device issues the 'load mode register' initialization command to two different addresses that differ in only the BA0 and BA1 address bits. These registers are the Extended Mode register and the Mode register. The Extended mode register exists only in mSDRAM and not in non-mSDRAM. If a non-mobile SDRAM memory ignores bits BA0 and BA1, the second loaded register value overwrites the first, leaving the desired value in the Mode register and the non-mobile SDRAM will work with device. The EM_A[20:15] address signals are multiplexed with the GPIO peripheral and controlled by the External Bus Selection Register (EBSR). For more detail on the pin muxing, see the Section 3.6.1, External Bus Selection Register (EBSR). 5.9.1 EMIF Asynchronous Memory Support The EMIF supports asynchronous: • SRAM memories • NAND Flash memories • NOR Flash memories The EMIF data bus can be configured for both 8- or 16-bit width. The device supports up to 21 address lines and four external wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIF (EM_CS[5:2]). Each chip select has the following individually programmable attributes: • Data bus width • Read cycle timings: setup, hold, strobe • Write cycle timings: setup, hold, strobe • Bus turn around time • Extended Wait Option With Programmable Timeout • Select Strobe Option • NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes 5.9.2 EMIF Mobile Synchronous DRAM Memory Supported The EMIF supports 16-bit non-mobile and mobile single data rate (SDR) SDRAM in addition to the asynchronous memories listed in Section 5.9.1, EMIF Asynchronous Memory Support. The supported SDRAM and mobile SDRAM configurations are: • One, two, and four bank SDRAM/mSDRAM devices • Supports devices with eight, nine, ten, and eleven column addresses • CAS latency of two or three clock cycles • 16-bit data-bus width • 3.3/2.8/2.5/1.8 -V LVCMOS interface that is separate from the rest of the chip I/Os. • One (EMA_CS0) or two (EMA_CS[1:0]) chip selects Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 73 PRODUCT PREVIEW The EMIF provides an 8-bit or 16-bit data bus, an address bus width up to 21 bits, and 6 chip selects, along with memory control signals. TMS320C5504 SPRS659 – JANUARY 2010 • • • • • • • • • • www.ti.com 256-, 512-, 1024-, and 2048- word page sizes Burst lengths of 4 or 8 Sequential burst type. Interleave burst type not supported. Auto initialization from reset Partial Array Self Refresh and Temperature Controlled Self Refresh modes Temperature Controlled Self Refresh is only supported for mobile SDRAM having on-chip temperature sensor Prioritized refresh Programmable refresh rate and backlog counter Programmable timing parameters Auto Precharge not supported for better Bank Interleaving performance PRODUCT PREVIEW Additionally, the SDRAM/mSDRAM interface of EMIF supports placing the SDRAM/mSDRAM in "Self-Refresh" and "Powerdown Modes". Self-Refresh mode allows the SDRAM/mSDRAM to be put into a low-power state while still retaining memory contents; since the SDRAM/mSDRAM will continue to refresh itself even without clocks from the DSP. Powerdown mode achieves even lower power, except the DSP must periodically wake the SDRAM/mSDRAM up and issue refreshes if data retention is required. To achieve the lowest power consumption, the SDRAM/mSDRAM interface has configurable slew rate on the EMIF pins. 5.9.3 EMIF Peripheral Register Description(s) Table 5-9 shows the EMIF registers. Table 5-9. External Memory Interface (EMIF) Peripheral Registers (1) HEX ADDRESS RANGE (1) 74 ACRONYM REGISTER NAME 1000h REV 1001h STATUS Revision Register Status Register 1004h AWCCR1 Asynchronous Wait Cycle Configuration Register 1 1005h AWCCR2 Asynchronous Wait Cycle Configuration Register 2 1008h SDCR1 SDRAM/mSDRAM Configuration Register 1 1009h SDCR2 SDRAM/mSDRAM Configuration Register 2 100Ch SDRCR SDRAM/mSDRAM Refresh Control Register 1010h ACS2CR1 Asynchronous CS2 Configuration Register 1 1011h ACS2CR2 Asynchronous CS2 Configuration Register 2 1014h ACS3CR1 Asynchronous CS3 Configuration Register 1 1015h ACS3CR2 Asynchronous CS3 Configuration Register 2 1018h ACS4CR1 Asynchronous CS4 Configuration Register 1 1019h ACS4CR2 Asynchronous CS4 Configuration Register 2 101Ch ACS5CR1 Asynchronous CS5 Configuration Register 1 101Dh ACS5CR2 Asynchronous CS5 Configuration Register 2 1020h SDTIMR1 SDRAM/mSDRAM Timing Register 1 1021h SDTIMR2 SDRAM/mSDRAM Timing Register 2 103Ch SDSRETR SDRAM/mSDRAM Self Refresh Exit Timing Register 1040h EIRR EMIF Interrupt Raw Register 1044h EIMR EMIF Interrupt Mask Register 1048h EIMSR EMIF Interrupt Mask Set Register 104Ch EIMCR EMIF Interrupt Mask Clear Register Before reading or writing to the EMIF registers, be sure to set the BYTEMODE bits to 00b in the EMIF system control register to enable word accesses to the EMIF registers. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 5-9. External Memory Interface (EMIF) Peripheral Registers ACRONYM REGISTER NAME 1060h NANDFCR NAND Flash Control Register 1064h NANDFSR1 NAND Flash Status Register 1 1065h NANDFSR2 NAND Flash Status Register 2 1068h PGMODECTRL1 Page Mode Control Register 1 1069h PGMODECTRL2 Page Mode Control Register 2 1070h NCS2ECC1 NAND Flash CS2 1-Bit ECC Register 1 1071h NCS2ECC2 NAND Flash CS2 1-Bit ECC Register 2 1074h NCS3ECC1 NAND Flash CS3 1-Bit ECC Register 1 1075h NCS3ECC2 NAND Flash CS3 1-Bit ECC Register 2 1078h NCS4ECC1 NAND Flash CS4 1-Bit ECC Register 1 1079h NCS4ECC2 NAND Flash CS4 1-Bit ECC Register 2 107Ch NCS5ECC1 NAND Flash CS5 1-Bit ECC Register 1 107Dh NCS5ECC2 NAND Flash CS5 1-Bit ECC Register 2 10BCh NAND4BITECCLOAD NAND Flash 4-Bit ECC Load Register 10C0h NAND4BITECC1 NAND Flash 4-Bit ECC Register 1 10C1h NAND4BITECC2 NAND Flash 4-Bit ECC Register 2 10C4h NAND4BITECC3 NAND Flash 4-Bit ECC Register 3 10C5h NAND4BITECC4 NAND Flash 4-Bit ECC Register 4 10C8h NAND4BITECC5 NAND Flash 4-Bit ECC Register 5 10C9h NAND4BITECC6 NAND Flash 4-Bit ECC Register 6 10CCh NAND4BITECC7 NAND Flash 4-Bit ECC Register 7 10CDh NAND4BITECC8 NAND Flash 4-Bit ECC Register 8 10D0h NANDERRADD1 NAND Flash 4-Bit ECC Error Address Register 1 10D1h NANDERRADD2 NAND Flash 4-Bit ECC Error Address Register 2 10D4h NANDERRADD3 NAND Flash 4-Bit ECC Error Address Register 3 10D5h NANDERRADD4 NAND Flash 4-Bit ECC Error Address Register 4 10D8h NANDERRVAL1 NAND Flash 4-Bit ECC Error Value Register 1 10D9h NANDERRVAL2 NAND Flash 4-Bit ECC Error Value Register 2 10DCh NANDERRVAL3 NAND Flash 4-Bit ECC Error Value Register 3 10DDh NANDERRVAL4 NAND Flash 4-Bit ECC Error Value Register 4 Copyright © 2010, Texas Instruments Incorporated (continued) Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 PRODUCT PREVIEW HEX ADDRESS RANGE (1) 75 TMS320C5504 SPRS659 – JANUARY 2010 5.9.4 www.ti.com EMIF Electrical Data/Timing CVDD = 1.05 V, DVDDEMIF = 3.3/2.8/2.5/1.8 V Table 5-10. Timing Requirements for EMIF SDRAM/mSDRAM Interface (see Figure 5-13 and Figure 5-14) CVDD = 1.05 V CVDD = 1.05 V DVDDEMIF = 3.3/2.8/2.5 V DVDDEMIF = 1.8 V UNIT MIN MAX MIN MAX NO. 19 tsu(DV-CLKH) Input setup time, read data valid on EM_D[15:0] before EM_SDCLK rising 20 th(CLKH-DIV) Input hold time, read data valid on EM_D[15:0] after EM_SDCLK rising TBD TBD ns 1.2 1 ns Table 5-11. Switching Characteristics Over Recommended Operating Conditions for EMIF SDRAM/mSDRAM Interface (1) (see Figure 5-13 and Figure 5-14) NO. PARAMETER CVDD = 1.05 V DVDDEMIF = 3.3/2.8/2.5 V MIN MAX CVDD = 1.05 V DVDDEMIF = 1.8 V MIN UNIT MAX PRODUCT PREVIEW 1 tc(CLK) Cycle time, EMIF clock EM_SDCLK E E ns 2 tw(CLK) Pulse width, EMIF clock EM_SDCLK high or low 3 3 ns 3 td(CLKH-CSV) Delay time, EM_SDCLK rising to EMA_CS[1:0] valid TBD 4 toh(CLKH-CSIV) Output hold time, EM_SDCLK rising to EMA_CS[1:0] invalid TBD 5 td(CLKH-DQMV) Delay time, EM_SDCLK rising to EM_DQM[1:0] valid TBD 6 toh(CLKH-DQMIV) Output hold time, EM_SDCLK rising to EM_DQM[1:0] invalid TBD 7 td(CLKH-AV) Delay time, EM_SDCLK rising to EM_A[20:0] and EM_BA[1:0] valid TBD 8 toh(CLKH-AIV) Output hold time, EM_SDCLK rising to EM_A[20:0] and EM_BA[1:0] invalid TBD 9 td(CLKH-DV) Delay time, EM_SDCLK rising to EM_D[15:0] valid TBD 10 toh(CLKH-DIV) Output hold time, EM_SDCLK rising to EM_D[15:0] invalid TBD 11 td(CLKH-RASV) Delay time, EM_SDCLK rising to EM_SDRAS valid TBD 12 toh(CLKH-RASIV) Output hold time, EM_CLK rising to EM_SDRAS invalid TBD 13 td(CLKH-CASV) Delay time, EM_SDCLK rising to EM_SDCAS valid TBD 14 toh(CLKH-CASIV) Output hold time, EM_SDCLK rising to EM_SDCAS invalid TBD 15 td(CLKH-WEV) Delay time, EM_SDCLK rising to EM_WE valid TBD 16 toh(CLKH-WEIV) Output hold time, EM_SDCLK rising to EM_WE invalid TBD 17 tdis(CLKH-DHZ) Delay time, EM_SDCLK rising to EM_D[15:0] Hi-Z 18 tena(CLKH-DLZ) Output hold time, EM_SDCLK rising to EM_D[15:0] driving TBD 21 td(CLKH-CKEV) Delay time, EM_SDCLK rising to EM_SDCKE valid TBD toh(CLKH-WEIV) Output hold time, EM_SDCLK rising to EM_SDCKE invalid TBD 22 (1) 76 TBD TBD 15 TBD TBD TBD ns 15 TBD TBD TBD TBD 15 TBD 15 TBD 15 TBD TBD TBD TBD ns ns TBD TBD TBD ns ns TBD TBD ns ns TBD TBD TBD ns ns TBD TBD ns ns TBD TBD ns ns TBD TBD ns ns ns TBD ns ns E = EM_SDCLK period in ns. EM_SDCLK is selected either as SYSCLK or SYSCLK/2. For example, when SYSCLK is selected and set to 100 MHz, E = 10 ns. When operating the SDRAM/mSDRAM with DVDDEMIF = 3.3 V, 2.8 V, or 2.5 V, the maximum SDRAM/mSDRAM clock rate is equal to the System clock rate. When operating the SDRAM/mSDRAM at DVDDEMIF = 1.8 V, the maximum SDRAM/mSDRAM clock rate is half of the System clock rate. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 5-12. Timing Requirements for EMIF Asynchronous Memory (1) (see Figure 5-15, Figure 5-17, and Figure 5-18) CVDD = 1.05 V DVDDEMIF = 3.3/2.8/2.5/1.8 V NO. MIN NOM UNIT MAX READS and WRITES 2 tw(EM_WAIT) Pulse duration, EM_WAITx assertion and deassertion 2E ns 14.5 ns READS 12 tsu(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high 13 th(EMOEH-EMDIV) Hold time, EM_D[15:0] valid after EM_OE high 14 tsu (EMOEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase (2) 0 ns 4E + 13 ns 4E + 13 ns WRITES 26 (1) E = SYSCLK period in ns, if EMIF is set for "full rate" or E = SYSCLK/2 period in ns, if EMIF is set for "half rate" as defined by bit 14 of the EMIF Status register (0x1001h). For example, when EMIF is set to full rate and SYSCLK is selected and set to 100 MHz, E = 10 ns. Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended wait states. Figure 5-17 and Figure 5-18 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles. PRODUCT PREVIEW (2) tsu (EMWEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase (2) Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 77 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 5-13. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory (1) Figure 5-18) (3) NO. (2) (see Figure 5-16 and CVDD = 1.05 V DVDDEMIF = 3.3/2.8/2.5/1.8 V PARAMETER MIN UNIT NOM MAX READS and WRITES 1 td(TURNAROUND) Turn around time (TA)*E - 13 (TA)*E (TA)*E + 13 ns EMIF read cycle time (EW = 0) (RS+RST+RH)*E - 13 EMIF read cycle time (EW = 1) (RS+RST+RH+(EWC*16))*E 13 (RS+RST+RH)*E (RS+RST+RH)*E + 13 ns (RS+RST+RH+(EWC*16))*E (RS+RST+RH+(EWC*16))*E +139 ns Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0) Output setup time, EM_CS[5:2] low to EM_OE low (SS = 1) (RS)*E-13 (RS)*E (RS)*E+13 ns -13 0 +13 ns Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0) (RH)*E - 13 (RH)*E (RH)*E + 13 ns Output hold time, EM_OE high to EM_CS[5:2] high (SS = 1) -13 0 +13 ns READS PRODUCT PREVIEW 3 tc(EMRCYCLE) 4 tsu(EMCEL-EMOEL) 5 th(EMOEH-EMCEH) 6 tsu(EMBAV-EMOEL) Output setup time, EM_BA[1:0] valid to EM_OE low (RS)*E-13 (RS)*E (RS)*E+13 ns 7 th(EMOEH-EMBAIV) Output hold time, EM_OE high to EM_BA[1:0] invalid (RH)*E-13 (RH)*E (RH)*E+13 ns 8 tsu(EMBAV-EMOEL) Output setup time, EM_A[20:0] valid to EM_OE low (RS)*E-13 (RS)*E (RS)*E+13 ns 9 th(EMOEH-EMAIV) Output hold time, EM_OE high to EM_A[20:0] invalid (RH)*E-13 (RH)*E (RH)*E+13 ns EM_OE active low width (EW = 0) (RST)*E-13 (RST)*E (RST)*E+13 ns EM_OE active low width (EW = 1) (RST+(EWC*16))*E-13 (RST+(EWC*16))*E (RST+(EWC*16))*E+13 ns 4E-13 4E 4E+13 ns EMIF write cycle time (EW = 0) (WS+WST+WH)*E-13 (WS+WST+WH)*E (WS+WST+WH)*E+13 ns EMIF write cycle time (EW = 1) (WS+WST+WH+(EWC*16))*E 13 (WS+WST+WH+(EWC*16))*E (WS+WST+WH+(EWC*16))*E + 13 ns Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0) (WS)*E - 13 (WS)*E (WS)*E + 13 ns Output setup time, EM_CS[5:2] low to EM_WE low (SS = 1) -13 0 +13 ns Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0) (WH)*E-13 (WH)*E (WH)*E+13 ns Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1) -13 0 +13 ns 10 tw(EMOEL) 11 td(EMWAITH-EMOEH) Delay time from EM_WAITx deasserted to EM_OE high WRITES 15 tc(EMWCYCLE) 16 tsu(EMCSL-EMWEL) 17 th(EMWEH-EMCSH) 18 tsu(EMBAV-EMWEL) Output setup time, EM_BA[1:0] valid to EM_WE low (WS)*E-13 (WS)*E (WS)*E+13 ns 19 th(EMWEH-EMBAIV) Output hold time, EM_WE high to EM_BA[1:0] invalid (WH)*E-13 (WH)*E (WH)*E+13 ns 20 tsu(EMAV-EMWEL) Output setup time, EM_A[20:0] valid to EM_WE low (WS)*E-13 (WS)*E (WS)*E+13 ns 21 th(EMWEH-EMAIV) Output hold time, EM_WE high to EM_A[20:0] invalid (WH)*E-13 (WH)*E (WH)*E+13 ns (1) (2) (3) 78 TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Configuration and Asynchronous Wait Cycle Configuration Registers. E = SYSCLK period in ns, if EMIF is set for "full rate" or E = SYSCLK/2 period in ns, if EMIF is set for "half rate" as defined by bit 14 of the EMIF Status register (0x1001h). For example, when EMIF is set to full rate and SYSCLK is selected and set to 100 MHz, E = 10 ns. EWC = external wait cycles determined by EM_WAITx input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 5-13. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory Figure 5-18 ) (3) (continued) NO. (1) (2) (see Figure 5-16 and CVDD = 1.05 V DVDDEMIF = 3.3/2.8/2.5/1.8 V PARAMETER MIN NOM UNIT MAX EM_WE active low width (EW = 0) (WST)*E-13 (WST)*E (WST)*E+13 ns EM_WE active low width (EW = 1) (WST+(EWC*16))*E-13 (WST+(EWC*16))*E (WST+(EWC*16))*E+13 ns 3E-13 4E 4E+13 ns Output setup time, EM_D[15:0] valid to EM_WE low (WS)*E-13 (WS)*E (WS)*E+13 ns Output hold time, EM_WE high to EM_D[15:0] invalid (WH)*E-13 (WH)*E (WH)*E+13 ns tw(EMWEL) 23 td(EMWAITH-EMWEH) Delay time from EM_WAITx deasserted to EM_WE high 24 tsu(EMDV-EMWEL) 25 th(EMWEH-EMDIV) PRODUCT PREVIEW 22 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 79 TMS320C5504 SPRS659 – JANUARY 2010 5.9.5 www.ti.com EMIF Electrical Data/Timing CVDD = 1.3 V, DVDDEMIF = 3.3/2.8/2.5/1.8 V Table 5-14. Timing Requirements for EMIF SDRAM/mSDRAM Interface (see Figure 5-13 and Figure 5-14) CVDD = 1.3 V DVDDEMIF = 3.3/2.8/2.5 V NO. MIN 19 tsu(DV-CLKH) Input setup time, read data valid on EM_D[15:0] before EM_SDCLK rising 20 th(CLKH-DIV) Input hold time, read data valid on EM_D[15:0] after EM_SDCLK rising MAX CVDD = 1.3 V DVDDEMIF = 1.8 V UNI T MIN MAX TBD TBD ns 1.1 1 ns Table 5-15. Switching Characteristics Over Recommended Operating Conditions for EMIF SDRAM/mSDRAM Interface (1) (see Figure 5-13 and Figure 5-14) NO. PARAMETER CVDD = 1.3 V DVDDEMIF = 3.3/2.8/2.5 V MIN MAX PRODUCT PREVIEW 1 tc(CLK) Cycle time, EMIF clock EM_SDCLK 2 tw(CLK) Pulse width, EMIF clock EM_SDCLK high or low 3 td(CLKH-CSV) Delay time, EM_SDCLK rising to EMA_CS[1:0] valid TBD 4 toh(CLKH-CSIV) Output hold time, EM_SDCLK rising to EMA_CS[1:0] invalid TBD 5 td(CLKH-DQMV) Delay time, EM_SDCLK rising to EM_DQM[1:0] valid TBD 6 toh(CLKH-DQMIV) Output hold time, EM_SDCLK rising to EM_DQM[1:0] invalid TBD 7 td(CLKH-AV) Delay time, EM_SDCLK rising to EM_A[20:0] and EM_BA[1:0] valid TBD 8 toh(CLKH-AIV) Output hold time, EM_SDCLK rising to EM_A[20:0] and EM_BA[1:0] invalid TBD 9 td(CLKH-DV) Delay time, EM_SDCLK rising to EM_D[15:0] valid TBD 10 toh(CLKH-DIV) Output hold time, EM_SDCLK rising to EM_D[15:0] invalid TBD 11 td(CLKH-RASV) Delay time, EM_SDCLK rising to EM_SDRAS valid TBD 12 toh(CLKH-RASIV) Output hold time, EM_CLK rising to EM_SDRAS invalid TBD 13 td(CLKH-CASV) Delay time, EM_SDCLK rising to EM_SDCAS valid TBD 14 toh(CLKH-CASIV) Output hold time, EM_SDCLK rising to EM_SDCAS invalid TBD 15 td(CLKH-WEV) Delay time, EM_SDCLK rising to EM_WE valid TBD 16 toh(CLKH-WEIV) Output hold time, EM_SDCLK rising to EM_WE invalid TBD 17 tdis(CLKH-DHZ) Delay time, EM_SDCLK rising to EM_D[15:0] Hi-Z 18 tena(CLKH-DLZ) Output hold time, EM_SDCLK rising to EM_D[15:0] driving TBD 21 td(CLKH-CKEV) Delay time, EM_SDCLK rising to EM_SDCKE valid TBD 22 toh(CLKH-WEIV) Output hold time, EM_SDCLK rising to EM_SDCKE invalid TBD (1) 80 E CVDD = 1.3 V DVDDEMIF = 1.8 V MIN MAX E 3 ns 3 TBD TBD ns TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns ns TBD TBD ns ns TBD TBD ns ns TBD TBD TBD ns ns TBD TBD ns ns TBD TBD ns ns TBD TBD ns ns TBD TBD UNIT ns ns TBD ns ns E = EM_SDCLK period in ns. EM_SDCLK is selected either as SYSCLK or SYSCLK/2. For example, when SYSCLK is selected and set to 100 MHz, E = 10 ns. When operating the SDRAM/mSDRAM with DVDDEMIF = 3.3 V, 2.8 V, or 2.5 V, the maximum SDRAM/mSDRAM clock rate is equal to the System clock rate. When operating the SDRAM/mSDRAM at DVDDEMIF = 1.8 V, the maximum SDRAM/mSDRAM clock rate is half of the System clock rate. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 5-16. Timing Requirements for EMIF Asynchronous Memory (1) (see Figure 5-15, Figure 5-17, and Figure 5-18) CVDD = 1.3 V DVDDEMIF = 3.3/2.8/2.5/1.8 V NO. MIN NOM UNIT MAX READS and WRITES 2 tw(EM_WAIT) Pulse duration, EM_WAITx assertion and deassertion 2E ns 11 ns READS 12 tsu(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high 13 th(EMOEH-EMDIV) Hold time, EM_D[15:0] valid after EM_OE high 14 tsu (EMOEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase (2) 0 ns 4E + 7.5 ns 4E + 7.5 ns 26 (1) (2) tsu (EMWEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase (2) E = SYSCLK period in ns, if EMIF is set for "full rate" or E = SYSCLK/2 period in ns, if EMIF is set for "half rate" as defined by bit 14 of the EMIF Status register (0x1001h). For example, when EMIF is set to full rate and SYSCLK is selected and set to 100/120 MHz, E = 10/8.33 ns, respectively. Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended wait states. Figure 5-17 and Figure 5-18 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles. Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 81 PRODUCT PREVIEW WRITES TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 5-17. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory (1) Figure 5-17, and Figure 5-18) NO. (2) (3) (see Figure 5-15, CVDD = 1.3 V DVDDEMIF = 3.3/2.8/2.5/1.8 V PARAMETER MIN UNIT NOM MAX READS and WRITES 1 td(TURNAROUND) Turn around time (TA)*E - 7.5 (TA)*E (TA)*E + 7.5 ns EMIF read cycle time (EW = 0) (RS+RST+RH)*E - 7.5 EMIF read cycle time (EW = 1) (RS+RST+RH+(EWC*16))*E 7.5 (RS+RST+RH)*E (RS+RST+RH)*E + 7.5 ns (RS+RST+RH+(EWC*16))*E (RS+RST+RH+(EWC*16))*E + 7.5 ns Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0) Output setup time, EM_CS[5:2] low to EM_OE low (SS = 1) (RS)*E - 7.5 (RS)*E (RS)*E + 7.5 ns -7.5 0 +7.5 ns Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0) (RH)*E - 7.5 (RH)*E (RH)*E + 7.5 ns Output hold time, EM_OE high to EM_CE[5:2] high (SS = 1) -7.5 0 +7.5 ns READS PRODUCT PREVIEW 3 tc(EMRCYCLE) 4 tsu(EMCSL-EMOEL) 5 th(EMOEH-EMCSH) 6 tsu(EMBAV-EMOEL) Output setup time, EM_BA[1:0] valid to EM_OE low (RS)*E - 7.5 (RS)*E (RS)*E + 7.5 ns 7 th(EMOEH-EMBAIV) Output hold time, EM_OE high to EM_BA[1:0] invalid (RH)*E - 7.5 (RH)*E (RH)*E + 7.5 ns 8 tsu(EMAV-EMOEL) Output setup time, EM_A[20:0] valid to EM_OE low (RS)*E - 7.5 (RS)*E (RS)*E + 7.5 ns 9 th(EMOEH-EMAIV) Output hold time, EM_OE high to EM_A[20:0] invalid (RH)*E - 7.5 (RH)*E (RH)*E + 7.5 ns EM_OE active low width (EW = 0) (RST)*E - 7.5 (RST)*E (RST)*E + 7.5 ns EM_OE active low width (EW = 1) (RST+(EWC*16))*E - 7.5 (RST+(EWC*16))*E (RST+(EWC*16))*E + 7.5 ns 4E - 7.5 4E 4E + 7.5 ns EMIF write cycle time (EW = 0) (WS+WST+WH)*E - 7.5 (WS+WST+WH)*E (WS+WST+WH)*E + 7.5 ns EMIF write cycle time (EW = 1) (WS+WST+WH+(EWC*16))*E 7.5 (WS+WST+WH+(EWC*16))*E (WS+WST+WH+(EWC*16))*E + 7.5 ns Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0) (WS)*E - 7.5 (WS)*E (WS)*E +7. 5 ns Output setup time, EM_CS[5:2] low to EM_WE low (SS = 1) -7.5 0 +7.5 ns Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0) (WH)*E - 7.5 (WH)*E (WH)*E + 7.5 ns Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1) -7.5 0 +7.5 ns 10 tw(EMOEL) 11 td(EMWAITH-EMOEH) Delay time from EM_WAITx deasserted to EM_OE high WRITES 15 tc(EMWCYCLE) 16 tsu(EMCSL-EMWEL) 17 th(EMWEH-EMCSH) 18 tsu(EMBAV-EMWEL) Output setup time, EM_BA[1:0] valid to EM_WE low (WS)*E - 7.5 (WS)*E (WS)*E + 7.5 ns 19 th(EMWEH-EMBAIV) Output hold time, EM_WE high to EM_BA[1:0] invalid (WH)*E - 7.5 (WH)*E (WH)*E + 7.5 ns 20 tsu(EMAV-EMWEL) Output setup time, EM_A[20:0] valid to EM_WE low (WS)*E - 7.5 (WS)*E (WS)*E + 7.5 ns 21 th(EMWEH-EMAIV) Output hold time, EM_WE high to EM_A[20:0] invalid (WH)*E - 7.5 (WH)*E (WH)*E + 7.5 ns (1) (2) (3) 82 TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Configuration and Asynchronous Wait Cycle Configuration Registers. E = SYSCLK period in ns, if EMIF is set for "full rate" or E = SYSCLK/2 period in ns, if EMIF is set for "half rate" as defined by bit 14 of the EMIF Status register (0x1001h). For example, when EMIF is set to full rate and SYSCLK is selected and set to 100/120 MHz, E = 10/8.33, respectively ns. EWC = external wait cycles determined by EM_WAITx input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 5-17. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory Figure 5-17 , and Figure 5-18 ) (continued) NO. (1) (2) (3) (see Figure 5-15 , CVDD = 1.3 V DVDDEMIF = 3.3/2.8/2.5/1.8 V PARAMETER MIN NOM UNIT MAX EM_WE active low width (EW = 0) (WST)*E - 7.5 (WST)*E (WST)*E + 7.5 ns EM_WE active low width (EW = 1) (WST+(EWC*16))*E - 7.5 (WST+(EWC*16))*E (WST+(EWC*16))*E + 7.5 ns 3E - 7.5 4E 4E + 7.5 ns Output setup time, EM_D[15:0] valid to EM_WE low (WS)*E - 7.5 (WS)*E (WS)*E + 7.5 ns Output hold time, EM_WE high to EM_D[15:0] invalid (WH)*E - 7.5 (WH)*E (WH)*E + 7.5 ns tw(EMWEL) 23 td(EMWAITH-EMWEH) Delay time from EM_WAITx deasserted to EM_WE high 24 tsu(EMDV-EMWEL) 25 th(EMWEH-EMDIV) PRODUCT PREVIEW 22 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 83 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com 1 BASIC mSDRAM WRITE OPERATION 2 2 EM_SDCLK 3 4 EM_CS[1:0] 5 6 EM_DQM[1:0] 7 8 7 8 EM_BA[1:0] EM_A[20:0] 9 10 EM_D[15:0] 11 12 EM_SDRAS PRODUCT PREVIEW 13 EM_SDCAS 15 16 EM_WE Figure 5-13. EMIF Basic SDRAM/mSDRAM Write Operation BASIC mSDRAM READ OPERATION 1 2 2 EM_SDCLK 3 4 EM_CS[1:0] 5 6 EM_DQM[1:0] 7 8 7 8 EM_BA[1:0] EM_A[20:0] 19 17 20 2 EM_CLK Delay 18 EM_D[15:0] 11 12 EM_SDRAS 13 14 EM_SDCAS EM_WE Figure 5-14. EMIF Basic SDRAM/mSDRAM Read Operation 84 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 3 1 EM_CS[5:2] EM_BA[1:0] EM_A[20:0] 4 8 5 9 6 7 10 EM_OE 13 12 EM_D[15:0] PRODUCT PREVIEW EM_WE Figure 5-15. Asynchronous Memory Read Timing for EMIF 15 1 EM_CS[5:2] EM_BA[1:0] EM_A[20:0] 16 17 18 19 20 22 21 EM_WE 25 24 EM_D[15:0] EM_OE Figure 5-16. Asynchronous Memory Write Timing for EMIF Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 85 TMS320C5504 SPRS659 – JANUARY 2010 EM_CS[5:2] www.ti.com SETUP STROBE Extended Due to EM_WAITx STROBE HOLD EM_BA[1:0] EM_A[20:0] EM_D[15:0] 14 11 EM_OE 2 EM_WAITx Asserted 2 Deasserted Figure 5-17. EM_WAITx Read Timing Requirements EM_CS[5:2] SETUP STROBE Extended Due to EM_WAITx STROBE HOLD PRODUCT PREVIEW EM_BA[1:0] EM_A[20:0] EM_D[15:0] 28 25 EM_WE 2 EM_WAITx Asserted 2 Deasserted Figure 5-18. EM_WAITx Write Timing Requirements 86 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 5.10 Multimedia Card/Secure Digital (MMC/SD) The C5504 includes two MMC/SD controller s which are compliant with MMC V3.31, Secure Digital Part 1 Physical Layer Specification V2.0, and Secure Digital Input Output (SDIO) V3.3 specifications. The MMC/SD card controller supports these industry standards and assumes the reader is familiar with these standards. Each C5504 MMC/SD Controller has the following features: • Multimedia Card/Secure Digital (MMC/SD) protocol support • Programmable clock frequency • 512 bit Read/Write FIFO to lower system overhead • Slave DMA transfer capability The MMC/SD card controller transfers data between the CPU and DMA controller on one side and MMC/SD card on the other side. The CPU and DMA controller can read/write the data in the card by accessing the registers in the MMC/SD controller. The MMC/SD controller on this device, does not support the SPI mode of operation. 5.10.1 MMC/SD Peripheral Register Description(s) Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 PRODUCT PREVIEW Table 5-18 shows the MMC/SD registers. The MMC/SD0 registers start at address 0x3A00. 87 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 5-18. MMC/SD0 Registers HEX ADDRESS RANGE ACRONYM 3A00h MMCCTL MMC Control Register 3A04h MMCCLK MMC Memory Clock Control Register 3A08h MMCST0 MMC Status Register 0 3A0Ch MMCST1 MMC Status Register 1 PRODUCT PREVIEW 88 REGISTER NAME 3A10h MMCIM 3A14h MMCTOR MMC Interrupt Mask Register MMC Response Time-Out Register 3A18h MMCTOD MMC Data Read Time-Out Register 3A1Ch MMCBLEN MMC Block Length Register 3A20h MMCNBLK MMC Number of Blocks Register 3A24h MMCNBLC MMC Number of Blocks Counter Register 3A28h MMCDRR1 MMC Data Receive 1 Register 3A29h MMCDRR2 MMC Data Receive 2 Register 3A2Ch MMCDXR1 MMC Data Transmit 1 Register 3A2Dh MMCDXR2 MMC Data Transmit 2 Register 3A30h MMCCMD MMC Command Register 3A34h MMCARGHL MMC Argument Register 3A38h MMCRSP0 MMC Response Register 0 3A39h MMCRSP1 MMC Response Register 1 3A3Ch MMCRSP2 MMC Response Register 2 3A3Dh MMCRSP3 MMC Response Register 3 3A40h MMCRSP4 MMC Response Register 4 3A41h MMCRSP5 MMC Response Register 5 3A44h MMCRSP6 MMC Response Register 6 3A45h MMCRSP7 MMC Response Register 7 3A48h MMCDRSP MMC Data Response Register 3A50h MMCCIDX MMC Command Index Register 3A64h – 3A70h – 3A74h MMCFIFOCTL Reserved MMC FIFO Control Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 5-19. MMC/SD1 Registers HEX ADDRESS RANGE ACRONYM 3B00h MMCCTL MMC Control Register 3B04h MMCCLK MMC Memory Clock Control Register 3B08h MMCST0 MMC Status Register 0 3B0Ch MMCST1 MMC Status Register 1 REGISTER NAME MMCIM 3B14h MMCTOR MMC Interrupt Mask Register MMC Response Time-Out Register 3B18h MMCTOD MMC Data Read Time-Out Register 3B1Ch MMCBLEN MMC Block Length Register 3B20h MMCNBLK MMC Number of Blocks Register 3B24h MMCNBLC MMC Number of Blocks Counter Register 3B28h MMCDRR1 MMC Data Receive 1 Register 3B29h MMCDRR2 MMC Data Receive 2 Register 3B2Ch MMCDXR1 MMC Data Transmit 1 Register 3B2Dh MMCDXR2 MMC Data Transmit 2 Register 3B30h MMCCMD MMC Command Register 3B34h MMCARGHL MMC Argument Register 3B38h MMCRSP0 MMC Response Register 0 3B39h MMCRSP1 MMC Response Register 1 3B3Ch MMCRSP2 MMC Response Register 2 3B3Dh MMCRSP3 MMC Response Register 3 3B40h MMCRSP4 MMC Response Register 4 3B41h MMCRSP5 MMC Response Register 5 3B44h MMCRSP6 MMC Response Register 6 3B45h MMCRSP7 MMC Response Register 7 3B48h MMCDRSP MMC Data Response Register 3B50h MMCCIDX MMC Command Index Register 3B74h MMCFIFOCTL Copyright © 2010, Texas Instruments Incorporated PRODUCT PREVIEW 3B10h MMC FIFO Control Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 89 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com 5.10.2 MMC/SD Electrical Data/Timing Table 5-20. Timing Requirements for MMC/SD (see Figure 5-19 and Figure 5-22) NO. CVDD = 1.3 V CVDD = 1.05 V FAST MODE STD MODE MIN MAX MIN UNIT MAX 1 tsu(CMDV-CLKH) Setup time, MMCx_CMD data input valid before MMCx_CLK high 3 3 ns 2 th(CLKH-CMDV) Hold time, MMCx_CMD data input valid after MMCx_CLK high 3 3 ns 3 tsu(DATV-CLKH) Setup time, MMC_Dx data input valid before MMCx_CLK high 3 3 ns 4 th(CLKH-DATV) Hold time, MMC_Dx data input valid after MMCx_CLK high 3 3 ns Table 5-21. Switching Characteristics Over Recommended Operating Conditions for MMC Output (1) (see Figure 5-19 and Figure 5-22) NO. PARAMETER CVDD = 1.3 V CVDD = 1.05 V FAST MODE STD MODE UNIT MIN MAX MIN MAX 7 f(CLK) Operating frequency, MMCx_CLK 0 50 (2) 0 25 (2) MHz 8 f(CLK_ID) Identfication mode frequency, MMCx_CLK 0 400 0 400 kHz PRODUCT PREVIEW 9 tw(CLKL) Pulse width, MMCx_CLK low 7 10 10 tw(CLKH) Pulse width, MMCx_CLK high 7 10 11 tr(CLK) Rise time, MMCx_CLK TBD 10 ns 12 tf(CLK) Fall time, MMCx_CLK TBD 10 ns 13 td(MDCLKL-CMDIV) Delay time, MMCx_CLK low to MMC_CMD data output invalid 14 td(MDCLKL-CMDV) Delay time, MMCx_CLK low to MMC_CMD data output valid 15 td(MDCLKL-DATIV) Delay time, MMCx_CLK low to MMC_Dx data output invalid td(MDCLKL-DATV) Delay time, MMCx_CLK low to MMC_Dx data output valid 16 (1) (2) -4 ns ns -4 ns 4 5 -4 -4 ns ns 4 5 ns For MMC/SD, the parametric values are measured at DVDDIO = 3.3 V. Use this value or SYS_CLK/2 whichever is smaller. 7 9 10 MMCx_CLK 13 14 VALID MMCx_CMD Figure 5-19. MMC/SD Host Command Write Timing 9 10 7 MMCx_CLK 4 4 3 MMCx_Dx Start 3 D0 D1 Dx End Figure 5-20. MMC/SD Card Response Timing 90 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 9 7 10 MMCx_CLK 1 2 MMCx_CMD START XMIT Valid Valid Valid END Figure 5-21. MMC/SD Host Write Timing 7 9 10 MMCx_CLK 15 16 VALID MMCx_DAT Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 PRODUCT PREVIEW Figure 5-22. MMC/SD Data Write Timing 91 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com 5.11 Real-Time Clock (RTC) The C5504 includes a Real-Time Clock (RTC) with its own separated power supply and isolation circuits. The separate supply and isolation circuits allow the RTC to run while the rest of the C5504 device (Core and I/O) is powered off. All RTC registers are preserved (except for RTC Control and RTC Update Registers) and the counter continues to operate when the device is powered off. The RTC is able to output an alarm or periodic interrupt on the WAKEUP pin to cause external power management to re-enable power to the DSP Core and I/O. PRODUCT PREVIEW The C5504 RTC provides the following features: • 100-year calendar up to year 2099. • Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation • Millisecond time correction • Binary-coded-decimal (BCD) representation of time, calendar, and alarm • 24-hour clock mode • Second, minute, hour, day, or week alarm interrupt • Periodic interrupt: every millisecond, second, minute, hour, or day • Alarm interrupt: precise time of day • Single interrupt to the DSP CPU • 32.768-kHz crystal oscillator with frequency calibration Control of the RTC is maintained through a set of I/O memory mapped registers (see Table 5-22). Note that any write to these registers will be synchronized to the RTC 32.768-KHz clock; thus, the CPU must run at least 3X faster than the RTC. Writes to these registers will not be evident until the next two 32.768-KHz clock cycles later. Furthermore, if the RTC Oscillator is disabled, no RTC register can be written to. The RTC has its own power-on-reset (POR) circuit which resets the registers in the RTC core domain when power is first applied to the CVDD_RTC power pin. The RTC flops are not reset by the device's RESET pin. The scratch registers in the RTC can be used to take advantage of this unique reset domain to keep track of when the DSP boots and whether the RTC time registers have already been initialized to the current clock time or whether the software needs to go into a routine to prompt the user to set the time/date. 92 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 5.11.1 RTC Peripheral Register Description(s) Table 5-22 shows the RTC registers. Table 5-22. Real-Time Clock (RTC) Registers ACRONYM REGISTER NAME 1900h RTCINTEN 1901h RTCUPDATE RTC Interrupt Enable Register RTC Update Register 1904h RTCMIL Milliseconds Register 1905h RTCMILA Milliseconds Alarm Register 1908h RTCSEC Seconds Register 1909h RTCSECA 190Ch RTCMIN Seconds Alarm Register Minutes Register 190Dh RTCMINA Minutes Alarm Register 1910h RTCHOUR Hours Register 1911h RTCHOURA 1914h RTCDAY 1915h RTCDAYA 1918h RTCMONTH Hours Alarm Register Days Register Days Alarm Register Months Register 1919h RTCMONTHA 191Ch RTCYEAR 191Dh RTCYEARA 1920h RTCINTFL 1921h RTCNOPWR RTC Lost Power Status Register 1924h RTCINTREG RTC Interrupt Register 1928h RTCDRIFT Months Alarm Register Years Register Years Alarm Register RTC Interrupt Flag Register RTC Compensation Register 192Ch RTCOSC 1930h RTCPMGT RTC Power Management Register 1960h RTCSCR1 RTC LSW Scratch Register 1 1961h RTCSCR2 RTC MSW Scratch Register 2 1964h RTCSCR3 RTC LSW Scratch Register 3 1965h RTCSCR4 RTC MSW Scratch Register 4 Copyright © 2010, Texas Instruments Incorporated PRODUCT PREVIEW HEX ADDRESS RANGE RTC Oscillator Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 93 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com 5.12 Inter-Integrated Circuit (I2C) The inter-integrated circuit (I2C) module provides an interface between C5504 and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External components attached to this 2-wire serial bus can transmit/receive 2 to 8-bit data to/from the DSP through the I2C module. The I2C port does not support CBUS compatible devices. The I2C port supports the following features: • Compatible with Philips I2C Specification Revision 2.1 (January 2000) • Data Transfer Rate from 10 kbps to 400 kbps (Philips Fast-Mode Rate) • Noise Filter to Remove Noise 50 ns or Less • Seven- and Ten-Bit Device Addressing Modes • Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality • One Read DMA Event and One Write DMA Event, which can be used by the DMA Controller • One Interrupt that can be used by the CPU • Slew-Rate Limited Open-Drain Output Buffers PRODUCT PREVIEW The I2C module clock must be in the range from 6.7 MHz to 13.3 MHz. This is necessary for proper operation of the I2C module. With the I2C module clock in this range, the noise filters on the SDA and SCL pins suppress noise that has a duration of 50 ns or shorter. The I2C module clock is derived from the DSP clock divided by a programmable prescaler. 94 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com 5.12.1 SPRS659 – JANUARY 2010 I2C Peripheral Register Description(s) Table 5-23 shows the Inter-Integrated Circuit (I2C) registers. Table 5-23. Inter-Integrated Circuit (I2C) Registers ACRONYM REGISTER NAME 1A00h ICOAR I2C Own Address Register 1A04h ICIMR I2C Interrupt Mask Register 1A08h ICSTR I2C Interrupt Status Register 1A0Ch ICCLKL I2C Clock Low-Time Divider Register 1A10h ICCLKH I2C Clock High-Time Divider Register 1A14h ICCNT I2C Data Count Register 1A18h ICDRR I2C Data Receive Register 1A1Ch ICSAR I2C Slave Address Register 1A20h ICDXR I2C Data Transmit Register 1A24h ICMDR I2C Mode Register 1A28h ICIVR I2C Interrupt Vector Register 1A2Ch ICEMDR I2C Extended Mode Register 1A30h ICPSC I2C Prescaler Register 1A34h ICPID1 I2C Peripheral Identification Register 1 1A38h ICPID2 I2C Peripheral Identification Register 2 Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 PRODUCT PREVIEW HEX ADDRESS RANGE 95 TMS320C5504 SPRS659 – JANUARY 2010 5.12.2 www.ti.com I2C Electrical Data/Timing Table 5-24. Timing Requirements for I2C Timings (1) (see Figure 5-23) CVDD = 1.05 V CVDD = 1.3 V NO. STANDARD MODE MIN PRODUCT PREVIEW (2) (3) (4) (5) (6) 96 MIN MAX 1 tc(SCL) Cycle time, SCL 10 2.5 µs 2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs 3 th(SCLL-SDAL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs 4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs 5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs 6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100 (2) (3) (3) 7 (1) MAX UNIT FAST MODE th(SDA-SCLL) Hold time, SDA valid after SCL low 0 8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 9 tr(SDA) Rise time, SDA (5) 1000 20 + 0.1Cb 300 ns 10 tr(SCL) Rise time, SCL (5) 1000 20 + 0.1Cb 300 ns 11 tf(SDA) Fall time, SDA (5) 300 20 + 0.1Cb 300 ns 12 tf(SCL) Fall time, SCL (5) 300 20 + 0.1Cb 300 ns 13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 14 tw(SP) Pulse duration, spike (must be suppressed) 15 Cb (6) Capacitive load for each bus line 0 ns 0.9 (4) 1.3 4 (6) (6) (6) (6) µs 0.6 0 400 µs µs 50 ns 400 pF The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. Also these pins are not 3.6 V-tolerant (their VIH cannot go above DVDDIO + 0.3 V). A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. The rise/fall times are measured at 30% and 70% of DVDDIO. The fall time is only slightly influenced by the external bus load (Cb) and external pullup resistor. However, the rise time (tr) is mainly determined by the bus load capacitance and the value of the pullup resistor. The pullup resistor must be selected to meet the I2C rise and fall time values specified. Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 11 9 SDA 6 8 14 4 13 5 10 SCL 1 12 3 2 7 3 Stop Start Repeated Start Stop PRODUCT PREVIEW Figure 5-23. I2C Receive Timings Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 97 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 5-25. Switching Characteristics for I2C Timings (1) (see Figure 5-24) CVDD = 1.05 V CVDD = 1.3 V NO. PARAMETER STANDARD MODE MIN 16 PRODUCT PREVIEW (1) (2) MAX UNIT FAST MODE MIN MAX tc(SCL) Cycle time, SCL 10 2.5 µs 17 td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) 4.7 0.6 µs 18 td(SDAL-SCLL) Delay time, SDA low to SCL low (for a START and a repeated START condition) 4 0.6 µs 19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs 20 tw(SCLH) Pulse duration, SCL high 4 0.6 µs 21 td(SDAV-SCLH) Delay time, SDA valid to SCL high 250 100 22 tv(SCLL-SDAV) Valid time, SDA valid after SCL low 0 0 23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 24 tr(SDA) Rise time, SDA (2) 1000 20 + 0.1Cb 300 ns 25 tr(SCL) Rise time, SCL (2) 1000 20 + 0.1Cb 300 ns 26 tf(SDA) Fall time, SDA (2) 300 20 + 0.1Cb 300 ns 27 tf(SCL) Fall time, SCL (2) 300 20 + 0.1Cb 300 ns 28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) 29 Cp Capacitance for each I2C pin 10 pF 4 (1) (1) (1) (1) ns 0.9 µs 0.6 10 µs µs Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. The rise/fall times are measured at 30% and 70% of DVDDIO. The fall time is only slightly influenced by the external bus load (Cb) and external pullup resistor. However, the rise time (tr) is mainly determined by the bus load capacitance and the value of the pullup resistor. The pullup resistor must be selected to meet the I2C rise and fall time values specified. 26 24 SDA 21 23 19 28 20 25 SCL 16 27 18 17 22 18 Stop Start Repeated Start Stop Figure 5-24. I2C Transmit Timings 98 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 5.13 Universal Asynchronous Receiver/Transmitter (UART) The UART performs serial-to-parallel conversions on data received from an external peripheral device and parallel-to-serial conversions on data transmitted to an external peripheral device via a serial bus. PRODUCT PREVIEW The C5504 has one UART peripheral with the following features: • Programmable baud rates (frequency pre-scale values from 1 to 65535) • Fully programmable serial interface characteristics: – 5, 6, 7, or 8-bit characters – Even, odd, or no PARITY bit generation and detection – 1, 1.5, or 2 STOP bit generation • 16-byte depth transmitter and receiver FIFOs: – The UART can be operated with or without the FIFOs – 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA • DMA signaling capability for both received and transmitted data • CPU interrupt capability for both received and transmitted data • False START bit detection • Line break generation and detection • Internal diagnostic capabilities: – Loopback controls for communications link fault isolation – Break, parity, overrun, and framing error simulation • Programmable autoflow control using CTS and RTS signals 5.13.1 UART Peripheral Register Description(s) Table 5-26 shows the UART registers. Table 5-26. UART Registers HEX ADDRESS RANGE ACRONYM 1B00h RBR Receiver Buffer Register (read only) 1B00h THR Transmitter Holding Register (write only) 1B02h IER Interrupt Enable Register 1B04h IIR Interrupt Identification Register (read only) 1B04h FCR FIFO Control Register (write only) 1B06h LCR Line Control Register REGISTER NAME 1B08h MCR Modem Control Register 1B0Ah LSR Line Status Register 1B0Ch MSR Modem Status Register 1B0Eh SCR Scratch Register 1B10h DLL Divisor LSB Latch 1B12h DLH Divisor MSB Latch 1B18h PWREMU_MGMT Copyright © 2010, Texas Instruments Incorporated Power and Emulation Management Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 99 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com 5.13.2 UART Electrical Data/Timing [Receive/Transmit] Table 5-27. Timing Requirements for UART Receive (1) (2) (see Figure 5-25) CVDD = 1.05 V NO. CVDD = 1.3 V MIN MAX MIN MAX UNIT 4 tw(URXDB) Pulse duration, receive data bit (UART_RXD) [15/30/100 pF] U - 3.5 U+3 U - 3.5 U+3 ns 5 tw(URXSB) Pulse duration, receive start bit [15/30/100 pF] U - 3.5 U+3 U - 3.5 U+3 ns (1) (2) U = UART baud time = 1/programmed baud rate. These parametric values are measured at DVDDIO = 3.3 V, 2.75 V, and 2.5 V Table 5-28. Switching Characteristics Over Recommended Operating Conditions for UART Transmit (1) (see Figure 5-25) NO. 1 2 3 PRODUCT PREVIEW (1) (2) CVDD = 1.05 V PARAMETER MIN CVDD = 1.3 V MAX f(baud) Maximum programmable bit rate tw(UTXDB) Pulse duration, transmit data bit (UART_TXD) [15/30/100 pF] U - 3.5 U+4 tw(UTXSB) Pulse duration, transmit start bit [15/30/100 pF] U - 3.5 U+4 MIN 3.75 MAX (2) UNIT 6.25 MHz U - 3.5 U+4 ns U - 3.5 U+4 ns U = UART baud time = 1/programmed baud rate. These parametric values are measured at DVDDIO = 3.3 V, 2.75 V, and 2.5 V 3 2 UART_TXD Start Bit Data Bits 5 4 UART_RXD Start Bit Data Bits Figure 5-25. UART Transmit/Receive Timing 100 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 5.14 Inter-IC Sound (I2S) The C5504 I2S peripherals allow serial transfer of full-duplex streaming data, usually audio data, between the device and an external I2S peripheral device such as an audio codec. The C5504 supports 4 independent dual-channel I2S peripherals, each with the following features: • Full-duplex (transmit and receive) dual-channel communication • Double buffered data registers that allow for continuous data streaming • I2S/Left-justified and DSP data format with a data delay of 1 or 2 bits • Data word-lengths of 8, 10, 12, 14, 16, 18, 20, 24, or 32 bits • Ability to sign-extend received data samples for easy use in signal processing algorithms • Programmable polarity for both frame synchronization and bit clocks • Stereo (in I2S/Left-justified or DSP data formats) or mono (in DSP data format) mode • Detection of over-run, under-run, and frame-sync error conditions 5.14.1 I2S Peripheral Register Description(s) Table 5-29 through Table 5-32 show the I2S0 through I2S3 registers. HEX ADDRESS RANGE ACRONYM PRODUCT PREVIEW Table 5-29. I2S0 Registers REGISTER NAME 2800h I2S0SCTRL I2S0 Serializer Control Register 2804h I2S0SRATE I2S0 Sample Rate Generator Register 2808h I2S0TXLT0 I2S0 Transmit Left Data 0 Register 2809h I2S0TXLT1 I2S0 Transmit Left Data 1 Register 280Ch I2S0TXRT0 I2S0 Transmit Right Data 0 Register 280Dh I2S0TXRT1 I2S0 Transmit Right Data 1 Register 2810h I2S0INTFL I2S0 Interrupt Flag Register 2814h I2S0INTMASK I2S0 Interrupt Mask Register 2828h I2S0RXLT0 I2S0 Receive Left Data 0 Register 2829h I2S0RXLT1 I2S0 Receive Left Data 1 Register 282Ch I2S0RXRT0 I2S0 Receive Right Data 0 Register 282Dh I2S0RXRT1 I2S0 Receive Right Data 1 Register Table 5-30. I2S1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 2900h I2S1SCTRL I2S1 Serializer Control Register 2904h I2S1SRATE I2S1 Sample Rate Generator Register 2908h I2S1TXLT0 I2S1 Transmit Left Data 0 Register 2909h I2S1TXLT1 I2S1 Transmit Left Data 1 Register 290Ch I2S1TXRT0 I2S1 Transmit Right Data 0 Register 290Dh I2S1TXRT1 I2S1 Transmit Right Data 1 Register 2910h I2S1INTFL I2S1 Interrupt Flag Register 2914h I2S1INTMASK I2S1 Interrupt Mask Register 2928h I2S1RXLT0 I2S1 Receive Left Data 0 Register 2929h I2S1RXLT1 I2S1 Receive Left Data 1 Register 292Ch I2S1RXRT0 I2S1 Receive Right Data 0 Register 292Dh I2S1RXRT1 I2S1 Receive Right Data 1 Register Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 101 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 5-31. I2S2 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 2A00h I2S2SCTRL I2S2 Serializer Control Register 2A04h I2S2SRATE I2S2 Sample Rate Generator Register 2A08h I2S2TXLT0 I2S2 Transmit Left Data 0 Register 2A09h I2S2TXLT1 I2S2 Transmit Left Data 1 Register 2A0Ch I2S2TXRT0 I2S2 Transmit Right Data 0 Register 2A0Dh I2S2TXRT1 I2S2 Transmit Right Data 1 Register 2A10h I2S2INTFL I2S2 Interrupt Flag Register 2A14h I2S2INTMASK I2S2 Interrupt Mask Register 2A28h I2S2RXLT0 I2S2 Receive Left Data 0 Register 2A29h I2S2RXLT1 I2S2 Receive Left Data 1 Register 2A2Ch I2S2RXRT0 I2S2 Receive Right Data 0 Register 2A2Dh I2S2RXRT1 I2S2 Receive Right Data 1 Register Table 5-32. I2S3 Registers PRODUCT PREVIEW HEX ADDRESS RANGE 102 ACRONYM REGISTER NAME 2B00h I2S3SCTRL I2S3 Serializer Control Register 2B04h I2S3SRATE I2S3 Sample Rate Generator Register 2B08h I2S3TXLT0 I2S3 Transmit Left Data 0 Register 2B09h I2S3TXLT1 I2S3 Transmit Left Data 1 Register 2B0Ch I2S3TXRT0 I2S3 Transmit Right Data 0 Register 2B0Dh I2S3TXRT1 I2S3 Transmit Right Data 1 Register 2B10h I2S3INTFL I2S3 Interrupt Flag Register 2B14h I2S3INTMASK I2S3 Interrupt Mask Register 2B28h I2S3RXLT0 I2S3 Receive Left Data 0 Register 2B29h I2S3RXLT1 I2S3 Receive Left Data 1 Register 2B2Ch I2S3RXRT0 I2S3 Receive Right Data 0 Register 2B2Dh I2S3RXRT1 I2S3 Receive Right Data 1 Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 5.14.2 I2S Electrical Data/Timing Table 5-33. Timing Requirements for I2S [I/O = 3.3 V, 2.8 V, and 2.5 V] (1) (see Figure 5-26) NO. CVDD = 1.05 V MIN CVDD = 1.3 V MIN CVDD = 1.05 V CVDD = 1.3 V MIN MIN MAX MAX UN IT MAX 40 or 2P (1) 40 or 2P (1) 40 or 2P (1) 40 or 2P (1) (2) ns 1 tc(CLK) Cycle time, I2S_CLK 2 tw(CLKH) Pulse duration, I2S_CLK high 20 20 20 20 ns 3 tw(CLKL) Pulse duration, I2S_CLK low 20 20 20 20 ns tsu(RXV-CLKH) Setup time, I2S_RX valid before I2S CLK high (CLKPOL = 0) 5 5 TBD TBD ns tsu(RXV-CLKL) Setup time, I2S_RX valid before I2S_CLK low (CLKPOL = 1) 5 5 TBD TBD ns th(CLKH-RXV) Hold time, I2S_RX valid after I2S_CLK high (CLKPOL = 0) TBD TBD TBD TBD ns th(CLKL-RXV) Hold time, I2S_RX valid after I2S_CLK low (CLKPOL = 1) TBD TBD TBD TBD ns tsu(FSV-CLKH) Setup time, I2S_FS valid before I2S_CLK high (CLKPOL = 0) – – 15 15 ns tsu(FSV-CLKL) Setup time, I2S_FS valid before I2S_CLK low (CLKPOL = 1) – – 15 15 ns th(CLKH-FSV) Hold time, I2S_FS valid after I2S_CLK high (CLKPOL = 0) – – tw(CLKH) + TBD (3) tw(CLKH) + TBD (3) ns th(CLKL-FSV) Hold time, I2S_FS valid after I2S_CLK low (CLKPOL = 1) – – tw(CLKL) + TBD (3) tw(CLKL) + TBD (3) ns 7 8 9 10 (1) (2) (3) MAX SLAVE (2) (2) (2) P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns. Use whichever value is greater. In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK). Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 103 PRODUCT PREVIEW MASTER TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 5-34. Timing Requirements for I2S [I/O = 1.8 V] (1) (see Figure 5-26) MASTER NO. CVDD = 1.05 V MIN MAX SLAVE CVDD = 1.3 V MIN 50 or 2P (1) 40 or 2P (1) 1 tc(CLK) Cycle time, I2S_CLK 2 tw(CLKH) Pulse duration, I2S_CLK high 25 20 3 tw(CLKL) Pulse duration, I2S_CLK low 25 20 tsu(RXV-CLKH) Setup time, I2S_RX valid before I2S CLK high (CLKPOL = 0) 5 tsu(RXV-CLKL) Setup time, I2S_RX valid before I2S_CLK low (CLKPOL = 1) th(CLKH-RXV) MIN MIN MAX 50 or 2P (1) MAX 40 or 2P UN IT MAX (1) ns 25 20 ns 25 20 ns 5 TBD TBD ns 5 5 TBD TBD ns Hold time, I2S_RX valid after I2S_CLK high (CLKPOL = 0) TBD TBD TBD TBD ns th(CLKL-RXV) Hold time, I2S_RX valid after I2S_CLK low (CLKPOL = 1) TBD TBD TBD TBD ns tsu(FSV-CLKH) Setup time, I2S_FS valid before I2S_CLK high (CLKPOL = 0) – – 15 15 ns tsu(FSV-CLKL) Setup time, I2S_FS valid before I2S_CLK low (CLKPOL = 1) – – 15 15 ns th(CLKH-FSV) Hold time, I2S_FS valid after I2S_CLK high (CLKPOL = 0) – – tw(CLKH) + TBD (3) tw(CLKH) + TBD (3) ns th(CLKL-FSV) Hold time, I2S_FS valid after I2S_CLK low (CLKPOL = 1) – – tw(CLKL) + TBD (3) tw(CLKL) + TBD (3) ns 8 9 PRODUCT PREVIEW 10 104 CVDD = 1.3 V (2) 7 (1) (2) (3) CVDD = 1.05 V (2) (2) (2) P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns. Use whichever value is greater. In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK). Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 5-35. Switching Characteristics Over Recommended Operating Conditions for I2S Output [I/O = 3.3 V, 2.8 V, or 2.5 V] (see Figure 5-26) MASTER NO . PARAMETER CVDD = 1.05 V MIN 2 3 4 MIN MAX MIN UN IT MAX 40 or 2P (1) (2) 40 or 2P (1) (2) 40 or 2P (1) (2) ns Pulse duration, I2S_CLK high (CLKPOL = 0) 20 20 20 20 ns Pulse duration, I2S_CLK low (CLKPOL = 1) 20 20 20 20 ns tw(CLKL) Pulse duration, I2S_CLK low (CLKPOL = 0) 20 20 20 20 ns tw(CLKH) Pulse duration, I2S_CLK high (CLKPOL = 1) 20 20 20 20 ns tdmax(CLKL- Output Delay time, I2S_CLK low to I2S_DX valid (CLKPOL = 0) TBD TBD TBD TBD TBD TBD TBD TBD ns Output Delay time, I2S_CLK high to I2S_DX valid (CLKPOL = 1) TBD TBD TBD TBD TBD TBD TBD TBD ns Delay time, I2S_CLK low to I2S_FS valid (CLKPOL = 0) TBD TBD TBD TBD – – ns Delay time, I2S_CLK high to I2S_FS valid (CLKPOL = 1) TBD TBD TBD TBD – – ns Cycle time, I2S_CLK tw(CLKH) tw(CLKL) DXV) tdmax(CLKHtdmax(CLKLFSV) tdmax(CLKHFSV) (1) (2) MAX CVDD = 1.3 V 40 or 2P (1) (2) tc(CLK) DXV) 5 MIN CVDD = 1.05 V P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns. Use whichever value is greater. Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 PRODUCT PREVIEW 1 MAX SLAVE CVDD = 1.3 V 105 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 5-36. Switching Characteristics Over Recommended Operating Conditions for I2S Output [I/O = 1.8 V] (see Figure 5-26) MASTER NO . PARAMETER CVDD = 1.05 V MIN 1 2 3 MIN MAX MIN UN IT MAX 50 or 2P (1) (2) 40 or 2P (1) (2) ns Pulse duration, I2S_CLK high (CLKPOL = 0) 25 20 25 20 ns Pulse duration, I2S_CLK low (CLKPOL = 1) 25 20 25 20 ns tw(CLKL) Pulse duration, I2S_CLK low (CLKPOL = 0) 25 20 25 20 ns tw(CLKH) Pulse duration, I2S_CLK high (CLKPOL = 1) 25 20 25 20 ns tdmax(CLKL- Output Delay time, I2S_CLK low to I2S_DX valid (CLKPOL = 0) TBD TBD TBD TBD TBD TBD TBD TBD ns Output Delay time, I2S_CLK high to I2S_DX valid (CLKPOL = 1) TBD TBD TBD TBD TBD TBD TBD TBD ns Delay time, I2S_CLK low to I2S_FS valid (CLKPOL = 0) TBD TBD TBD TBD – – ns Delay time, I2S_CLK high to I2S_FS valid (CLKPOL = 1) TBD TBD TBD TBD – – ns tw(CLKH) tw(CLKL) DXV) tdmax(CLKLFSV) tdmax(CLKHFSV) PRODUCT PREVIEW (1) (2) MAX CVDD = 1.3 V 40 or 2P (1) (2) Cycle time, I2S_CLK tdmax(CLKH- 5 MIN CVDD = 1.05 V 50 or 2P (1) (2) tc(CLK) DXV) 4 MAX SLAVE CVDD = 1.3 V P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns. Use whichever value is greater. 1 2 3 I2S_CLK (CLKPOL = 0) I2S_CLK (CLKPOL = 1) 5 I2S_FS (Output, MODE = 1) 8 9 I2S_FS (Input, MODE = 0) 4 I2S_DX 6 7 I2S_RX Figure 5-26. I2S Input and Output Timings 106 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 5.15 Serial Port Interface (SPI) The C5504 serial port interface (SPI) is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (1 to 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI supports multi-chip operation of up to four SPI slave devices. The SPI can operate as a master device only, slave mode is not supported. The SPI is normally used for communication between the DSP and external peripherals. Typical applications include an interface to external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EEPROMs, and analog-to-digital converters. PRODUCT PREVIEW The SPI has the following features: • Programmable divider for serial data clock generation • Four pin interface (SPI_CLK, SPI_CSn, SPI_RX, and SPI_TX) • Programmable data length (1 to 32 bits) • 4 external chip select signals • Programmable transfer or frame size (1 to 4096 characters) • Optional interrupt generation on character completion • Programmable SPI_CSn to SPI_TX delay from 0 to 3 SPI_CLK cycles • Programmable signal polarities • Programmable active clock edge • Internal loopback mode for testing 5.15.1 SPI Peripheral Register Description(s) Table 5-37 shows the SPI registers. Table 5-37. SPI Module Registers CPU WORD ADDRESS ACRONYM 3000h SPICDR Clock Divider Register 3001h SPICCR Clock Control Register 3002h SPIDCR1 Device Configuration Register 1 3003h SPIDCR2 Device Configuration Register 2 3004h SPICMD1 Command Register 1 3005h SPICMD2 Command Register 2 3006h SPISTAT1 Status Register 1 3007h SPISTAT2 Status Register 2 3008h SPIDAT1 Data Register 1 3009h SPIDAT2 Data Register 2 Copyright © 2010, Texas Instruments Incorporated REGISTER NAME Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 107 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com 5.15.2 SPI Electrical Data/Timing Table 5-38. Timing Requirements for SPI input (see Figure 5-27 through Figure 5-30) CVDD = 1.05 V NO. MIN 30 19 ns Pulse duration, SPI_CLK low 30 19 ns Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 0 16.5 11 ns Setup time, SPI_RX valid before SPI_CLK low, SPI Mode 1 16.5 11 ns Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 2 16.5 11 ns Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 3 16.5 11 ns Hold time, SPI_RX vaild after SPI_CLK high, SPI Mode 0 0 0 ns Hold time, SPI_RX vaild after SPI_CLK low, SPI Mode 1 0 0 ns Hold time, SPI_RX vaild after SPI_CLK low, SPI Mode 2 0 0 ns Hold time, SPI_RX vaild after SPI_CLK high, SPI Mode 3 0 0 ns tw(SCLKH) 7 tw(SCLKL) PRODUCT PREVIEW (1) (2) UNIT Pulse duration, SPI_CLK high 6 th(SCLK-SRXV) MAX ns Cycle time, SPI_CLK 9 MIN 40 or 4P (1) (2) tC(SCLK) tsu(SRXV-SCLK) MAX 66.4 or 4P (1) (2) 5 8 CVDD = 1.3 V P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns. Use whichever value is greater. Table 5-39. Switching Characteristics Over Recommended Operating Conditions for SPI Outputs (see Figure 5-27 through Figure 5-30) NO. 1 2 3 (1) CVDD = 1.05 V PARAMETER td(SCLK-STXV) CVDD = 1.3 V UNIT MIN MAX MIN MAX Delay time, SPI_CLK low to SPI_TX vaild, SPI Mode 0 -5 9 -5 5.5 ns Delay time, SPI_CLK high to SPI_TX vaild, SPI Mode 1 -5 9 -5 5.5 ns Delay time, SPI_CLK high to SPI_TX vaild, SPI Mode 2 -5 9 -5 5.5 ns Delay time, SPI_CLK low to SPI_TX vaild, SPI Mode 3 -5 9 -5 5.5 ns tC - 8 + D (1) ns td(SPICS-SCLK) Delay time, SPI_CS active to SPI_CLK active toh(SCLKI-SPICSI) Output hold time, SPI_CS inactive to SPI_CLK inactive tC - 8 + D (1) 0.5tC - 2.5 0.5tC - 2.5 ns D is the programable data delay in ns. Data delay can be programmed to 0, 1, 2, or 3 SPICLK clock cycles. 4 6 5 SPI_CLK 1 SPI_TX B0 SPI_RX B1 B0 2 B1 7 Bn-2 Bn-1 Bn-2 Bn-1 8 3 SPI_CS A. B. Character length is programmable between 1 and 32 bits; 8-bit character length shown. Polarity of SPI_CSn is configurable, active-low polarity is shown. Figure 5-27. SPI Mode 0 Transfer (CKPn = 0, CKPHn = 0) 108 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 4 6 5 SPI_CLK 1 B0 SPI_TX B1 SPI_RX 7 2 B1 Bn-2 Bn-1 B1 Bn-2 Bn-1 8 3 SPI_CS A. B. Character length is programmable between 1 and 32 bits; 8-bit character length shown. Polarity of SPI_CSn is configurable, active-low polarity is shown. Figure 5-28. SPI Mode 1 Transfer (CKPn = 0, CKPHn = 1) 4 5 6 SPI_CLK 1 B0 B1 SPI_RX B0 B1 Bn-2 Bn-1 Bn-2 7 2 Bn-1 3 8 PRODUCT PREVIEW SPI_TX SPI_CS A. B. Character length is programmable between 1 and 32 bits; 8-bit character length shown. Polarity of SPI_CSn is configurable, active-low polarity is shown. Figure 5-29. SPI Mode 2 Transfer (CKPn = 1, CKPHn = 0) 4 5 6 SPI_CLK 1 B0 SPI_TX B0 SPI_RX SPI_CS A. B. 2 7 B1 Bn-2 Bn-1 B1 Bn-2 Bn-1 8 3 Character length is programmable between 1 and 32 bits; 8-bit character length shown. Polarity of SPI_CSn is configurable, active-low polarity is shown. Figure 5-30. SPI Mode 3 Transfer (CKPn = 1, CKPHn = 1) Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 109 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com 5.16 Universal Serial Bus (USB) 2.0 Controller The C5504 USB2.0 peripheral supports the following features: • USB 2.0 peripheral at speeds high-speed (480 Mb/s) and full-speed (12 Mb/s) • All transfer modes (control, bulk, interrupt, and isochronous asynchronous mode) • 4 Transmit (TX) and 4 Receive (RX) Endpoints in addition to Control Endpoint 0 • FIFO RAM – 4K endpoint – Programmable size • Integrated USB 2.0 High Speed PHY • RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB The USB2.0 peripheral on this device, does not support: • Host Mode (Peripheral/Device Modes supported only) • On-Chip Charge Pump • On-the-Go (OTG) Mode PRODUCT PREVIEW 110 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 5.16.1 USB2.0 Peripheral Register Description(s) Table 5-40 lists of the USB2.0 peripheral registers. Table 5-40. Universal Serial Bus (USB) Registers (1) CPU WORD ADDRESS ACRONYM 8000h REVID1 Revision Identification Register 1 8001h REVID2 Revision Identification Register 2 8004h CTRLR Control Register REGISTER DESCRIPTION 8008h STATR Status Register 800Ch EMUR Emulation Register 8010h MODER1 Mode Register 1 8011h MODER2 Mode Register 2 AUTOREQ 8018h SRPFIXTIME1 Auto Request Register SRP Fix Time Register 1 8019h SRPFIXTIME2 SRP Fix Time Register 2 801Ch TEARDOWN1 Teardown Register 1 801Dh TEARDOWN2 Teardown Register 2 8020h INTSRCR1 USB Interrupt Source Register 1 8021h INTSRCR2 USB Interrupt Source Register 2 8024h INTSETR1 USB Interrupt Source Set Register 1 8025h INTSETR2 USB Interrupt Source Set Register 2 8028h INTCLRR1 USB Interrupt Source Clear Register 1 8029h INTCLRR2 USB Interrupt Source Clear Register 2 802Ch INTMSKR1 USB Interrupt Mask Register 1 802Dh INTMSKR2 USB Interrupt Mask Register 2 8030h INTMSKSETR1 USB Interrupt Mask Set Register 1 8031h INTMSKSETR2 USB Interrupt Mask Set Register 2 8034h INTMSKCLRR1 USB Interrupt Mask Clear Register 1 8035h INTMSKCLRR2 USB Interrupt Mask Clear Register 2 8038h INTMASKEDR1 USB Interrupt Source Masked Register 1 8039h INTMASKEDR2 USB Interrupt Source Masked Register 2 803Ch EOIR 8040h INTVECTR1 USB Interrupt Vector Register 1 8041h INTVECTR2 USB Interrupt Vector Register 2 8050h GREP1SZR1 Generic RNDIS EP1Size Register 1 8051h GREP1SZR2 Generic RNDIS EP1Size Register 2 8054h GREP2SZR1 Generic RNDIS EP2 Size Register 1 8055h GREP2SZR2 Generic RNDIS EP2 Size Register 2 8058h GREP3SZR1 Generic RNDIS EP3 Size Register 1 8059h GREP3SZR2 Generic RNDIS EP3 Size Register 2 805Ch GREP4SZR1 Generic RNDIS EP4 Size Register 1 805Dh GREP4SZR2 Generic RNDIS EP4 Size Register 2 8401h FADDR_POWER 8402h INTRTX Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4 8405h INTRRX Interrupt Register for Receive Endpoints 1 to 4 8406h INTRTXE Interrupt enable register for INTRTX PRODUCT PREVIEW 8014h USB End of Interrupt Register Common USB Registers (1) Function Address Register, Power Management Register Before reading or writing to the USB registers, be sure to set the BYTEMODE bits to "00b" in the USB system control register to enable word accesses to the USB registers . Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 111 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 5-40. Universal Serial Bus (USB) Registers CPU WORD ADDRESS ACRONYM (continued) REGISTER DESCRIPTION 8409h INTRRXE 840Ah INTRUSB_INTRUSBE 840Dh FRAME 840Eh (1) Interrupt Enable Register for INTRRX Interrupt Register for Common USB Interrupts, Interrupt Enable Register Frame Number Register Index Register for Selecting the Endpoint Status and Control Registers, Register to Enable the USB 2.0 Test Modes INDEX_TESTMODE USB Indexed Registers 8411h 8412h Maximum Packet Size for Peripheral/Host Transmit Endpoint. (Index register set to select Endpoints 1-4) TXMAXP_INDX Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to select Endpoint 0) PERI_CSR0_INDX PERI_TXCSR_INDX 8415h 8416h 8419h Control Status Register for Peripheral Transmit Endpoint. (Index register set to select Endpoints 1-4) Maximum Packet Size for Peripheral/Host Receive Endpoint. (Index register set to select Endpoints 1-4) RXMAXP_INDX PRODUCT PREVIEW PERI_RXCSR_INDX Control Status Register for Peripheral Receive Endpoint. (Index register set to select Endpoints 1-4) COUNT0_INDX Number of Received Bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) Number of Bytes in Host Receive Endpoint FIFO. (Index register set to select Endpoints 1- 4) RXCOUNT_INDX 841Ah - Reserved 841Dh - Reserved 841Eh CONFIGDATA_INDC (Upper byte of 841Eh) 8421h FIFO0R1 Transmit and Receive FIFO Register 1 for Endpoint 0 8422h FIFO0R2 Transmit and Receive FIFO Register 2 for Endpoint 0 8425h FIFO1R1 Transmit and Receive FIFO Register 1 for Endpoint 1 8426h FIFO1R2 Transmit and Receive FIFO Register 2 for Endpoint 1 8429h FIFO2R1 Transmit and Receive FIFO Register 1 for Endpoint 2 Returns details of core configuration. (index register set to select Endpoint 0) USB FIFO Registers 842Ah FIFO2R2 Transmit and Receive FIFO Register 2 for Endpoint 2 842Dh FIFO3R1 Transmit and Receive FIFO Register 1 for Endpoint 3 842Eh FIFO3R2 Transmit and Receive FIFO Register 2 for Endpoint 3 8431h FIFO4R1 Transmit and Receive FIFO Register 1 for Endpoint 4 8432h FIFO4R2 Transmit and Receive FIFO Register 2 for Endpoint 4 Dynamic FIFO Control Registers 8461h 8462h - Reserved TXFIFOSZ_RXFIFOSZ Transmit Endpoint FIFO Size, Receive Endpoint FIFO Size (Index register set to select Endpoints 1-4) 8465h TXFIFOADDR Transmit Endpoint FIFO Address (Index register set to select Endpoints 1-4) 8466h RXFIFOADDR Receive Endpoint FIFO Address (Index register set to select Endpoints 1-4) 846Dh - Reserved Control and Status Register for Endpoint 0 112 8501h - Reserved 8502h PERI_CSR0 8505h - Reserved 8506h - Reserved 8509h COUNT0 850Ah - Control Status Register for Peripheral Endpoint 0 Number of Received Bytes in Endpoint 0 FIFO Reserved Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 5-40. Universal Serial Bus (USB) Registers CPU WORD ADDRESS ACRONYM (1) (continued) REGISTER DESCRIPTION 850Dh - 850Eh CONFIGDATA (Upper byte of 850Eh) Reserved 8511h TXMAXP 8512h PERI_TXCSR Returns details of core configuration. Control and Status Register for Endpoint 1 8515h RXMAXP 8516h PERI_RXCSR 8519h RXCOUNT Maximum Packet Size for Peripheral/Host Transmit Endpoint Control Status Register for Peripheral Transmit Endpoint (peripheral mode) Maximum Packet Size for Peripheral/Host Receive Endpoint Control Status Register for Peripheral Receive Endpoint (peripheral mode) Number of Bytes in the Receiving Endpoint's FIFO 851Ah - Reserved 851Dh - Reserved 851Eh - Reserved 8521h TXMAXP 8522h PERI_TXCSR 8525h RXMAXP 8526h PERI_RXCSR 8529h RXCOUNT 852Ah - Reserved 852Dh - Reserved 852Eh - Control and Status Register for Endpoint 2 Maximum Packet Size for Peripheral/Host Transmit Endpoint Control Status Register for Peripheral Transmit Endpoint (peripheral mode) PRODUCT PREVIEW Maximum Packet Size for Peripheral/Host Receive Endpoint Control Status Register for Peripheral Receive Endpoint (peripheral mode) Number of Bytes in Host Receive endpoint FIFO Reserved Control and Status Register for Endpoint 3 8531h TXMAXP 8532h PERI_TXCSR 8535h RXMAXP 8536h PERI_RXCSR Maximum Packet Size for Peripheral/Host Transmit Endpoint Control Status Register for Peripheral Transmit Endpoint (peripheral mode) Maximum Packet Size for Peripheral/Host Receive Endpoint Control Status Register for Peripheral Receive Endpoint (peripheral mode) 8539h RXCOUNT 853Ah - Number of Bytes in Host Receive endpoint FIFO Reserved 853Dh - Reserved 853Eh - Reserved Control and Status Register for Endpoint 4 8541h TXMAXP 8542h PERI_TXCSR 8545h RXMAXP 8546h PERI_RXCSR 8549h RXCOUNT Maximum Packet Size for Peripheral/Host Transmit Endpoint Control Status Register for Peripheral Transmit Endpoint (peripheral mode) Maximum Packet Size for Peripheral/Host Receive Endpoint Control Status Register for Peripheral Receive Endpoint (peripheral mode) Number of Bytes in Host Receive endpoint FIFO 854Ah - Reserved 854Dh - Reserved 854Eh - Reserved 9000h - Reserved 9001h - Reserved CPPI DMA (CMDA) Registers 9004h TDFDQ 9008h DMAEMU 9800h TXGCR1[0] Transmit Channel 0 Global Configuration Register 1 9801h TXGCR2[0] Transmit Channel 0 Global Configuration Register 2 9808h RXGCR1[0] Receive Channel 0 Global Configuration Register 1 Copyright © 2010, Texas Instruments Incorporated CDMA Teardown Free Descriptor Queue Control Register CDMA Emulation Control Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 113 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 5-40. Universal Serial Bus (USB) Registers CPU WORD ADDRESS ACRONYM (1) (continued) REGISTER DESCRIPTION RXGCR2[0] RXHPCR1A[0] Receive Channel 0 Host Packet Configuration Register 1 A 980Dh RXHPCR2A[0] Receive Channel 0 Host Packet Configuration Register 2 A 9810h RXHPCR1B[0] Receive Channel 0 Host Packet Configuration Register 1 B 9811h RXHPCR2B[0] Receive Channel 0 Host Packet Configuration Register 2 B 9820h TXGCR1[1] Transmit Channel 1 Global Configuration Register 1 9821h TXGCR2[1] Transmit Channel 1 Global Configuration Register 2 9828h RXGCR1[1] Receive Channel 1 Global Configuration Register 1 9829h RXGCR2[1] Receive Channel 1 Global Configuration Register 2 982Ch RXHPCR1A[1] Receive Channel 1 Host Packet Configuration Register 1 A 982Dh RXHPCR2A[1] Receive Channel 1 Host Packet Configuration Register 2 A 9830h RXHPCR1B[1] Receive Channel 1 Host Packet Configuration Register 1 B 9831h RXHPCR2B[1] Receive Channel 1 Host Packet Configuration Register 2 B 9840h TXGCR1[2] Transmit Channel 2 Global Configuration Register 1 9841h TXGCR2[2] Transmit Channel 2 Global Configuration Register 2 9848h RXGCR1[2] Receive Channel 2 Global Configuration Register 1 9849h RXGCR2[2] Receive Channel 2 Global Configuration Register 2 984Ch RXHPCR1A[2] Receive Channel 2 Host Packet Configuration Register 1 A 984Dh RXHPCR2A[2] Receive Channel 2 Host Packet Configuration Register 2 A 9850h RXHPCR1B[2] Receive Channel 2 Host Packet Configuration Register 1 B 9851h RXHPCR2B[2] Receive Channel 2 Host Packet Configuration Register 2 B 9860h TXGCR1[3] Transmit Channel 3 Global Configuration Register 1 9861h TXGCR2[3] Transmit Channel 3 Global Configuration Register 2 9868h RXGCR1[3] Receive Channel 3 Global Configuration Register 1 9869h RXGCR2[3] Receive Channel 3 Global Configuration Register 2 986Ch RXHPCR1A[3] Receive Channel 3 Host Packet Configuration Register 1 A 986Dh RXHPCR2A[3] Receive Channel 3 Host Packet Configuration Register 2 A 9870h RXHPCR1B[3] Receive Channel 3 Host Packet Configuration Register 1 B 9871h RXHPCR2B[3] Receive Channel 3 Host Packet Configuration Register 2 B A000h DMA_SCHED_CTRL1 CDMA Scheduler Control Register 1 A001h DMA_SCHED_CTRL2 CDMA Scheduler Control Register 1 A800h + 4 × N ENTRYLSW[N] A801h + 4 × N ENTRYMSW[N] PRODUCT PREVIEW 9809h 980Ch Receive Channel 0 Global Configuration Register 2 CDMA Scheduler Table Word N Registers LSW (N = 0 to 63) CDMA Scheduler Table Word N Registers MSW (N = 0 to 63) Queue Manager (QMGR) Registers C000h 114 - Reserved C001h - Reserved C008h DIVERSION1 Queue Manager Queue Diversion Register 1 C009h DIVERSION2 Queue Manager Queue Diversion Register 2 C020h FDBSC0 Queue Manager Free Descriptor/Buffer Starvation Count Register 0 C021h FDBSC1 Queue Manager Free Descriptor/Buffer Starvation Count Register 1 C024h FDBSC2 Queue Manager Free Descriptor/Buffer Starvation Count Register 2 C025h FDBSC3 Queue Manager Free Descriptor/Buffer Starvation Count Register 3 C028h FDBSC4 Queue Manager Free Descriptor/Buffer Starvation Count Register 4 C029h FDBSC5 Queue Manager Free Descriptor/Buffer Starvation Count Register 5 C02Ch FDBSC6 Queue Manager Free Descriptor/Buffer Starvation Count Register 6 C02Dh FDBSC7 Queue Manager Free Descriptor/Buffer Starvation Count Register 7 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 Table 5-40. Universal Serial Bus (USB) Registers (1) (continued) CPU WORD ADDRESS ACRONYM C080h LRAM0BASE1 Queue Manager Linking RAM Region 0 Base Address Register 1 C081h LRAM0BASE2 Queue Manager Linking RAM Region 0 Base Address Register 2 C084h LRAM0SIZE C085h - C088h LRAM1BASE1 Queue Manager Linking RAM Region 1 Base Address Register 1 C089h LRAM1BASE2 Queue Manager Linking RAM Region 1 Base Address Register 2 C090h PEND0 Queue Manager Queue Pending 0 C091h PEND1 Queue Manager Queue Pending 1 C094h PEND2 Queue Manager Queue Pending 2 C095h PEND3 Queue Manager Queue Pending 3 C098h PEND4 Queue Manager Queue Pending 4 C099h PEND5 Queue Manager Queue Pending 5 D000h + 16 × R QMEMRBASE1[R] Queue Manager Memory Region R Base Address Register 1 (R = 0 to 15) D001h + 16 × R QMEMRBASE2[R] Queue Manager Memory Region R Base Address Register 2 (R = 0 to 15) D004h + 16 × R QMEMRCTRL1[R] Queue Manager Memory Region R Control Register (R = 0 to 15) D005h + 16 × R QMEMRCTRL2[R] Queue Manager Memory Region R Control Register (R = 0 to 15) E000h + 16 × N CTRL1A Queue Manager Queue N Control Register 1A (N = 0 to 63) E001h + 16 × N CTRL2A Queue Manager Queue N Control Register 2A (N = 0 to 63) E004h + 16 × N CTRL1B Queue Manager Queue N Control Register 1B (N = 0 to 63) E005h + 16 × N CTRL2B Queue Manager Queue N Control Register 2B (N = 0 to 63) E008h + 16 × N CTRL1C Queue Manager Queue N Control Register 1C (N = 0 to 63) E009h + 16 × N CTRL2C Queue Manager Queue N Control Register 2C (N = 0 to 63) E00Ch + 16 × N CTRL1D Queue Manager Queue N Control Register 1D (N = 0 to 63) E00Dh + 16 × N CTRL2D Queue Manager Queue N Control Register 2D (N = 0 to 63) E800h + 16 × N QSTAT1A Queue Manager Queue N Status Register 1A (N = 0 to 63) E801h + 16 × N QSTAT2A Queue Manager Queue N Status Register 2A (N = 0 to 63) E804h + 16 × N QSTAT1B Queue Manager Queue N Status Register 1B (N = 0 to 63) E805h + 16 × N QSTAT2B Queue Manager Queue N Status Register 2B (N = 0 to 63) E808h + 16 × N QSTAT1C Queue Manager Queue N Status Register 1C (N = 0 to 63) E809h + 16 × N QSTAT1C Queue Manager Queue N Status Register 2C (N = 0 to 63) Copyright © 2010, Texas Instruments Incorporated REGISTER DESCRIPTION Queue Manager Linking RAM Region 0 Size Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 PRODUCT PREVIEW Reserved 115 TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com 5.16.2 USB2.0 Electrical Data/Timing Table 5-41. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see Figure 5-31) CVDD = 1.05 V CVDD = 1.3 V NO. 1 PARAMETER tr(D) FULL SPEED 12 Mbps Rise time, USB_DP and USB_DM signals (2) (2) HIGH SPEED 480 Mbps (1) MIN MAX MIN 4 20 0.5 UNIT MAX ns 2 tf(D) Fall time, USB_DP and USB_DM signals 4 20 0.5 3 trfM Rise/Fall time, matching (3) 90 111 – – % 4 VCRS Output signal cross-over voltage (2) 1.3 2 – – V 160 175 – – ns (4) PRODUCT PREVIEW 7 tw(EOPT) Pulse duration, EOP transmitter 8 tw(EOPR) Pulse duration, EOP receiver (4) 9 t(DRATE) Data Rate 10 ZDRV Driver Output Resistance 40.5 11 ZINP Receiver Input Impedance 100k (1) (2) (3) (4) 82 ns – 12 49.5 ns 480 Mb/s 40.5 49.5 Ω - - Ω For more detailed informaton, see the Universal Serial Bus Specification, Revision 2.0, Chapter 7. Full Speed and High Speed CL = 50 pF tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.] Must accept as valid EOP USB_DM VCRS USB_DP tper - tjr 90% VOH 10% VOL tr tf Figure 5-31. USB2.0 Integrated Transceiver Interface Timing 116 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 5.17 General-Purpose Timers The C5504 Timers support the following: • 32-bit Programmable Countdown Timer • 13-bit Prescaler Divider • Timer Modes: – 32-bit General-Purpose Timer – 32-bit Watchdog Timer (Timer2 only) • Auto Reload Option • Generates Single Interrupt to CPU (The interrupt is individually latched to determine which timer triggered the interrupt.) • Generates Active Low Pulse to the Hardware Reset (Watchdog only) • Interrupt can be Used for DMA Event 5.17.1 Timers Peripheral Register Description(s) Table 5-42 through Table 5-45 show the Timer and Watchdog registers. Table 5-42. Watchdog Timer Registers (Timer2 only) CPU WORD ADDRESS ACRONYM 1880h WDKCKLK REGISTER DESCRIPTION Watchdog Kick Lock Register 1882h WDKICK Watchdog Kick Register 1884h WDSVLR Watchdog Start Value Lock Register 1886h WDSVR Watchdog Start Value Register Watchdog Enable Lock Register 1888h WDENLOK 188Ah WDEN 188Ch WDPSLR 188Eh WDPS Watchdog Enable Register Watchdog Prescale Lock Register Watchdog Prescale Register Table 5-43. General-Purpose Timer 0 Registers CPU WORD ADDRESS ACRONYM REGISTER DESCRIPTION 1810h TCR Timer 0 Control Register 1812h TIMPRD1 Timer 0 Period Register 1 1813h TIMPRD2 Timer 0 Period Register 2 1814h TIMCNT1 Timer 0 Counter Register 1 1815h TIMCNT2 Timer 0 Counter Register 2 Table 5-44. General-Purpose Timer 1 Registers CPU WORD ADDRESS ACRONYM 1850h TCR Copyright © 2010, Texas Instruments Incorporated REGISTER DESCRIPTION Timer 1 Control Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 117 PRODUCT PREVIEW The C5504 has three 32-bit software programmable Timers. Each timer can be used as a general- purpose (GP) timer. Timer2 can be configured as either a GP or a Watchdog (WD) or both. General-purpose timers are typically used to provide interrupts to the CPU to schedule periodic tasks or a delayed task. A watchdog timer is used to reset the CPU in case it gets into an infinite loop. The GP timers are 32-bit timers with a 13-bit prescaler that can divide the CPU clock and uses this scaled value as a reference clock. These timers can be used to generate periodic interrupts. The Watchdog Timer is a 16-bit counter with a 16-bit prescaler used to provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop. TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 5-44. General-Purpose Timer 1 Registers (continued) CPU WORD ADDRESS ACRONYM 1852h TIMPRD1 Timer 1 Period Register 1 1853h TIMPRD2 Timer 1 Period Register 2 1854h TIMCNT1 Timer 1 Counter Register 1 1855h TIMCNT2 Timer 1 Counter Register 2 REGISTER DESCRIPTION Table 5-45. General-Purpose Timer 2 Registers CPU WPRD ADDRESS ACRONYM 1890h TCR Timer 2 Control Register 1892h TIMPRD1 Timer 2 Period Register 1 1893h TIMPRD2 Timer 2 Period Register 2 1894h TIMCNT1 Timer 2 Counter Register 1 1895h TIMCNT2 Timer 2 Counter Register 2 REGISTER DESCRIPTION PRODUCT PREVIEW 118 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 5.18 General-Purpose Input/Output The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, you can write to an internal register to control the state driven on the output pin. When configured as an input, you can detect the state of the input by reading the state of the internal register. The GPIO can also be used to send interrupts to the CPU. The C5504 GPIO peripheral supports the following: • Up to 26 GPIOs plus 1 general-purpose output (XF) • The 26 GPIO pins have internal pulldowns (IPDs) which can be individually disabled • The 26 GPIOs can be configured to generate edge detected interrupts to the CPU on either the rising or falling edge PRODUCT PREVIEW C5504 GPIO pin functions are multiplexed with various other signals. For more detailed information on what signals are multiplexed with the GPIO and how to configure them, see Section 2.5, Terminal Functions and Section 3, Device Configuration of this document. Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 119 TMS320C5504 SPRS659 – JANUARY 2010 5.18.1 www.ti.com General-Purpose Input/Output Peripheral Register Description(s) The external parallel port interface includes a 16-bit general purpose I/O that can be individually programmed as input or output with interrupt capability. Control of the general purpose I/O is maintained through a set of I/O memory-mapped registers shown in Table 5-46. Table 5-46. GPIO Registers HEX ADDRESS RANGE ACRONYM 1C06h IODIR1 GPIO Direction Register 1 1C07h IODIR2 GPIO Direction Register 2 1C08h IOINDATA1 GPIO Data In Register 1 GPIO Data In Register 2 PRODUCT PREVIEW 120 REGISTER NAME 1C09h IOINDATA2 1C0Ah IODATAOUT1 GPIO Data Out Register 1 1C0Bh IODATAOUT2 GPIO Data Out Register 2 1C0Ch IOINTEDG1 GPIO Interrupt Edge Trigger Enable Register 1 1C0Dh IOINTEDG2 GPIO Interrupt Edge Trigger Enable Register 2 1C0Eh IOINTEN1 GPIO Interrupt Enable Register 1 1C0Fh IOINTEN2 GPIO Interrupt Enable Register 2 1C10h IOINTFLG1 GPIO Interrupt Flag Register 1 1C11h IOINTFLG2 GPIO Interrupt Flag Register 2 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com 5.18.2 SPRS659 – JANUARY 2010 GPIO Peripheral Input/Output Electrical Data/Timing Table 5-47. Timing Requirements for GPIO Inputs (1) (see Figure 5-32) CVDD = 1.05 V CVDD = 1.3 V NO. MIN 1 tw(ACTIVE) 2 (1) (2) tw(INACTIVE) 2C (1) Pulse duration, GPIO input/external interrupt pulse active Pulse duration, GPIO input/external interrupt pulse inactive C UNIT MAX (2) ns (1) (2) ns The pulse width given is sufficient to get latched into the GPIO_IFR register and to generate an interrupt. However, if a user wants to have the device recognize the GPIO changes through software polling of the GPIO Data In (GPIO_DIN) register, the GPIO duration must be extended to allow the device enough time to access the GPIO register through the internal bus. C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns. Table 5-48. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see Figure 5-32) CVDD = 1.05 V CVDD = 1.3 V PARAMETER MIN (1) (2) UNIT MAX 3 tw(GPOH) Pulse duration, GP[x] output high 3C (1) (2) ns 4 tw(GPOL) Pulse duration, GP[x] output low 3C (1) (2) ns This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO is dependent upon internal bus activity. C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns. 2 GP[x] Input (With IOINTEDGy = 0) 1 2 GP[x] Input (With IOINTEDGy = 1) 1 4 3 GP[x] Output Figure 5-32. GPIO Port Timing Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 121 PRODUCT PREVIEW NO. TMS320C5504 SPRS659 – JANUARY 2010 5.18.3 www.ti.com GPIO Peripheral Input Latency Electrical Data/Timing Table 5-49. Timing Requirements for GPIO Input Latency (1) CVDD = 1.05 V CVDD = 1.3 V NO . 1 (1) MIN tL(GPI) Latency, GP[x] input UNIT MAX Polling GPIO_DIN register 5 cyc Polling GPIO_IFR register 7 cyc Interrupt Detection 8 cyc The pulse width given is sufficient to generate a CPU interrupt. However, if a user wants to have C5504 recognize the GP[x] input changes through software polling of the GPIO register, the GP[x] input duration must be extended to allow device enough time to access the GPIO register through the internal bus. PRODUCT PREVIEW 122 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 5.19 IEEE 1149.1 JTAG The JTAG interface is used for Boundary-Scan testing and emulation of the C5504 device. TRST should only to be deasserted when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. The C5504 includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the device's internal emulation logic will always be properly initialized. It is also recommended that an external pulldown be added to ensure proper device operation when an emulation or boundary scan JTAG controller is not connected to the JTAG pins. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations. The C5504 device will not operate properly if TRST is not asserted low during powerup. 5.19.1 JTAG ID (JTAGID) Register Description(s) HEX ADDRESS RANGE ACRONYM N/A JTAGID REGISTER NAME JTAG Identification Register COMMENTS Read-only. Provides 32-bit JTAG ID of the device. The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. The register hex value for C5504 is: 0x01B8F E02F. For the actual register bit names and their associated bit field descriptions, see Figure 5-33 and Table 5-51. 31-28 27-12 11-1 0 VARIANT (4-Bit) PART NUMBER (16-Bit) MANUFACTURER (11-Bit) LSB R-0001 R-1011 1000 1111 1110 R-0000 0010 111 R-1 LEGEND: R = Read, W = Write, n = value at reset Figure 5-33. JTAG ID Register Description - C5504 Register Value - 0x01B8F E02F Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 123 PRODUCT PREVIEW Table 5-50. JTAG ID Register TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com Table 5-51. JTAG ID Register Selection Bit Descriptions BIT NAME 31:28 VARIANT DESCRIPTION 27:12 PART NUMBER 11-1 MANUFACTURER 0 LSB Variant (4-Bit) value. C5504 value: 0001. Part Number (16-Bit) value. C5504 value: 1011 1000 1111 1110. Manufacturer (11-Bit) value. C5504 value: 0000 0010 111. LSB. This bit is read as a "1" for C5504 . 5.19.2 JTAG Test_port Electrical Data/Timing Table 5-52. Timing Requirements for JTAG Test Port (see Figure 5-34) CVDD = 1.05 V CVDD = 1.3 V NO. MIN UNIT MAX PRODUCT PREVIEW 2 tc(TCK) Cycle time, TCK 60 ns 3 tw(TCKH) Pulse duration, TCK high 24 ns 4 tw(TCKL) Pulse duration, TCK low 24 ns 5 tsu(TDIV-TCKH) Setup time, TDI valid before TCK high 10 ns 6 tsu(TMSV-TCKH) Setup time, TMS valid before TCK high 6 ns 7 th(TCKH-TDIV) Hold time, TDI valid after TCK high 5 ns 8 th(TCKH-TDIV) Hold time, TMS valid after TCK high 4 ns Table 5-53. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see Figure 5-34) NO. CVDD = 1.05 V CVDD = 1.3 V PARAMETER MIN 1 td(TCKL-TDOV) Delay time, TCK low to TDO valid UNIT MAX 30.5 ns 2 3 4 TCK 1 1 TDO 7 5 TDI 8 6 TMS Figure 5-34. JTAG Test-Port Timing 124 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C5504 Copyright © 2010, Texas Instruments Incorporated TMS320C5504 www.ti.com SPRS659 – JANUARY 2010 6 Mechanical Packaging and Orderable Information The following table(s) show the thermal resistance characteristics for the PBGA–ZCH mechanical package. 6.1 Thermal Data for ZCH Table 6-1. Thermal Resistance Characteristics (PBGA Package) [ZCH] ＝C/W (1) AIR FLOW (m/s) (2) 1S0P 6.74 N/A 1S0P 14.5 N/A 2S2P 13.8 1S0P 57.0 2S2P 33.4 NO. 1 2 3 RΘJC Junction-to-case RΘJB Junction-to-board RΘJA Junction-to-free air 4 0.00 0.50 5 RΘJMA 6 1.00 Junction-to-moving air 2.00 3.00 8 0.09 9 0.00 0.50 10 PsiJT Junction-to-package top 1.00 11 2.00 12 3.00 13 13.7 14 15 0.00 0.50 PsiJB Junction-to-board 1.00 16 2.00 17 3.00 (1) (2) 6.2 These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. m/s = meters per second Packaging Information The following packaging information and addendum reflect the most current data available for the designated device(s). This data is subject to change without notice and without revision of this document. Copyright © 2010, Texas Instruments Incorporated Mechanical Packaging and Orderable Information Submit Documentation Feedback Product Folder Link(s): TMS320C5504 125 PRODUCT PREVIEW 7 PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TMS320C5504AZCH10 ACTIVE NFBGA ZCH 196 184 TBD Call TI Call TI TMS320C5504AZCH12 ACTIVE NFBGA ZCH 196 184 TBD Call TI Call TI TMS320C5504AZCHA10 ACTIVE NFBGA ZCH 196 184 TBD Call TI Call TI TMS320C5504AZCHA12 ACTIVE NFBGA ZCH 196 184 TBD Call TI Call TI TMX320C5504AZCH12 ACTIVE NFBGA ZCH 196 184 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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