LTC1448 Dual 12-Bit Rail-to-Rail Micropower DAC U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1448 is a dual rail-to-rail voltage output, 12-bit digital-to-analog converter (DAC). It includes rail-to-rail output buffer amplifiers and an easy-to-use 3-wire serial interface. It is available in 8-pin SO and PDIP packages and provides the smallest footprint of any dual 12-bit DAC. SO-8 Package 12-Bit Resolution Buffered True Rail-to-Rail Voltage Output External Reference Input Can Be Tied to VCC Output Swings from 0V to VREF 3V and 5V Supply Operation Schmitt Trigger on Clock Input Allows Direct Optocoupler Interface Power-On Reset Clears DACs to 0V 3-Wire Serial Interface Maximum DNL Error: 0.5LSB Low Cost The LTC1448 has an external reference input pin (REF) and its outputs swing from 0V to REF. The REF input can be tied to VCC providing rail-to-rail operation from supplies of 2.7V to 5.5V. (For devices with internal reference see the LTC1446 data sheet.) The LTC1448 dissipates 2.5mW from a 5V supply. The low power supply current and the small SO-8 package make the LTC1448 ideal for battery-powered applications. U APPLICATIONS ■ ■ ■ Digital Calibration Industrial Process Control Automatic Test Equipment Cellular Telephones , LTC and LT are registered trademarks of Linear Technology Corporation. U ■ TYPICAL APPLICATION Functional Block Diagram: 12-Bit Rail-to-Rail Dual DAC Differential Nonlinearity vs Input Code 2.7V TO 5.5V 0.5 7 4 REF VCC 0.4 2 DIN + 12-BIT DAC B µP VOUT B 8 – 1 CLK 3 CS/LD 24-BIT SHIFT REG AND DAC LATCH RAIL-TO-RAIL VOLTAGE OUTPUTS + 12-BIT DAC A DNL ERROR (LSB) 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 VOUT A 5 0 512 1024 1536 2048 2560 3072 3584 4095 CODE 1448 TA02 – POWER-ON RESET GND 6 1448 TA01 1 LTC1448 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER I FOR ATIO VCC to GND .............................................. – 0.5V to 7.5V Logic Inputs to GND ................................ – 0.5V to 7.5V VOUT A, VOUT B, REF to GND ........... – 0.5V to VCC + 0.5V Maximum Junction Temperature .......................... 125°C Operating Temperature Range LTC1448C ............................................ 0°C to 70°C LTC1448I......................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW CLK 1 8 VOUT B DIN 2 7 VCC CS/LD 3 6 GND REF 4 5 VOUT A N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO LTC1448CN8 LTC1448IN8 LTC1448CS8 LTC1448IS8 S8 PART MARKING TJMAX = 125°C, θJA = 100°C/W (N8) TJMAX = 125°C, θJA = 150°C/W (S8) 1448 1448I Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS VCC = 2.7V to 5.5V, VOUT A and VOUT B unloaded, REF ≤ VCC, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DAC Resolution ● 12 Bits Monotonicity ● 12 Bits DNL Differential Nonlinearity VREF ≤ VCC – 0.1V (Note 1) ● INL Integral Nonlinearity VREF ≤ VCC – 0.1V (Note 1), TA = 25°C VREF ≤ VCC – 0.1V (Note 1) Measured at Code 20, TA = 25°C Measured at Code 20 VOS Offset Error VOSTC Offset Error Temperature Coefficient VFS Full-Scale Voltage VFSTC ± 0.2 ± 0.5 LSB ● ± 5.0 ± 5.5 LSB LSB ● ± 10 ± 15 mV mV ±15 VREF = 4.096V, TA = 25°C VREF = 4.096V ● 4.070 4.060 Full-Scale Voltage Temperature Coefficient 4.095 4.095 µV/°C 4.120 4.130 10 V V ppm/°C Power Supply VCC Positive Supply Voltage For Specified Performance ● ICC Supply Current (Note 4) ● Short-Circuit Current Low VOUT Shorted to GND Short-Circuit Current High 2.7 5.5 V 450 700 µA ● 55 120 mA VOUT Shorted to VCC ● 65 120 mA Output Impedance to GND Input Code = 0 ● 30 120 Ω Output Line Regulation Input Code = 4095. VCC = 4.5V to 5.5V, VREF = 4.096V ● 0.2 1.5 LSB/V Op Amp DC Performance 2 LTC1448 ELECTRICAL CHARACTERISTICS VCC = 2.7V to 5.5V, VOUT A and VOUT B unloaded, REF ≤ VCC, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.5 1.0 V/µs 14 µs 0.3 nV • s AC Performance Voltage Output Slew Rate Voltage Output Settling Time ● (Notes 2, 3) to ± 0.5LSB Digital Feedthrough Reference Input RIN REF Input Resistance ● 7.5 REF REF Input Range VIH 12.5 18 kΩ (Notes 5, 6) ● 0 VCC V Digital Input High Voltage VCC = 5V VCC = 3V ● ● 2.4 2.0 VIL Digital Input Low Voltage VCC = 5V VCC = 3V ● ● 0.8 0.6 V V ILEAK Digital Input Leakage VIN = GND to VCC ● ± 10 µA CIN Digital Input Capacitance (Note 6) ● 10 pF Digital I/O V V Switching (VCC = 4.5V to 5.5V) t1 DIN Valid to CLK Setup t2 DIN Valid to CLK Hold ● 0 ns t3 CLK High Time (Note 6) ● 40 ns t4 CLK Low Time (Note 6) ● 40 ns t5 CS/LD Pulse Width (Note 6) ● 50 ns t6 LSB CLK to CS/LD (Note 6) ● 40 ns t7 CS/LD Low to CLK (Note 6) ● 20 ns t8 CLK Low to CS/LD Low (Note 6) ● 20 ns ● 60 ns ● 40 ns Switching (VCC = 2.7V to 5.5V) t1 DIN Valid to CLK Setup t2 DIN Valid to CLK Hold ● 0 ns t3 CLK High Time (Note 6) ● 60 ns t4 CLK Low Time (Note 6) ● 60 ns t5 CS/LD Pulse Width (Note 6) ● 80 ns t6 LSB CLK to CS/LD (Note 6) ● 60 ns t7 CS/LD Low to CLK (Note 6) ● 30 ns t8 CLK Low to CS/LD Low (Note 6) ● 30 ns The ● denotes specifications which apply over the full operating temperature range. Note 1: Nonlinearity is defined from code 20 to code 4095 (full scale). See Applications Information. Note 2: Load is 5k in parallel with 100pF. Note 3: DAC switched between all 1s and the code corresponding to VOS for the part. Note 4: Digital inputs at 0V or VCC. Note 5: VOUT can only swing from (GND + VOS) to (VCC – VOS) when output is unloaded. Note 6. Guaranteed by design, not subject to test. 3 LTC1448 U W TYPICAL PERFORMANCE CHARACTERISTICS Minimum Supply Headroom for Full Output Swing vs Load Current Differential Nonlinearity (DNL) 0.5 4 0.4 3 0.3 2 0.2 1 0 –1 –2 0.8 0.6 0.1 0 –0.1 0.5 0.4 0.3 –0.2 –3 –0.3 –4 –0.4 0.2 0.1 0 –0.5 –5 0 512 1024 1536 2048 2560 3072 3584 4095 CODE ∆VOUT < 1LSB CODE: ALL 1’s VOUT = 4.095V 0.7 VCC – VOUT (V) 5 DNL ERROR (LSB) INL ERROR (LSB) Integral Nonlinearity (INL) 0 512 1024 1536 2048 2560 3072 3584 4095 CODE 0 5 10 LOAD CURRENT (mA) 1448 G03 1448 TA02 1448 G01 Minimum Output Voltage vs Output Sink Current 15 Supply Current vs Logic Input Voltage CODE: ALL 0’s 2.0 700 600 SUPPLY CURRENT (mA) OUTPUT PULL-DOWN VOLTAGE (mV) 800 125°C 500 400 25°C 300 –55°C 200 1.6 1.2 0.8 0.4 100 0 0 0 5 10 OUTPUT SINK CURRENT (mA) 15 0 1 3 4 2 LOGIC INPUT VOLTAGE (V) 5 1448 G06 1448 G04 U U U PIN FUNCTIONS CLK (Pin 1): Serial Interface Clock. Internal Schmitt trigger on this input allows direct optocoupler interface. updating the DAC output and the CLK is disabled internally. DIN (Pin 2): Serial Interface Data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. REF (Pin 4): Reference Input for Both DACs. This pin can be tied to VCC. The output will swing from 0V to REF. The typical input resistance is 12.5k. CS/LD (Pin 3): Serial Interface Enable and Load Control. When CS/LD is low the CLK signal is enabled, so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, VOUT A, VOUT B (Pins 5, 8): Buffered DAC Outputs. 4 GND (Pin 6): Ground. VCC (Pin 7): Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V. Requires a bypass capacitor to ground. LTC1448 W BLOCK DIAGRA 12-BIT DAC B LD + DAC B REGISTER CLK 1 8 VOUT B 7 VCC 6 GND 5 VOUT A – 24-BIT SHIFT REGISTER DIN 2 LD CS/LD 3 DAC A REGISTER REF 4 12-BIT DAC A + – POWER-ON RESET 1448 BD WU W TI I G DIAGRA S OPERATING SEQUENCE DAC A INPUT DAC B INPUT MSB LSB MSB DIN D11 D10 D9 D8 D7 D6 CLK 1 2 3 4 5 6 D5 7 D4 D3 8 9 D2 10 D1 11 D0 12 D11 LSB D10 13 14 D9 15 D8 16 D7 D6 17 18 D5 19 D4 20 D3 21 D2 22 D1 D0 23 24 CS/LD (UPDATE DAC OUTPUT) (ENABLE CLOCK) 1448 TD01 t4 t3 t1 t2 t6 t7 CLK t8 DIN B0-B PREVIOUS WORD B11-A MSB B0-A LSB B11-B MSB B0-B LSB t5 CS/LD 1448 TD02 5 LTC1448 U U DEFI ITIO S Differential Nonlinearity (DNL): The differerence between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (∆VOUT – LSB)/LSB where ∆VOUT is the measured voltage difference between two adjacent codes. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset and gain errors (see Applications Information). Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [VOUT – VOS – (VFS – VOS)(code/4095)]/LSB where VOUT is the output voltage of the DAC measured at the given input code. Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = VREF/4096 Resolution (n): Defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (VOS): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero. U OPERATIO Serial Interface The data on the DIN input is loaded into the shift register on the rising edge of the clock. Data is loaded as one 24bit word where the first 12 bits are for DAC A and the second 12 are for DAC B. For each 12-bit segment the MSB is loaded first. Data from the shift register is loaded into the DAC register when CS/LD is pulled high. The clock is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. Voltage Output The LTC1448’s rail-to-rail buffered outputs can source or sink 5mA over the entire operating temperature range 6 while pulling to within 300mV of the positive supply voltage or ground. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 30Ω when driving a load to the rails. The output can drive 1000pF without going into oscillation. The output swings from 0V to the voltage at the REF pin, i.e., there is a gain of 1 from the REF to VOUT. Please note if REF is tied to VCC the output can only swing to (VCC – VOS). See Applications Information. LTC1448 U W U U APPLICATIONS INFORMATION Rail-to-Rail Output Considerations (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 1c. No full-scale limiting can occur if VREF is less than VCC – FSE. In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 1b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error VREF = VCC POSITIVE FSE OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC OUTPUT VOLTAGE 0 2048 INPUT CODE 4095 (a) OUTPUT VOLTAGE 0V NEGATIVE OFFSET INPUT CODE (b) 1448 F01 Figure 1. Effects of Rail-to-Rail Operation on a DAC Transfer Curve: (a) Overall Transfer Function, (b) Effect of Negative Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC 7 LTC1448 U TYPICAL APPLICATIONS This circuit shows how to use one LTC1448 to make an autoranging ADC. The microprocessor sets the reference span and the Common pin for the analog input by loading the appropriate digital code into the LTC1448. VOUT A controls the Common pin for the analog inputs to the LTC1296 and VOUT B controls the reference span by setting the REF + pin on the LTC1296. The LTC1296 has a Shutdown pin that goes low in shutdown mode. This will turn off the PNP transistor supplying power to the LTC1448. The resistor and capacitor on the LTC1448 outputs act as a lowpass filter for noise. An Autoranging 8-Channel ADC with Shutdown 22µF + 5V VCC CH0 CS DOUT µP CLK 8 ANALOG INPUT CHANNELS LTC1296 DIN CH7 COM SSO REF + REF – 74HC04 50k 50k 5V 0.1µF CLK VOUT B DIN VCC 100Ω 0.1µF CS/LD LTC1448 GND 100Ω REF 1448 TA04 VOUT A 0.1µF 8 LTC1448 U TYPICAL APPLICATIONS Digitally Programmable Current Source 5V 0.1µF CLK µP DIN CS/LD VCC RL REF LTC1448 VS + 6V TO 100V FOR RL ≤ 50Ω VOUT A DIN • 5 ≈ 0mA TO 10mA 4096 • RA + LT1077 GND IOUT = Q1 2N3440 – RA 510Ω 5% VOUT B PIN NOT SHOWN FOR CLARITY 1448 TA05 9 LTC1448 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 6 5 1 2 3 4 0.255 ± 0.015* (6.477 ± 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.065 (1.651) TYP 0.100 ± 0.010 (2.540 ± 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 10 0.130 ± 0.005 (3.302 ± 0.127) 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1197 LTC1448 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO8 0996 11 LTC1448 U TYPICAL APPLICATION 12-Bit, 3V to 5V Supply, Dual Voltage Output DAC 2.7V TO 5.5V 0.1µF DIN VCC µP CLK REF VOUT A OUTPUT A 0V TO REF VOUT B OUTPUT B 0V TO REF CS/LD LTC1448 GND 1448 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1257 Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V 5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package LTC1446/LTC1446L Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1450/LTC1450L Single 12-Bit VOUT DACs with Parallel Interface LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1451 Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin 5V Low Power, Complete VOUT DAC in SO-8 Package LTC1452 Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package LTC1453 Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454/LTC1454L Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1456 Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V Low Power, Complete VOUT DAC in SO-8 Package with Clear Pin LTC1458/LTC1458L Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1659 Single Rail-to-Rail 12-Bit VOUT DAC in MSOP-8 Package, VCC: 2.7V to 5.5V Low Power Multiplying VOUT DAC in MSOP-8 Package. Output Swings from GND to REF. REF Input Can Be Tied to VCC 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417● (408)432-1900 FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com 1448f LT/TP 0398 4K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1997