PRELIMINARY 54LVTH162373 3.3V 16-Bit Transparent D-Type Latches 1OE 1 48 1LE 1Q1 1D1 1Q2 1D2 GND GND 1Q3 1D3 1Q4 1D4 VCC VCC 1Q5 1D5 1Q6 1D6 GND GND 1Q7 1D7 1Q8 1D8 2Q1 2D1 2Q2 54LVTH162373 2D2 GND GND 2Q3 2D3 2Q4 2D4 VCC VCC 2Q5 2D5 Logic Diagram (PositiveLogic) 1OE/2OE 1LE/2LE 1/24 48/25 C1 1D1/2D1 47/36 2D6 GND GND 2Q7 2D7 To Seven Other Channels 2Q8 2D8 Logic Diagram 24 25 1Q1/2Q1 1D 2Q6 2OE 2/13 2LE DESCRIPTION: • 3.3V low voltage advanced BiCMOS technology (LVT) 16bit transparent D-type latches with 3-state outputs • Total dose hardness: - > 100 krad (Si), depending upon space mission • Excellent Single Event Effect: - SELTH: No LU > 119 MeV/mg/cm2 • Package: 48 pin RAD-PAK® flat package • Operating temperature range: - 55 to 125°C • Distributed VCC and GND pin configuration minimizes highspeed switching noise • Supports mixed-mode signal operation - 5V input and output voltages with 3.3V VCC • Supports unregulated battery operation down to 2.7V • Supports live insertion • Bus-hold data inputs eliminate the need for external pullup resistors Maxwell Technologies’ 54LVTH162373 16-bit transparent Dtype latches with 3-state output features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. The 54LVTH162373 is designed for low voltage (3.3V) VCC operation, but with the capability to provide a TTL interface to a 5V system environment. It is suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The 54LVTH162373 can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is low, the Q output are latched at the levels set up at the data (D) inputs. When LE is high, the Q outputs follow the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high impedance state and the increased drive provide the capability to drive bus lines without the need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S. 1000596 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com 12.19.01 Rev 1 All data sheets are subject to change without notice 1 ©2001 Maxwell Technologies All rights reserved. Memory FEATURES: PRELIMINARY 54LVTH162373 3.3V 16-Bit Transparent D-Type TABLE 1. PINOUT DESCRIPTION PIN SYMBOL DESCRIPTION 1, 24 1OE-2OE Output Enable 2, 3, 5, 6, 8, 9, 11, 12 1Q1-1Q8 Outputs 4, 10, 15, 21, 28, 34, 39, 45 GND Ground 7, 31, 42 VCC Power Supply 13, 14, 16, 17, 19, 20, 22, 23 2Q1-2Q8 Outputs 25, 48 2LE-1LE Latch Enable 26, 27, 29, 30, 32, 31, 32, 33, 35, 36 2D8-2D1 Inputs 37, 38, 40, 41, 43, 44, 46, 47 1D8-1D1 Inputs PARAMETER SYMBOL MIN MAX UNIT VCC -0.5 4.6 V VI -0.5 7 V Voltage range applied to any output in the high state or power-off state 1 VO -0.5 7 V Current into any output in the low state IO -- 30 mA IO -- 30 mA IIK -- -50 mA IOK -- -50 mA PD -- 0.85 mW TS -65 150 °C Supply voltage range Input voltage range 1 Current into any output in the high state 2 Input clamp current (VI < 0) Output clamp current (VO < O) Maximum power dissipation at TA = 55°C 3 Storage temperature range Memory TABLE 2. 54LVTH162373 ABSOLUTE MAXIMUM RATINGS 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150 °C and a board trace length of 750 mils. TABLE 3. DELTA LIMITS 1000596 PARAMETER VARIATION ICC(OL) ±10% of specified value in Table 5 ICC(OH) ±10% of specified value in Table 5 ICC(OD) ±10% of specified value in Table 5 12.19.01 Rev 1 All data sheets are subject to change without notice 2 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 54LVTH162373 3.3V 16-Bit Transparent D-Type TABLE 4. 54LVTH162373 RECOMMENDED OPERATING CONDITIONS 1 SYMBOL MIN MAX UNIT Supply voltage VCC 2.7 3.6 V High-level input voltage VIH 2 -- V Low-level input voltage VIL -- 0.8 V Input voltage VI -- 5.5 V High-level output current IOH -- -12 mA Low-level output current IOL -- 12 mA ∆t/∆v -- 10 ns/V TA -55 125 °C PARAMETER Input transition rise or fall rate (outputs enabled) Operating temperature 1. Unused control inputs must be held high or low to prevent them from floating. Memory TABLE 5. 54LVTH162373 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, TA = -55 to 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT Input Clamp Voltage VIK VCC = 2.7 II = -18mA -- -1.2 V High-Level Output Voltage VOH VCC = 3V IOH = -12 mA 2 -- V Low-Level Output Voltage VOL VCC = 3V IOL = 12 mA -- 0.8 V VI = 5.5V -- 10 µA Input Current II VCC = 0 or 3.6V VCC = 3.6V VI = VCC or GND Control inputs -- ±1 VCC = 3.6V VI = VCC Data Inputs -- 1 -- -5 75 -- -75 -- VI = 0 Hold Current II(HOLD) VCC = 3V VI = 0.8V VI = 2V Data Inputs µA Output Disabled Leakage Current - High IOZH VCC = 3.6V, VO = 3V -- 5 µA Output Disabled Leakage Current - Low IOZL VCC = 3.6V, VO = 0.5V -- -5 µA Power Up Current IOZPU2 VCC = 0 to 1.5V, VO = 0.5V to 3V, OE = don’t care -- ±100 µA Power Down Current IOZPD2 VCC = 1.5V to 0, VO = 0.5V to 3V, OE = don’t care -- ±100 µA 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 3 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 54LVTH162373 3.3V 16-Bit Transparent D-Type TABLE 5. 54LVTH162373 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, TA = -55 to 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL Supply Current MIN MAX UNIT Outputs high -- 0.19 mA Outputs low -- 5 Outputs disabled -- 0.19 ∆ICC 1 VCC = 3V to 3.6V, One input at VCC -0.6V, Other inputs -- 0.2 mA ICC Delta Supply Current TEST CONDITIONS VCC = 3.6V IO = 0 VI = VCC or GND at VCC or GND Input Capacitance C I2 VI = 3V or 0 -- 8 pF Input Output Capacitance CO2 VO = 3V or 0 -- 15 pF 1. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 2. Guaranteed by design. Memory TABLE 6. 54LVTH162373 AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, TA = -55 to 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL VCC = 3.3V ± 0.3V VCC = 2.7V UNIT MIN MAX MIN MAX Pulse duration, LE high tW 3.3 -- 3.0 -- ns Setup time, data before LEØ tSU 1.5 -- 0.6 -- ns Hold time, data after LEØ tH 1.8 -- 2 -- ns Propagation Delay Time D to Q tPLH 1.3 5.2 -- 6.0 ns tPHL 1.4 4.9 -- 5.0 tPLH 2.1 6.0 -- 6.5 tPHL 2.1 5.2 -- 4.9 Output Enable Time OE to Q tPZH 1.3 8.0 -- 7.4 tPZL 1.3 5.5 -- 6.2 Output Disable Time OE to Q tPHZ 2.0 6.8 -- 6.9 tPLZ 1.0 7.6 -- 6.7 Propagation Delay Time LE to Q 1000596 12.19.01 Rev 1 ns ns ns All data sheets are subject to change without notice 4 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 54LVTH162373 3.3V 16-Bit Transparent D-Type fp TABLE 7. FUNCTION TABLE (EACH 8-BIT SECTION) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z FIGURE 1. LOAD CIRCUIT Memory Figure Note: 1. CL includes probe and jig capacitance. PARAMETER MEASUREMENT INFORMATION TEST S1 tPLH/tPHL OPEN tPLZ/tPZL 6V tPHZ/tPZH GND FIGURE 2. PULSE DURATION 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 5 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 54LVTH162373 3.3V 16-Bit Transparent D-Type FIGURE 3. SETUP AND HOLD TIMES FIGURE 4. PROPAGATION DELAY TIMES INVERTING AND NON-INVERTING OUTPUTS Memory FIGURE 5. ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 6 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 54LVTH162373 3.3V 16-Bit Transparent D-Type Figure Notes: 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, ZO = 5Ω, tr < 2.5 ns, tf < 2.5 ns. 4. The outputs are measured one at a time with one transition per measurement. Memory 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 7 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 54LVTH162373 3.3V 16-Bit Transparent D-Type Memory 48 PIN RAD-PAK® FLAT PACKAGE SYMBOL DIMENSION MIN NOM MAX A 0.144 0.160 0.176 b 0.008 0.010 0.014 c 0.004 0.006 0.007 D -- 0.620 0.640 E 0.370 0.380 0.390 E1 -- -- 0.410 E2 0.200 0.210 0.220 E3 0.075 0.085 -- e 0.025 BSC L 0.275 0.285 0.295 Q 0.013 0.019 0.045 S1 0.005 0.018 -- N 48 F48-01 Note: All dimensions in inches 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 8 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V 16-Bit Transparent D-Type 54LVTH162373 Important Notice: These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 9 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 54LVTH162373 3.3V 16-Bit Transparent D-Type Product Ordering Options Model Number 54LVTH162373 F X Option Details Feature Screening Flow Monolithic S = Maxwell Class S B = Maxwell Class B E = Engineering (testing @ +25°C) I = Industrial (testing @ -55°C, +25°C, +125°C) Package F = Flat Pack Radiation Feature RP = RAD-PAK® package Base Product Nomenclature 3.3V 16-Bit Transparent D-Type Latches 12.19.01 Rev 1 All data sheets are subject to change without notice Memory 1000596 RP 10 ©2001 Maxwell Technologies All rights reserved.