MX23L6422 3.3 Volt 64M-BIT (4M x 16 / 2M x 32) Mask ROM with Page Mode ORDER INFORMATION FEATURES • Bit organization - 4M x 16 (byte mode) - 2M x 32 (double word mode) • Fast access time - Random access: 110ns (max.) for 3.15~3.6V 120ns (max.) for 3.0~3.6V - Page access: 30ns (max.) • Page Size - 8 double words per page • Current - Operating: 60mA (max.) - Standby: 20uA (max.) • Supply voltage - 3.3V±10% • Package - 70 pin SSOP - 86 pin TSOP(2) Part No. Access Page Access Package Time Time MX23L6422MC-11 110ns 30ns 70 pin SSOP MX23L6422MC-12 120ns 50ns 70 pin SSOP MX23L6422YC-12 50ns 86 pin TSOP 120ns PIN CONFIGURATION 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 MX23L6422 A0 A1 A2 A3 A4 A5 VCC D0 D16 D1 D17 VSS VCC D2 D18 D3 D19 D4 D20 D5 D21 VSS VCC D6 D22 D7 D23 VSS A6 A7 A8 A9 A10 A11 A12 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 NC A0 A1 A2 A3 A4 A5 NC NC VCC D0 D16 D1 D17 VSS VCC D2 D18 D3 D19 NC NC D4 D20 D5 D21 VSS VCC D6 D22 D7 D23 VSS A6 A7 A8 A9 A10 A11 A12 A13 NC NC NC NC A20 WORD OE CE VSS D31/A-1 D15 D30 D14 VSS VCC D29 D13 D28 D12 D27 D11 D26 D10 VSS VCC D25 D9 D24 D8 VCC A19 A18 A17 A16 A15 A14 A13 P/N:PM0410 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 MX23L6422 86 TSOP(2) 70 SSOP 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 NC NC NC NC A20 WORD OE CE NC VSS NC D31/A-1 D15 D30 D14 VSS VCC D29 D13 D28 D12 NC D27 D11 D26 D10 VSS VCC D25 D9 D24 D8 VCC A19 A18 A17 A16 A15 A14 NC NC NC NC REV. 2.7, OCT. 19, 2001 1 MX23L6422 PIN DESCRIPTION Symbol Pin Function A0~A20 Address Inputs D0~D30 Data Outputs D31/A-1 D31 (Double Word Mode)/ LSB Address (Word Mode) CE Chip Enable Input OE Output Enable Input WORD Double Word/ Word Mode Selection VCC Power Supply Pin VSS Ground Pin NC No Connection MODE SELECTION CE OE WORD D31/A-1 D0~D15 D16~D31 Mode Power H X X X High Z High Z - Stand-by L H X X High Z High Z - Active L L H Output D0~D15 D16~D31 Double Word Active L L L Input D0~D15 High Z Word Active BLOCK DIAGRAM A0/(A-1) A2 A3 Address Buffer Memory Array Page Decoder Page Buffer A20 Double Word/ Word Output Buffer D0 D31/(D15) CE WORD OE P/N:PM0410 REV. 2.7, OCT. 19, 2001 2 MX23L6422 ABSOLUTE MAXIMUM RATINGS Item Voltage on any Pin Relative to VSS Ambient Operating Temperature Storage Temperature Symbol VIN Topr Tstg Ratings -1.3V to 4.1V 0°C to 70°C -65°C to 125°C Note: Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to 1.3V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC+0.5V. During voltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns. DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%) Item Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Operating Current Symbol VOH VOL VIH VIL ILI ILO ICC1 MIN. 2.4V 2.2V -0.3V - MAX. 0.4V VCC+0.3V 0.8V 10uA 10uA 60mA Standby Current (TTL) Standby Current (CMOS) Input Capacitance Output Capacitance ISTB1 ISTB2 CIN COUT - 1mA 20uA 10pF 10pF Conditions IOH = -0.4mA IOL = 1.6mA 0V, VCC 0V, VCC tRC = 110ns, all output open, with normal sequential access testing pattern CE = VIH CE>VCC-0.2V Ta = 25°C, f = 1MHZ Ta = 25°C, f = 1MHZ AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%) Item Symbol Read Cycle Time Address Access Time Chip Enable Access Time Page Mode Access Time Output Enable Time Output Hold After Address Output High Z Delay tRC tAA tACE tPA tOE tOH tHZ 23L6422-11* MIN. MAX. 110ns 100ns 110ns 30ns 30ns 0ns 20ns 23L6422-12 MIN. MAX. 120ns 120ns 120ns 50ns 50ns 0ns 20ns Note: Output high-impedance delay (tHZ) is measured from OE or CE going high, and this parameter guaranteed by design over the full voltage and temperature operating range - not tested. * 110ns for 3.15~3.6V P/N:PM0410 REV. 2.7, OCT. 19, 2001 3 MX23L6422 AC Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Level Output Timing Level Output Load 0.4V~ 2.4V 10ns 1.4V 1.4V See Figure IOH (load)=-0.4mA DOUT IOL (load)=1.6mA C<100pF Note:No output loading is present in tester load board. Active loading is used and under software programming control. Output loading capacitance includes load board's and all stray capacitance. TIMING DIAGRAM RANDOM READ ADD ADD ADD ADD tRC tACE CE tOE OE tOH tAA VALID DATA VALID tHZ VALID PAGE READ VALID ADD A3-A20 (A-1),A0,A1,A2 2'nd ADD 1'st ADD tAA DATA 3'rd ADD tPA VALID VALID VALID Note: CE, OE are enable. Page size is 8 double words in 32-bit mode, 16 words in 16-bit mode. P/N:PM0410 REV. 2.7, OCT. 19, 2001 4 MX23L6422 REVISION HISTORY REVISION 2.1 2.2 2.3 2.4 2.5 2.6 2.7 DESCRIPTION AC CHARACTERISTICS tOH 10ns-->0ns Add new 86pin TSOP(2) package Add 100ns speed grade Delete 115ns speed grade Change 100ns speed grade to 110ns Add 110ns(max.) for 3.15~3.6V ; 120ns(max.) for 3.0~3.6V Modify Operating Current : 40mA-->60mA Modify Pin Configuration--100 TQFP D31-->D31/A-1; 86 TSOP NC-->D31/A-1 Delete package:100 pin TQFP P/N:PM0410 PAGE P4 P1 P1,2 P4 P4 P1 P1,3 P2 DATE JAN/29/1999 APR/09/1999 SEP/14/1999 DEC/29/1999 JAN/13/2000 DEC/26/2000 P1,2 OCT/19/2001 REV. 2.7, OCT. 19, 2001 5 MX23L6422 MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-6688 FAX:+886-3-563-2888 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 6