MITEL MT8924

MT8924

PCM Conference Circuit (PCC)
Preliminary Information
Features
ISSUE 1
•
Supports up to 10 independent conferences for
up to 32 PCM Voice Channels
•
ST-BUS compatible 2.048 Mb/s PCM Serial
Interface (also supports 1.536 Mb/s and 1.544
Mb/s data rates)
•
Per channel digital gain control (0/-3/-6 dB)
•
Parallel microprocessor port for device control
•
Programmable noise suppression
•
External Tone Input
•
Pin selectable A/µ-Law format
•
Low power CMOS technology
•
Available in 24 Pin PDIP and SOIC packages
Ordering Information
MT8924AE
24 Pin Plastic DIP
MT8924AS
24 Pin SOIC
°
0 C to +70 °C
Description
The MT8924 is designed to provide conference call
capability in digital switching systems. It allows up to
10 independent conferences to be set for up to 32
PCM voice channels.
A/µ-Law companded data from the PCM input port is
converted to linear format, processed by a dedicated
arithmetic unit, re-converted to companded format
and then sent to the PCM output port.The PCM
output signal contains all the information of each
channel connected in conference except its own.
Applications
•
Digital PBX / KTS
•
Conference bridges
•
Digital C.O. switches
April 1994
Programmable attenuation and noise suppression
are provided for channels connected in conference
or transparent mode. Additionally, an input for an
external tone is featured that can be used as a signal
to indicate to connected parties that they are on a
conference call.
OS
Overflow
Attenuation/Noise Suppression
DSTi
Linear
to
µ/A-Law
MUX
Channel RAM
and
Adder
µ/A-Law
to
Linear
Parallel-to-Serial
Conversion
Serial-to-Parallel
Conversion
PCM Mode
Control
RESET
A/µ
Timebase
Cki
F0i
Cko
PCM Tone
Generator
TF
TD
DSTo
Control
RD
WR
D0-D7
CS
C/D
Figure 1 - Functional Block Diagram
8-3
MT8924
Preliminary Information
TD
TF
RESET
OS
DSTo
D7
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VSS
A/µ
DSTi
Cko
Cki
F0i
WR
RD
CS
C/D
VDD
D0
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
TD
Tone Duration (Input). When TD is High, a PCM-coded tone is sent out to all channels of
the enabled conferences instead of PCM data. TD is latched by frame pulse F0i so that all
channels have the same tone during the same frame number. When TD is Low, normal
operation is enabled.
2
TF
Tone Frequency (Input). This input is connected to an external squarewave generator. TF
is strobed by frame pulse F0i so that all channels have the same tone frequency during the
same number of frames. The PCM-coded tone level corresponds to 1/10th of the full scale
value, and is activated when TD is High.
3
RESET
Master RESET (Input). This input is used for system initialization after power up, or when
the companding law format has been changed. The RESET pin is strobed by the rising edge
of clock Cki. Complete circuit initialization takes two frame periods. Initialization disables the
output drivers of the microprocessor interface and DSTo.
4
OS
Overflow Signalling (Output). When OS is Low, a conference is in the overflow condition.
This signal is delayed by half of a timeslot relative to the beginning of the output channel of
the conference in overflow (see Figure 9).
5
DSTo
6-13
8-4
ST-BUS Serial Output. This pin is the output for the PCM signal. It is enabled upon
channel selection, otherwise it is placed in a high impedance state. Maximum bit rate is
2.048 Mb/s.
D7 to D0 Data Bus I/O Port. These are bidirectional data pins over which data and instructions are
transferred to and from the microprocessor (where D0 is the least significant bit). The bus is
in a high impedance state when RESET is Low and/or CS is High.
14
VDD
Positive Supply Voltage. Nominally 5 volts.
15
C/D
Control/Data Select (Input). The signal on this input defines whether the information on the
data bus should be interpreted as opcode or data. During a write operation a Low signal
defines the bus content as data, while a High signal defines it as opcode. During a read
operation this input differentiates overflow status between the first eight channels for C/D
being LOW, and the last two channels for C/D being HIGH (see Instruction 4). This input also
allows status monitoring (see Instruction 6) during a read operation.
16
CS
Chip Select (Input). This active low input selects the device for microprocessor read/write
operations. When CS is Low, data and instructions can be transferred to or from the
microprocessor, and when CS is High, the data bus is in a high impedance state.
17
RD
Read (Input). This active low input is for the read signal on the microprocessor interface.
The data bus is updated on the falling edge of RD.
18
WR
Write Input. This active low input is for the write signal on the microprocessor interface. The
data bus is strobed on the rising edge of WR.
MT8924
Preliminary Information
Pin Description (continued)
Pin #
Name
Description
19
F0i
Frame Pulse (Input). This is an 8 kHz active low input used for frame synchronization of the
PCM bit stream. The first falling edge of Cki following the falling edge of frame pulse F0i
determines the start of a new frame and must correspond to the first bit of the first channel.
When PCM frames of 1544 kbit/s are used, the rising edge of F0i must correspond to the
Extra (193rd) bit.
20
Cki
Clock (Input). This signal is the timing reference used for all internal operations. The PCM
bit cell boundaries lie on the alternate falling edges of this clock. The maximum allowable
clock frequency is 4096 kHz.
21
Cko
Clock (Output). This pin provides the master clock for a digital crosspoint switch (e.g.,
MT898x series, or the MT9080, MT9085 combination). Normally the signal on this pin is
identical to Cki. When Extra bit operating mode is selected (see Instruction 5), the first two
cycles of the master clock are suppressed (see Figure 10). This feature allows the MT8924
to operate in 1544 kbit/s systems.
22
DSTi
ST-BUS Serial Input. This pin accepts the serial PCM input stream at a maximum allowable
bit rate of 2048 kbit/s. In normal operation the first bit of the first channel is defined by the
rising edge of Cki following the falling edge of frame pulse F0i. When Extra bit operating
mode is selected, the first bit of the first channel defines the extra bit.
23
A/µ
A/µ - Law Select Input. When A/µ is High, A-Law is selected, and when A/µ is Low, µ-Law is
selected. The companding law selection must be done before initializing the device using
the RESET pin.
24
VSS
Negative Power Supply Voltage. Nominally 0 Volts.
Functional Description
The MT8924 is a device designed to provide
conferencing in a digital switching system in any
combination for up to all 32 channels of a 2048 kbit/s
ST-BUS stream (see Figure 3).
The information of channel N, frame M is first
converted to Linear PCM and then added to the
signal from other conferencees during the first half of
Microcontroller
STi0
.
.
.
.
STix-1
MT8980/81/82
Digital Switch
STix
STo0
.
.
.
.
STox-1
STox
MT8924
PCM Conference
Circuit (PCC)
Figure 3 -Typical Conference Connection
channel N+1, frame M and subtracted during the
second half of channel N-1, frame M+1. After Linearto-PCM conversion the subtraction result goes to the
parallel-to-serial converter, and appears at the
output on the N+1 channel, M+1 frame with respect
to the corresponding sending party information (see
Figure 4).
To a microprocessor the MT8924 appears as a
memory mapped peripheral device that can be
controlled by a set of six instructions. These
commands can be used to establish or cancel
conferences between the PCM channels and also to
transmit control messages on specific operating
modes. The microprocessor can initiate and receive
status messages or check conference connections
that are currently in operation.
Output
Information
Input
Information
A
B
B+C A+C A+B
C
DSTi
DSTo
MT8924
N
N+1 N+2
Input Channels
Frame M
N+1 N+2 N+3
Output Channels
Frame M+1
Figure 4 - Input/Output Channel Relationship
8-5
MT8924
Preliminary Information
PCM Byte
Noise
Threshold
A-Law
µ-Law
+ve input
-ve input
B7 - B0
B7 - B0
1/4096
1000 0000
0000 0000
9/4096
1000 0100
0000 0100
16/4096
1000 1000
0000 1000
32/4096
1000 1111
0000 1111
1/8159
1111 1111
0111 1111
9/8159
1111 1011
0111 1011
16/8159
1111 0111
0111 0111
32/8159
1111 0000
0111 0000
Table 1 - PCM Noise Suppression Threshold Levels
Overflow Detection / Input Channel Attenuation
Alternatively, a conference in the overflow condition
can be detected using the OS signal in conjunction
with frame pulse F0i. OS will be low during the
second half of a general output channel slot time N,
if channel N belongs to a conference in overflow (see
Figure 11). This information can be used to control
input channel attenuation through software control.
If the sum of the channels involved in one
conference exceeds the full scale value of the
accumulator, an overflow condition is generated
which can be monitored specifically by reading the
status of the overflow register. If an overflow
condition occurs, then each channel in a conference
can be independently attenuated if desired.
F1
F0
0
0
0
1
1
0
1
1
+ Full Scale
+ 0 Level
- 0 Level
- Full Scale
+ Full Scale
+ 0 Level
- 0 Level
- Full Scale
+ Full Scale
+ 0 Level
- 0 Level
- Full Scale
+ Full Scale
+ 0 Level
- 0 Level
- Full Scale
B7
B6
B5
B4
B3
B2
B1
B0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
Table 2 - PCM Byte Format
B7 (sign bit) is the MSB and B0 is the LSB
F1-F0 corresponds to the D5-D4 bits of the control byte of Operating Mode Instruction 5
8-6
Comments
No Inversion
Even Bit Inversion
Odd Bit Inversion
Bit Inversion
MT8924
Preliminary Information
Noise Suppression
Testing and Diagnostic Feature
When noise suppression is enabled for a specific
input channel then the PCM bytes for this channel,
when below the selected threshold level, are
converted to PCM bytes corresponding to the
minimum PCM code level before being added to the
conference sum.
For testing and diagnostic purposes, a status
instruction has been provided that indicates
conference location and attenuation level for each
channel requested. This data appears on the
databus upon status request.
The four threshold levels available correspond to the
first, fifth, ninth and sixteenth step of the first
segment. These are 1/4096, 9/4096, 16/4096, and
32/4096 with respect to full scale A-Law, and 1/8159,
9/8159, 16/8159, and 32/8159 with respect to full
scale µ-Law (see Table 1).
Programmable Control
Instruction 1 : Conference Mode Connection
Output clock Cko provides a reference time base for
a digital time/space crosspoint switch. Normally this
signal is identical to the master clock input Cki.
When operating with the extra bit selection, through
Instruction 5, Cko is low for two clock periods, which
allows operation of the MT8924 with the 1.544 MHz
PCM frame format (see Figure 10).
This function connects a PCM channel to a
conference. The control information from the
microprocessor consists of two data bytes and one
control byte. The first byte contains the conference
number (bits D0-D3) and the Start bit S (D4). When
S is High, the accumulator registers connected to a
conference are initialized. S set to High is only
required in Instruction 1 of the first channel
connected to a new conference, otherwise S is set
LOW to bring other channels into the conference.
The second byte contains the number of the
channel to be connected (D0-D4), and the Insert
Tone Enable bit IT (D5). When IT and TD are both
High all the channels belonging to that conference
are enabled using the insert tone function. The
third byte contains a four bit opcode (D0-D3) plus
information about the attenuation level and noise
suppression to be applied to the specific channel.
Transparent Mode
Instruction 2 : Transparent Mode Connection
The MT8924 can operate in transparent mode. In
this case the PCM input (DSTi) is passed unmodified
through the MT8924 to the output (DSTo) with a
delay of one frame and one channel. This feature
allows attenuation of specific channels that are not
connected to a conference.
This function sets up a PCM channel for
transparent
mode
operation.
The
control
information from the microprocessor consists of
one data byte and one control byte.
PCM Format Selection
PCM
digital
code
assignment
is
register
programmable and achieved through the use of
Instruction 5 (see Table 2). The available formats are
CCITT G.711 A-Law or µ-Law, with true-sign
Alternate Digit Inversion or true-sign/Inverted
Magnitude coding.
Tone Insertion
The MT8924 provides for tone insertion into PCM
output channels by using the two input pins TD and
TF. An externally generated square wave tone
applied to the TF input will generate a level
corresponding to 1/10 of the full scale accumulator
value when TD is High. Only channels connected in
a conference with the insertion tone bit (IT) active
will have the PCM coded tone at their output (see
Instruction 1).
The first byte contains the channel number, and
the second byte contains a four bit opcode (D0-D3)
and information about attenuation and noise
suppression levels to be applied to the specific
channel. PCM data on this channel is not added to
any conference, but is transferred to the PCM
output after a full frame pulse plus one channel
delay. It is not affected by the tone control pins (TF,
TD).
Instruction 3 : Disconnection
This function disconnects a PCM channel from a
conference. The control information from the
microprocessor consists of one data byte and one
8-7
MT8924
control byte. The data byte contains the number of
the channel to be disconnected. The second byte
contains the opcode (D0-D3). One frame pulse
must
pass
between
disconnection
and
reconnection of the same channel.
Instruction 4 : Overflow Status Monitoring
This function extracts overflow status information
on all existing conferences and transfers it to the
microprocessor data bus. This instruction consists
of two control bytes which are differentiated by the
C/D control signal. C/D set Low reads the status of
the first eight conferences, while C/D set High
reads the status of the remaining two conferences.
A conference is in overflow when the
corresponding status bit is high.
Instruction 5 : PCM Mode Select
This function is used to set the PCM format. The
control byte from the microprocessor consists of
one data byte. It contains the Extra Bit E (D6), the
Format Bits F1-F0 (D5, D4), and the opcode (D0D3). The E bit must be high when the PCM frame
contains an extra bit (i.e. 1.544 Mb/s). Normally E
is Low. Bits F1-F0 are used to select the PCM byte
format, according to Table 2. After RESET the
default values correspond to F1 at Low and F0 at
High if A-Law is selected, and F1 at High and F0 at
High if µ-Law is selected. All channels must be
disconnected when the PCM mode select
instruction is sent. They must remain disconnected
for at least two frame pulses after the instruction is
sent. It is recommended that this instruction be
used immediately following a system reset (see
RESET pin description).
8-8
Preliminary Information
Instruction 6 : Status Monitoring
This function is a read operation which consists of
a data byte, a control byte, and a status byte. It
extracts information for test and diagnostic
purposes and transfers it to the microprocessor
bus. The first byte contains the channel number,
while the second byte contains the opcode (D0D3). The third byte contains the status information
about the operating mode of the channel (D4-D7);
the attenuation level (D2-D3); and the noise
suppression level (D0-D1).
MT8924
Preliminary Information
Instruction 1 : Channel Connection in Conference Mode
Control Signals
Data Bus
Comments
CS
RD
C/D
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
X
X
X
S
P3
P2
P1
P0
Conference Number
0
1
0
0
X
X
IT
C4
C3
C2
C1
C0
PCM Channel Number and
Insertion Tone control
0
1
1
0
A1
A0
T1
T0
0
1
1
1
Opcode, Attenuation, and
Noise Suppression control
S:
P3-P0:
IT:
C4-C0:
A1-A0:
Conference Start Bit
Conference Number (1-10)
Insertion Tone Function Enable (IT=1)
Channel Number (0-31)
Channel Attenuation
00 = -0dB
01 = -3dB
10 = -6dB
T1-T0:
T1/T0
00
01
10
11
Channel Noise Suppression
A-Law
µ-Law
no noise suppression
9/4096
9/8159
16/4096
16/8159
32/4096
32/8159
Instruction 2 : Channel Connection in Transparent Mode
Control Signals
Data Bus
Comments
CS
RD
C/D
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
X
X
X
C4
C3
C2
C1
C0
0
1
1
0
A1
A0
T1
T0
0
0
1
1
PCM Channel Number
Opcode and Attenuation
T1-T0: see noise suppression description given for Instruction 1
Instruction 3 : Channel Disconnection
Control Signals
Data Bus
Comments
CS
RD
C/D
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
X
X
X
C4
C3
C2
C1
C0
0
1
1
0
X
X
X
X
1
1
1
1
PCM Channel Number
Opcode
Instruction 4: Overflow Status Monitoring
Control Signals
Data Bus
Comments
CS
RD
C/D
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
CF
8
CF
7
CF
6
CF
5
CF
4
CF
3
CF
2
CF
1
Conferences 1 to 8
0
0
1
1
X
X
X
X
X
X
CF
10
CF
9
Conferences 9 to 10
CF10 - CF1 : Conference is in overflow when bit is HIGH
Note : as long as RD remains LOW, the overflow status of the conference selected by C/D can be monitored in real time
8-9
MT8924
Preliminary Information
Instruction 5 : PCM Operating Mode Selection
Control Signals
CS
RD
0
1
E:
F1 - F0:
Data Bus
Comments
C/D
WR
D7
D6
D5
D4
D3
D2
D1
D0
1
0
X
E
F1
F0
0
1
0
1
see Table 1
Extra bit insertion (active when E=1)
PCM byte format selection (see Table 1)
00 = no bit inverted
01 = even bit (B0, B2, B4, B6) inverted
10 = odd bit (B1, B3, B5) inverted
11 = all bits (B0, B1, B2, B3, B4, B5, B6) inverted
Instruction 6 : Status Monitoring
Control Signals
Data Bus
Comments
CS
RD
C/D
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
X
X
X
C4
C3
C2
C1
C0
0
1
1
0
X
X
X
X
0
1
1
0
0
0
1
1
P3
P2
P1
P0
A1
A0
T1
T0
P3 - P0:
Note:
8-10
channel mode operation information
A1 - A0:
see channel attenuation description
0000 = no connection
for Instruction 1
1111 = transparent mode
T1 - T0:
see noise suppression description
1010 - 0001 = conference mode
for Instruction 1
P3 - P0 provides conference number
Instruction 6 enables the data bus to read the status until reset by C/D=0, WR=1, and CS=0
MT8924
Preliminary Information
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Units
VDD - VSS
- 0.3
7
V
VSS - 0.3
VDD + 0.3
V
± 10
mA
+ 150
°C
500
mW
1
Supply Voltage
2
Voltage on any I/O pin
VI/O
3
Current on any I/O pin
II/O
4
Storage Temperature
TST
5
Power Dissipation (plastic package)
PD
- 65
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed.
Recommended Operating Conditions
Characteristics
Sym
Min
Typ*
Max
Units
5
5.25
V
1
Supply Voltage
VDD
4.75
2
Ambient Operating Temp. Range
TOP
0
+70
°C
3
Input Voltage High
VIH
2.4
VDD
V
4
Input Voltage Low
VIL
VSS
0.8
V
Test Conditions
for 400mv noise
margin
* Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
DC Characteristics: Clocked operation (TOP=0 to 70°C; V DD=5V±5%)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
0.8
V
Pins 1-3, 6-13, 15-20, 22-23
V
Pins 1-3, 6-13, 15-20, 22-23
V
Pins 4, 6-13; IOL=4 mA
V
Pins 4, 6-13; IOL=4 mA
1
Input Low Level
VIL
2
Input High Level
VIH
3
Output Low Level
VOL
4
Output High Level
VOH
5
Output Low Level
VOL
0.4
V
Pins 5, 21; IOL=8 mA
6
Input Leakage Current
IIL
10
µA
Pins 1-3, 6-13, 15-20, 22-23;
VIN=0 to VDD
7
Data Bus Leakage Current
IOL
±10
µA
Pins 6-13; VIN=0 to VDD;
CS=VDD
8
Supply Current
IDD
10
mA
Pin 14; Cki=4.096 MHz
2.0
0.4
2.4
All DC characterisitics are valid 250µs after VDD and C4i have been applied.
AC Electrical Characteristics - Capacitances
Characteristics
Sym
Min
Typ
Max
Units
CI
5
pF
1
Input Capacitance
2
I/O Capacitance (Bidirectional)
CI/O
15
pF
3
Output Capacitance
CO
10
pF
Test Conditions
frequency=1MHz; TOP=0
to 70°C;
unused pins tied to VSS;
VDD=5V±5%
8-11
MT8924
Preliminary Information
AC Electrical Characteristics - Clocked Timing* (TOP=0 to 70°C; V DD=5V±5%)
Characteristics
Sym
Min
Typ
Max
Units
tCK
230
ns
Test Conditions
1
Clock period
2
Clock low level width
tWLCK
100
ns
3
Clock high level width
tWHCK
100
ns
4
Clock rise time
tRCK
25
ns
5
Clock fall time
tFCK
25
ns
6
Sync. low setup time
tSLSY
50
ns
7
Sync. low level hold time
tHLSY
40
ns
8
Sync. high setup time
tSHSY
80
ns
9
Sync. high width
tWHSY
tCK
ns
10
OS propagation delay from rising
edge of Clock
tPDOS
100
ns
CL=50pF
11
Cko propagation delay to Clock
edges
tPDEC
80
ns
CL=50pF
12
TD setup time
tSTD
80
ns
13
TD hold time
tHTD
40
ns
14
TD setup time
tSTF
80
ns
15
TD hold time
tHTD
40
ns
**
* All AC characteristics are valid 250µs after VDD and the clock have been applied. C L is the max. capacitive load and RL is the test pull up
resistor. With Extra Bit Insert operating mode these times are 80ns longer.
** With Extra Bit Insert operating mode this time becomes 3tCK.
tRCK
tCK
tFCK
Cki
tWHCK
tWLCK
tHLSY
tSHSY
tSLSY
F0i
tWHSY
tHTD
tSTD
TD
tSTF
tHTF
TF
tPDEC
tPDEC
Cko
tPDOS
OS
Figure 5 - Clock Timing
8-12
MT8924
Preliminary Information
AC Electrical Characteristics - PCM Timing* (TOP=0 to 70°C; V DD=5V±5%)
Characteristics
Sym
Min
Input PCM setup time
tSPCM
80
ns
2
Input PCM hold time
tHPCM
35
ns
3
Output PCM propagation delay
tPD
25
1
Typ
Max
125
Units
Test Conditions
ns
CL=150pF, RL=1KΩ
in 2.048MHz mode **
*All AC characteristics are valid 250µs after VDD and the clock have been applied. CL is the max. capacitive load and R L is the test pull up
resistor.
**With Extra Bit Insert operating mode these times are 80ns longer.
0
Cki
1
2
F0i
tSPCM tHPCM
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DSTi
MSB
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tPD
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DSTo
MSB
Figure 6 - PCM Timing
AC Electrical Characteristics - RESET Timing* (TOP=0 to 70°C; VDD=5V±5%)
Characteristics
Sym
Min
Typ
Max
Units
1
RESET low setup time
tSLRES
100
ns
2
RESET low hold time
tHLRES
50
ns
3
RESET high setup time
tSHRES
90
ns
4
RESET high level width
tWHRES
tCK
ns
Test Conditions
* All AC characteristics are valid 250µs after VDD and the clock have been applied. CL is the max. capacitive load and RL is the test pull up
resistor.
Cki
tSLRES
tHLRES
tSHRES
RESET
tWHRES
Figure 7 - Reset Timing
8-13
MT8924
Preliminary Information
AC Electrical Characteristics - Write Timing (TOP=0 to 70°C; V DD=5V±5%)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Write Pulse low width
tWLWR
150
ns
2
Write Pulse high width
tWHWR
200
ns
3
Repetition Interval between active Write
Pulses
tREPWR
500
ns
4
Read high setup time to active Write
Pulse
tSHRD
0
ns
5
Read high hold time from active Write
Pulse
tHHRD
20
ns
6
Write Pulse rise time
tRWR
60
ns
7
Write Pulse fall time
tFWR
60
ns
8
CS low setup time to WR falling edge
tSLCSWR
0
ns
Active case
9
CS low hold time from WR falling edge
tHLCSWR
0
ns
Active case
10
CS high setup time to WR rising edge
tSHCSWR
0
ns
11
CS high hold time from WR rising edge tHHCSWR
0
ns
12
C/D setup time to Write Pulse end
tSC/DWR
130
ns
13
C/D hold time from Write Pulse end
tHCDWR
25
ns
14
Input setup time to Write Pulse end
tSDWR
130
ns
15
Input hold time from Bus Write Pulse
end
tHDWR
25
ns
tWLWR
tWHWR
WR
tSHRD
tRWR
tFWR
tREPWR
tHHRD
RD
tSHCSWR
CS
tHLCSWR
tHHCSWR
tSLCSWR
tSCDWR
tHCDWR
C/D
tSDWR
tHDWR
DIN
Figure 8 - Write Timing Characteristics
8-14
MT8924
Preliminary Information
AC Electrical Characteristics - Read Timing (TOP=0 to 70°C; V DD=5V±5%)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Read Pulse low width
tWLRD
180
ns
2
Read Pulse high width
tWHRD
200
ns
3
Repetition Interval between active Read
Pulses
tREPRD
500
ns
4
Write high setup time to active Read
Pulse
tSHWR
0
ns
5
Write high hold time from active Read
Pulse
tHHWR
20
ns
6
Read Pulse rise time
tRRD
60
ns
7
Read Pulse fall time
tFRD
60
ns
8
Low setup time to RD falling edge
tSLCSRD
0
ns
Active case
9
Low hold time from RD falling edge
tHLCSRD
0
ns
Active case
10
High setup time to RD falling edge
tSHCSRD
0
ns
Active case
11
High hold time from RD rising edge
tHHCSRD
0
ns
Active case
12
C/D setup time to RD Pulse start
tSCDRD
20
ns
13
Hold time from Read Pulse end
tHCDRD
25
ns
14
Propagation delay from falling edge of
Read Pulse
tPDD
120
ns
Read; CL=200pF
15
Propagation delay from rising edge of
Read Pulse to high impedance state
tHZ
80
ns
Write; CL=200pF
tWHRD
tWLRD
RD
tSHWR
tHHWR
tFRD
tREPRD
tRRD
WR
tSHCSRD
CS
tSLCSRD
tHLCSRD
tSCDRD
tHCDRD
tHHCSRD
C/D
tPDD
tHZ
DOUT
Figure 9 - Read Timing Characteristics
8-15
MT8924
Preliminary Information
Extra Bit
Bit 0 Channel 0
Bit 1 Channel 0
Cki
tPDEC
Cko
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F0i
Figure 10 - CKo Timing with Extra Bit Insertion Mode
Channel N-1
Channel N
Channel N+1
Cki
OS
Figure 11 - OS Timing with Output PCM Channel belonging to a Conference in Overflow
8-16