MV1820 Purchase of Mitel Semiconductor I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. HEADQUARTERS OPERATIONS MITEL SEMICONDUCTOR Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (01793) 518000 Fax: (01793) 518411 MITEL SEMICONDUCTOR 1500 Green Hills Road, Scotts Valley, California 95066-4922 United States of America. Tel (408) 438 2900 Fax: (408) 438 5576/6231 Internet: http://www.gpsemi.com CUSTOMER SERVICE CENTRES ● FRANCE & BENELUX Les Ulis Cedex Tel: (1) 69 18 90 00 Fax : (1) 64 46 06 07 ● GERMANY Munich Tel: (089) 419508-20 Fax : (089) 419508-55 ● ITALY Milan Tel: (02) 6607151 Fax: (02) 66040993 ● JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 ● KOREA Seoul Tel: (2) 5668141 Fax: (2) 5697933 ● NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 5576/6231 ● SOUTH EAST ASIA Singapore Tel:(65) 3827708 Fax: (65) 3828872 ● SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 ● TAIWAN, ROC Taipei Tel: 886 2 25461260 Fax: 886 2 27190260 ● UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (01793) 726666 Fax : (01793) 518582 These are supported by Agents and Distributors in major countries world-wide. © Mitel Corporation 1998 Publication No. DS3106 Issue No. 3.0 May 1996 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners. 6 MV1820 5 MV1820 CRYSTAL SPECIFICATION Parallel resonant fundamental frequency 27.750000MHz. AT cut. Tolerance at -10°C to 60°C ± 50ppm. Tolerance overall ± 100ppm. Nominal load capacitance 20pF. Equivalent series resistance <20Ω. FUNCTIONAL DESCRIPTION The video signal is sliced to produce data and synchronising signals. Timing circuits monitor the sync signal to enable the MV1820 to lock onto the broadcast signal. A timing window, for the Vertical Blanking Interval (VBI) lines 6 - 22 and 318 - 335, is established to enable the acquisition circuit to monitor the sliced data signal for valid teletext data. The framing code is checked for valid World System Teletext (WST) data. Magazine, packet and designation code bytes are checked and valid Broadcast Service Data Packets (BSDP) format two type only are accepted. These are known as packet 8/30. Format two is signalled by byte six, data bit two being set high and bits 3 and 4 set low. Bytes 13 to 25 inclusive are Hamming decoded (8,4) and stored in seven registers each of eight bits. If the complete message is correctly received with no uncorrectable Hamming errors, an interrupt to the microprocessor is signalled by the DAV (bar) pin going low. At the same time the data is transferred to a second bank of registers, reorganised with original numbered bytes 14, 15, 24, 25 and 13 placed after byte 23, to be read out on the I2C bus when so requested. Subsequent valid messages will continue to be transferred to the output registers overwriting any existing data. In this way the output registers always contain the latest PDC message. The MV1820 is configured as an I2C bus slave transmitter with a selectable address. The I2C bus address is 0010 0001 (20 + 1 hex) with the address select (AS) pin set high, or 0010 0011 (22 + 1 hex) with the AS pin set low. The read bit (LSB) must always be set, it is not possible to write to the MV1820. On recognising its address, the MV1820 will send an acknowledge and then transmit on the SDA line the first byte from the output registers (decoded byte 16 and 17) most significant bit (MSB) first. It will then monitor the SDA line for an acknowledge from the microprocessor. If the microprocessor does NOT send an acknowledge, the MV1820 will release the data line to allow the microprocessor to send a stop condition. If the microprocessor does send an acknowledge, the following bytes of the message will be output provided each byte is acknowledged. The final data will be byte 13 followed by the four ‘1’s. When readout is complete, the DAV (bar) pin is reset high and the output registers are all set high. If the microprocessor continues to send clocks on the SCL line, the MV1820 will output FF bytes on the SDA line. Also, if the MV1820 is readdressed before another PDC message is received, the MV1820 will output FF bytes on the SDA line. The microprocessor can prematurely stop the message by NOT sending an Acknowledge followed by a STOP condition after any byte has been sent by the MV1820. The registers will then be reset to FF bytes and the DAV pin will be reset high. To prevent any corruption of the data in the output registers during I2C bus activity, valid PDC messages are held in the incoming registers until I2C bus activity ceases. Here they may be overwritten by new PDC messages until the I2C bus activity ceases and they can then be transferred to the output registers. System clock is provided by an on - chip 27.75MHz oscillator together with an external parallel resonant fundamental frequency AT cut crystal. Following a reset, RESET pulled low, the output I2C bus registers will contain FF bytes and the DAV pin will be set high. When the power supply is removed, the I2C bus will not be clamped to ground, leaving it free for other I2C bus traffic. Fig.3 Typical application diagram 4 MV1820 ELECTRICAL CHARACTERISTICS (continued) These characteristics are guaranteed over the following conditions (unless otherwise stated) Tamb = 0 to 70˚C, VDD = 5V ± 10% Pin Characteristic Value Min Typ Max Units Conditions I2C bus 11, 13 SCL, SDA Schmitt inputs Not clamped when VDD = 0V Input voltage Low 0 1.5 V Input voltage High 3.5 VDD V 0.1 0.4 V 100 1000 kHz Output voltage Low 11 SCL clock frequency DAV data available IOL = 3.0mA 100k (nom) pull-up resistor 0.2 Output voltage low 0.4 V 1 RESET Schmitt input IOH = 2.4mA 100k (nom) pull-up resistor Input voltage Low 0 0.8 V Input voltage High VDD-1.0 VDD V Input current Low -22 -220 µA VIN = VSS Input current High -10 +10 µA VIN = VDD -50 NOTE Input voltage low and input voltage high for EXT/INT, AS and XTI are as specified for DATA I/O. PIN DESCRIPTION Pin Name and Description Symbol Pin RESET 1 Active Low Reset. Includes a 100kΩ pull - up resistor EXT/INT 2 Control Pin for SYNC I/O and DATA I/O. Includes a 100kΩ pull - down resistor. When low or not connected, internal SYNC and DATA are used, pins 9 and 10 are outputs. When high, supply SYNC and DATA from an external source, pins 9 and 10 are inputs. BLC 3 Black level capacitor. WLC 4 White level capacitor. VIDEO 5 Input for composite video signal with negative going syncs GND 6 Ground 0 volts. TCR 7 Time constant resistor. Controlling discharge rate of black and white level capacitor voltages. AS 8 Address select for I2C bus. [0010 0001] with AS set high, or [0010 0011] with AS set low. Includes 100kΩ pull - down resistor. DATA I/O 9 Data input/output. SYNC I/O 10 Sync input/output. SCL 11 I2C bus serial clock. VDD 12 Positive supply voltage +5V ± 10% SDA 13 I2C bus bi-directional data port. DAV 14 Active low open drain output data available signal to microprocessor. Includes 100kΩ pull - up resistor XTO 15 Crystal out, 27.75MHz fundamental crystal with on-chip 1MΩ resistor to XTI. XTI 16 Crystal input. 3 MV1820 ELECTRICAL CHARACTERISTICS These characteristics are guaranteed over the following conditions (unless otherwise stated) Tamb = 0 to 70˚C, VDD = 5V ± 10% Characteristic Pin Supply voltage 12 Supply current 12 Video input 5 Value Max 4.5 5.0 5.5 V 20 25 mA 1.8 3.0 Vpp 250 Ω 200 kΩ Connected to VDD nF Connected to GND Ω 1MHz V IOH = -1.2mA 0.4 V IOL = 2.4mA Source impedance TCR input 4.7 4.7 3&4 10 Capacitor value +10% -10% Capacitor tolerance 5 Effective series resistance DATA I/O and SYNC I/O 9 & 10 VDD-1.0 Output voltage High 4.5 0.2 Output voltage Low Input voltage Low 0 0.8 V Input voltage High VDD-1.0 VDD V -30 +30 µA Input current EXT/INT Bottom of sync to white (pk to pk) 7 External resistance BLC and WLC Conditions Typ 0.8 Video amplitude Units Min 2 VIN = VSS or VDD 100k (nom) pull-down resistor Input voltage Low 0 0.8 V Input voltage High VDD-1.0 VDD V Input current Low -10 +10 µA VIN = VSS Input current High 22 220 µA VIN = VDD AS 50 8 100k (nom) pull-down resistor Input voltage Low 0 1.0 V Input voltage High VDD-1.0 VDD V Input current Low -10 +10 µA VIN = VSS Input current High 22 50 220 µA VIN = VDD Input current Low -0.5 -5.0 -20 µA -0.3<VIN<VIL max Input current High 0.5 5.0 20 µA VIHmin<VIN<(VDD + 0.3) VDD-1.0 4.5 V IOH = -1.0mA V IOL = 2.0mA XTI Input XTO Output Output voltage High Output voltage Low Frequency 2 16 15 0.2 27.750 0.4 MHz ±100ppm MV1820 Video Programme Delivery Control Interface Circuit Supersedes version in October 1995 Media IC Handbook, HB3120 - 3.0 DS3106 - 3.0 May 1996 The MV1820 is a high speed CMOS receiver for Programme Delivery Control (PDC) messages broadcast in World System Teletext (WST) Format Two Broadcast Service Data Packets (BSDP). The PDC message can be read on an I2C bus with data format similar to standard Video Programming Service (VPS) decoders. Additional data is appended to include new PDC features. It is intended for use in Video Cassette Recorders to provide automatic recording of suitably labelled Television programmes requested by the user. 8 7 6 5 4 3 2 1 DP16 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 FEATURES ■ ■ ■ ■ On chip data slicing Low external component count I2C bus for low cost interfacing Advanced CMOS technology gives low power dissipation and high reliability MP16 9 10 11 12 13 14 15 16 PIN DESCRIPTION PIN DESCRIPTION 1 2 3 4 5 6 7 8 RESET EXT/INT BLC WLC VIDEO GND TCR AS 16 15 14 13 12 11 10 9 XTI XTO DAV SDA VDD SCL SYNC I/O DATA I/O ABSOLUTE MAXIMUM RATINGS Supply voltage All inputs Operating temperature Storage temperature ORDERING INFORMATION MV1820F/CG/DPAS MV1820F/CG/MPES 0.3V to 7V -0.3 to VDD +0.3V 0 to +70°C -55 to 125°C Fig.1 Pin connections - top view Fig.2 MV1820 block diagram For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE