E2U0037-28-82 ¡ Semiconductor MSM7602 ¡ Semiconductor This version: Aug. 1998 MSM7602 Previous version: Nov. 1996 Echo Canceler GENERAL DESCRIPTION The MSM7602 is an improved version of the MSM7520 with the same basic configuration. The MSM7602 uses a 19.2 MHz clock frequency to meet PHS, the 3 V power supply (2.7 V to 5.5 V), and compact packaging. Also, this device adds the howling detecter control pins and main clook output pins. (See the Appendix) The MSM7602 is a low-power CMOS IC device for canceling echo (in an acoustic system or telephone line) generated in a speech path. Echo is canceled, in digital signal processing, by estimating the echo path and generating a pseudo echo signal. When used as an acoustic echo canceler, the device cancels the acoustic echo between the loud speaker and the microphone which occurs during hands free communication such as with a cellular phone or a conference system phone. When used as a line echo canceler, the device cancels the line echo caused by impedance mismatching in a hybrid. In addition, the MSM7602 makes possible a quality conversation by controlling the noise level and preventing howling with howling detector, double talk detector, attenuation function, and a gain control function. The devise also controls the low level noise with a center clipping function. Further, the MSM7602 I/O interface supports m-law PCM . The use of a single chip CODEC, such as the MSM7566/7704 (3 V) or MSM7543/7533 (5 V), allows an economic and efficient echo canceler configuration. FEATURES • Handles both acoustic echoes and telephone line echoes. • Cancelable echo delay time: MSM7602-001 ................. For a single chip: 23 ms (max.) MSM7602-011 ................. For a cascade connection (can also be used for a single chip) Master chip: 23 ms (max.) Slave chip: 31 ms (max.) Cancelable up to 209 ms (1 master plus 6 slaves) For a single chip: 23 ms (max.) • Echo attenuation : 30 dB (typ.) • Clock frequency : 19.2 MHz External input and internal oscillator circuit are provided. • Power supply voltage : 2.7 V to 5.5 V • Package options: 28-pin plastic SSOP (SSOP28-P-485-0.65-K) (Product name : MSM7602-001GS-K) 56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name : MSM7602-011GS-2K) 1/29 ¡ Semiconductor MSM7602 BLOCK DIAGRAM MSM7602-001 (Single chip only) RIN S/P Non–linear/ Linear ATT Howling Detector Double Talk Detector Power Calculator Linear/ Non–linear Gain SOUT P/S Center Clip ROUT Adaptive FIR Filter (AFF) – Linear/ Non–linear P/S + ATT + Non–linear/ S/P Linear SIN RST WDT VDD PWDWN * Clock Generator Mode Selector I/O Controller VSS MCKO X1/CLKIN X2 SCKO SYNCO NLP HCL ADP ATT GC INT IRLD HD SCK SYNC , MSM7602-011 (Cascade connection or single chip) S/P Non–linear/ Linear ATT Howling Detector Double Talk Detector Power Calculator Gain Linear/ Non–linear SOUT P/S Center Clip ATT + Parallel I/O Controller + Non–linear/ Linear ROUT PD15 * Parallel I/O Port Adaptive FIR Filter (AFF) – Linear/ Non–linear P/S – RIN S/P PD 0 * OF1 * OF2 * SF1 * SF2 * SIN RST * WDT VDD * * PWDWN MCKO * Clock Generator Mode Selector I/O Controller VSS * X1/CLKIN X2 SCKO SYNCO NLP HCL ADP ATT GC MS HD INT IRLD SCK SYNC * * * * * If the MSM7602-011 is used in the slave mode, only the diagonally hatched blocks and the pins marked with * are used. 2/29 ¡ Semiconductor MSM7602 PIN CONFIGURATION (TOP VIEW) 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 28-Pin Plastic SSOP Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 NLP 8 SIN 15 VSS 22 SYNCO 2 HCL 9 RIN 16 HD 23 SCKO 3 ADP 10 SCK 17 X1/CLKIN 24 RST 4 VDD 11 SYNC 18 X2 25 WDT 5 ATT 12 SOUT 19 VDD 26 GC 6 INT 13 ROUT 20 PWDWN 27 VDD 7 IRLD 14 VSS 21 VSS 28 MCKO 3/29 ¡ Semiconductor MSM7602 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 42 2 41 3 40 4 39 5 38 6 37 7 36 8 35 9 34 10 33 11 32 12 31 13 30 14 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56-Pin Plastic QFP Pin Symbol Pin Symbol Pin Symbol Pin 1 NLP 15 PD0 29 PD12 43 * 2 HCL 16 PD1 30 PD13 44 PD14 3 ADP 17 PD2 31 X1/CLKIN 45 PD15 4 MS 18 PD3 32 X2 46 MCKO 5 ATT 19 PD4 33 VDD 47 SF2 6 INT 20 PD5 34 PWDWN 48 OF1 7 IRLD 21 VSS 35 VSS 49 VSS 8 SIN 22 PD6 36 SYNCO 50 * 9 RIN 23 PD7 37 SCKO 51 VSS 10 SCK 24 PD8 38 RST 52 SF1 11 SYNC 25 PD9 39 WDT 53 OF2 12 SOUT 26 PD10 40 GC 54 VDD 13 ROUT 27 PD11 41 VDD 55 VDD 14 VSS 28 HD 42 VDD 56 * Symbol *: No connect pin 4/29 ¡ Semiconductor MSM7602 PIN DESCRIPTIONS (1/5) Pin 28-pin 56-pin Symbol Type Description Control pin for the center clipping function. This pin forces the SOUT output to a minimum value when the SOUT signal is below –54 dBm0. Effective for reducing low-level noise. • Single Chip or Master Chip in a Cascade Connection "H": Center clip ON "L": Center clip OFF • Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. Through mode control. When this pin is in the through mode, RIN and SIN data is output to ROUT and SOUT. At the same time, the coefficient of the adaptive FIR filter is cleared. • Single Chip or Master Chip in a Cascade Connection "H": Through mode "L": Normal mode (echo canceler operates) • Slave Chip in a Cascade Connection Same as master This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. SSOP QFP 1 1 NLP I 2 2 HCL I 3 3 ADP I AFF coefficient control. This pin stops updating of the adaptive FIR filter (AFF) coefficient and sets the coefficient to a fixed value, when this pin is configured to be the coefficient fix mode. This pin is used when holding the AFF coefficient which has been once converged. • Single Chip or Master Chip in a Cascade Connection "H": Coefficient fix mode "L": Normal mode (coefficient update) • Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. — 4 MS I Select signal. This pin selects between the master chip and slave chip when used in a cascade connection. "L": Single chip or master chip "H": Slave chip 5/29 ¡ Semiconductor MSM7602 (2/5) Pin 28-pin 56-pin Symbol Type Description 5 ATT I Control for the ATT function. This pin prevents howling by attenuators (ATT) for the RIN input and SOUT output. If there is input only to RIN, the ATT for the SOUT output is activated. If there is no input to SIN, or if there is input to both SIN and RIN, the ATT for the RIN input is activated. Either the ATT for the RIN output or the ATT for the SOUT is always activated in all cases, and the attenuation of ATT is 6 dB. • Single Chip or Master Chip in a Cascade Connection "H": ATT OFF "L": ATT ON "L" is recommended if performing echo cancellation. • Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. 6 6 INT I Interrupt signal which starts 1 cycle (8 kHz) of the signal processing. Signal processing starts when "H"-to-"L" transition is detected. • Single Chip or Master Chip in a Cascade Connection Connect the IRLD pin. • Slave Chip in a Cascade Connection Connect the IRLD pin of the master chip. INT input is invalid for 100 ms after reset due to initialization. Refer to the control pin connection example. 7 7 IRLD O 8 8 SIN I Load detection signal output when the SIN and RIN serial input data is loaded in the internal registers. • Single Chip Connect to the INT pin. • Master Chip in a Cascade Connection Connect to the INT pin of the master chip and all the slave chips. • Slave Chip in a Cascade Connection Leave open. Refer to the control pin connection example. Transmit serial data. Input the PCM signal synchronized to SYNC and SCK. Data is read in at the falling edge of SCK. 9 9 RIN I Receive serial data. Input the PCM signal synchronized to SYNC and SCK. Data is read at the falling edge of SCK. 10 10 SCK I Clock input for transmit/receive serial data. This pin uses the external SCK or the SCKO. Input the PCM CODEC transmit/receive clock (64 to 2048 kHz). SSOP QFP 5 6/29 ¡ Semiconductor MSM7602 (3/5) Pin 28-pin 56-pin Symbol Type Description 11 11 SYNC I Sync signal for transmit/receive serial data. This pin uses the external SYNC or SYNCO. Input the PCM CODEC transmit/receive sync signal (8 kHz). 12 12 SOUT O Transmit serial data. Outputs the PCM signal synchronized to SYNC and SCK. This pin is in a high impedance state during no data output. 13 13 ROUT O Receive serial data. Outputs the PCM signal synchronized to SYNC and SCK. This pin is in a high impedance state during no data output. — 15 PD0 I/O This is the bidirectional bus pin for parallel data transfer between the master chip and slave chip when used in a cascade connection. The PD15 pin corresponds to MSB. This pin is in a high impedance state during no data output. Data is loaded in at the falling edge of SFx. — — — QFP — SSOP 20 22 PD5 PD6 — — — — — — — 27 29 30 44 45 PD11 PD12 PD13 PD14 PD15 16 28 HD I 17 31 X1/CLKIN I 18 32 X2 O Controls the howling detect function. This pin detets and cancels a howling generated during hand-free talking for acoustic system. This function is used to cancel acoustic echoes. • Single Chip or Master Chip in a Cascade Connection "L": Howling detector ON "H": Howling detector OFF • Slave Chip in a Cascade Connection Fixed at "L" External input for the basic clock (17.5 to 20 MHz) or for the crystal oscillator. When the internal sync signal (SYNCO, SCKO) is used, input the basic clock of 19.2 MHz. Crystal oscillator output. Used to configure the oscilation circuit. Refer to the internal clock generator circuit example. When inputting the basic clock externally, insert a 5 pF capacitor with excellent high frequency characteristics between X2 and GND. 7/29 ¡ Semiconductor MSM7602 (4/5) Pin 28-pin 56-pin Symbol Type Description SSOP QFP 20 34 PWDWN I Power-down mode control when powered down. "L": Power-down mode "H": Normal operation mode During power-down mode, all input pins are disabled and output pins are in the following states : High impedance : SOUT, ROUT, PD0 to 15 "L": SYNCO, SCKO, MCKO "H": OF1, OF2, X2 Holds the last state : WDT, IRLD Reset after the power-down mode is released. 22 36 SYNCO O 8 kHz sync signal for the PCM CODEC. Connect to the SYNC pin and the PCM CODEC transmit/receive sync pin. Leave it open if using an external SYNC. 23 37 SCKO O 24 38 RST I Transmit clock signal (256 kHz) for the PCM CODEC. Connect to the SCK pin and the PCM CODEC transmit/receive clock pin. Leave it open if using an external SCK. Reset signal. "L": Reset mode "H": Normal operation mode Due to initialization, input signals are disabled for 100 ms after reset (after RST is returned from L to H). Input the basic clock during the reset. Output pins during the reset are in the following states : High impedance: SOUT, ROUT, PD0 to 15 "L": WDT "H": OF1, OF2 Not affected: X2, SYNCO, SCKO, IRLD, MCKO 25 39 WDT O 26 40 GC I Test program end signal. This signal is output when the one cycle (8kHz) of processing is completed. Leave it open. Input signal by which the gain controller for the RIN input is controlled and the RIN input level is controlled and howling is prevented. The gain controller adjusts the RIN input level when it is –20 dBm0 or above. RIN input levels from –20 to –11.5 dBm0 will be suppressed to –20 dBm0 in the attenuation range from 0 to 8.5 dB. RIN input levels above –11.5 dBm0 will always be attenuated by 8.5 dB. • Single Chip or Master Chip in a Cascade Connection "H": Gain control ON "L": Gain control OFF "H" is recommended for echo cancellation. • Slave Chip in a Cascade Connection Fixed at "L" This pin is loaded in synchronization with the falling edge of the INT signal or the rising edge of RST. 8/29 ¡ Semiconductor MSM7602 (5/5) Pin 28-pin 56-pin Symbol Type Description SSOP QFP 28 — 46 47 MCKO SF2 O I Basic clock (19.2 MHz). Parallel data transfer flag. • Single Chip Fixed at "H" • Master Chip in a Cascade Connection Fixed at "H" • Slave Chip in a Cascade Connection Connect OF2 of the master chip to the 1st stage slave chip. Connect OF1 of the previous stage slave chip to the 2nd and later stage slave chips. Refer to the control pin connection example. — 48 OF1 O — 52 SF1 I Parallel data transfer flag. • Single Chip Leave open. • Master Chip in a Cascade Connection Connect to the SF1 of all slaves. • Slave chip in a Cascade Connection Connect to the SF2 of the next stage slave chip. Connect the last stage slave chip to the SF1 of the master chip. Refer to the control pin connection example. Parallel data transfer flag. • Single Chip Connect OF2. • Master Chip in a Cascade Connection Connect OF1 of the last stage slave chip. • Slave Chip in a Cascade Connection Connect OF1 of master chip for all slave chips. Refer to the control pin connection example. — 53 OF2 O Parallel data output flag. • Single Chip Connect to SF1. • Master Chip in a Cascade Connection Connect to SF2 of the 1st stage slave chip. • Slave Chip in a Cascade Connection Leave open. Refer to the control pin connection example. 9/29 ¡ Semiconductor MSM7602 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Power Supply Voltage VDD Input Voltage VIN Power Dissipation Storage Temperature Condition Rating Unit –0.3 to +7 V Ta = 25˚C –0.3 to VDD + 0.3 V 1 W — –55 to +150 ˚C PD TSTG RECOMMENDED OPERATING CONDITIONS Parameter (VDD = 2.7 V to 3.6 V) Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD — 2.7 3.3 3.6 V Power Supply Voltage VSS — 0 — V Pins other than X1 2.0 — VDD V X1 pin 2.2 — VDD V — High Level Input Voltage VIH Low Level Input Voltage VIL — 0 — 0.5 V Operating Temperature Ta — –40 +25 +85 ˚C Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD — 4.5 5 5.5 V Power Supply Voltage VSS (VDD = 4.5 V to 5.5 V) Parameter — 0 — V Pins other than X1, SCK 2.4 — VDD V X1, SCK pins — High Level Input Voltage VIH 3.5 — VDD V Low Level Input Voltage VIL — 0 — 0.8 V Operating Temperature Ta — –40 +25 +85 ˚C ELECTRICAL CHARACTERISTICS DC Characteristics Parameter (VDD = 2.7 V to 3.6 V, Ta = –40˚C to +85˚C) Symbol Condition Min. Typ. Max. Unit 2.2 — VDD V 0.4 V High Level Output Voltage VOH IOH = 40 mA Low Level Output Voltage VOL IOL = 1.6 mA 0 — High Level Input Current IIH VIH = VDD — 0.1 1 mA MS with pull-down 6 60 120 mA Low Level Input Current IIL VIL = VSS –1 –0.1 — mA SF1, SF2 with pull-up –60 –33 –6 mA VOH = VDD — 0.1 1 mA –60 –33 –6 mA –1 –0.1 — mA — 20 30 mA — 10 50 mA High Level Output Leakage Current IOZH PD15 to PD0 Low Level Output Leakage Current IOZL with pull-up VOL = VSS Input other than the above Power Supply Current (Operating) IDDO Power Supply Current (Stand-by) IDDS Input Capacitance Output Load Capacitance — PWDWN = "L" CI — — — 15 pF CLOAD — — — 20 pF 10/29 ¡ Semiconductor Parameter MSM7602 Symbol Condition (VDD = 4.5 V to 5.5 V, Ta = –40˚C to +85˚C) Typ. Min. Max. Unit High Level Output Voltage VOH IOH = 40 mA 4.2 — VDD V Low Level Output Voltage VOL IOL = 1.6 mA 0 — 0.4 V High Level Input Current IIH VIH = VDD — 0.1 10 mA MS with pull-down 10 100 200 mA Low Level Input Current IIL VIL = VSS –10 –0.1 — mA –100 –50 –10 mA — 0.1 10 mA –100 –50 –10 mA –10 –0.1 — mA — 30 45 mA — 10 50 mA High Level Output Leakage Current IOZH SF1, SF2 with pull-up VOH = VDD PD15 to PD0 Low Level Output Leakage Current IOZL with pull-up VOL = VSS Input other than the above Power Supply Current (Operating) IDDO Input Capacitance IDDS Input Capacitance Output Load Capacitance — PWDWN = "L" CI — — — 15 pF CLOAD — — — 20 pF Min. Typ. Max. Unit — 30 — dB — — 23 ms — — 31 ms Echo Canceler Characteristics (Refer to Characteristics Diagram) Parameter Symbol Condition RIN = –10 dBm0 (5 kHz band white noise) Echo Attenuation LRES E. R. L. (echo return loss) = 6 dB TD = 20 ms ATT, GC, NLP: OFF Cancelable Echo Delay Time for a Single Chip or a Master Chip in a TD Cascade Cancelable Echo Delay Time for a Slave Chip in a Cascade RIN = –10 dBm0 (5 kHz band white noise) E. R. L. = 6 dB TDS ATT, GC, NLP: OFF 11/29 ¡ Semiconductor MSM7602 AC Characteristics (Ta = –40˚C to +85˚C) Parameter Symbol VDD = 2.7 V to 3.6 V Min. Typ. Max. VDD = 4.5 V to 5.5 V Min. Typ. Max. Unit — 19.2 — — 19.2 — 17.5 — 20 17.5 — 20 — 52.08 — — 52.08 — 50 — 57.14 50 — 57.14 tDMC 40 — 60 40 — 60 ns tMCH 20.8 — 31.3 20.8 — 31.3 ns tMCL 20.8 — 31.3 20.8 — 31.3 ns Clock Rise Time tr — — 5 — — 5 ns Clock Fall Time tf — — 5 — — 5 ns tDCM — — 30 — — 30 ns fCO — 256 — — 256 — kHz Internal Sync Clock Output Cycle Time tCO — 3.9 — — 3.9 — ms Internal Sync Clock Duty Ratio tDCO — 50 — — 50 — % Internal Sync Signal Output Delay Time tDCC — — 5 — — 5 ns Internal Sync Signal Period tCYO — 125 — — 125 — ms Internal Sync Signal Output Width tWSO — tCO — — tCO — ms Transmit/receive Operation Clock Frequency fSCK 64 — 2048 64 — 2048 kHz Transmit/receive Sync Clock Cycle Time tSCK 0.488 — 15.6 0.488 — 15.6 ms Transmit/receive Sync Clock Duty Ratio tDSC 40 50 60 40 50 60 % Transmit/receive Sync Signal Period tCYC 123 125 — 123 125 — ms tXS 45 — — 45 — — ns tSX 45 — tCYC-tSCK 45 — tCYC-tSCK ns Clock Frequency When Internal Sync Signal is not used Clock Cycle Time When Internal Sync Signal is not used Clock Duty Ratio Clock "H" Level Pulse Width fc = 19.2 MHz Clock "L" Level Pulse Width fc = 19.2 MHz Sync Clock Output Time Internal Sync Clock Frequency Sync Timing fC tMCK MHz ns tWSY tSCK — — tSCK — — ms Receive Signal Setup Time tDS 45 — — 45 — — ns Receive Signal Hold Time tDH 45 — — 45 — — ns Receive Data Input Time tID — 7tSCK — — 7tSCK — ms IRLD Signal Output Delay Time tDIC — — 138 — — 138 ns IRLD Signal Output Width tWIR — tSCK — — tSCK — ms tSD — — 90 — — 90 ns Sync Signal Width Serial Output Delay Time tXD — — 90 — — 90 ns Reset Signal Input Width tWR 1 — — 1 — — ms Reset Start Time tDRS 5 — — 5 — — ns Reset End Time tDRE — — 52 — — 52 ns Processing Operation Start Time tDIT 100 — — 100 — — ms 12/29 ¡ Semiconductor MSM7602 AC Characteristics (Continued) (Ta = –40˚C to +85˚C) Parameter Symbol VDD = 2.7 V to 3.6 V VDD = 4.5 V to 5.5 V Unit Min. Typ. Max. Min. Typ. Max. tDPS — — 111 — — 111 ns Power Down End Time tDPE — — 15 — — 15 ns Control Pin Setup Time (INT) tDTS 20 — — 20 — — ns Control Pin Hold Time (INT) tDTH 120 — — 120 — — ns Control Pin Setup Time (RST) tDSR 20 — — 20 — — ns Control Pin Hold Time (RST) tDHR 10 — — 10 — — ns Parallel Data Output Signal Width tWPD — 2tMCK — — 2tMCK — ns Flag Signal Output Time tDF — tMCK — — tMCK — ns Flag Signal Output Width tWFO — tMCK/2 — — tMCK/2 — ns Flag Signal Input Width tWFI — tWFO — — tWFO — ns Data Read Setup Time tFS — 20 — — 20 — ns Data Read Hold Time fFH — 10 — — 10 — ns Power Down Start Time 13/29 ¡ Semiconductor MSM7602 TIMING DIAGRAM Clock Timing fC, tMCK, tDMC tMCH tr tMCL tf X1/CLKIN tDCM tDCM SCKO tDCO fCO, tCO SCKO tDCC tDCC tCYO SYNCO tWSO Serial Input Timing fSCK, tSCK tDSC SCK tSX tXS tCYC SYNC tWSY tDH tDS SIN RIN MSB 7 6 5 4 3 2 LSB 0 1 MSB 7 tID tDIC tDIC IRLD tWIR 14/29 ¡ Semiconductor MSM7602 Serial Output Timing fSCK, tSCK tDSC SCK tSX tXS SYNC tCYC , tWSY tXD tSD tXD SOUT ROUT High-Z MSB 7 6 5 4 3 2 1 tXD LSB High-Z 0 MSB 7 Operation Timing After Reset tWR RST *Reset timing can be asynchronous tDIT tDRS tDRE Internal operaion Reset Initialization Processing Start Note: INT is invalid in the diagonally shaded interval. Power Down Timing PWDWN tDPS Internal Operation Power Down tDPE Processing Start 15/29 ¡ Semiconductor MSM7602 Control Pin Load-in Timing *tCYC INT(IRLD) tDTH tDTS *For IRLD output timing, refer to Serial Input Timing NLP, HCL, HD, ATT, ADP, GC tWR RST tDSR tDHR NLP, HCL, HD, ATT, ADP, GC Parallel Output Timing tWPD PD15 – High-Z High-Z Output Data PD 0 tDF tWFO OF1 OF2 Parallel Input Timing tWFI SF1 SF2 tFS tFH PD15 – Input Data PD 0 16/29 ¡ Semiconductor MSM7602 HOW TO USE THE MSM7602 The MSM7602 cancels (based on the RIN signal) the echo which returns to SIN. Connect the base signal to the R side and the echo generated signal to the S side. Connection Methods According to Echos Example 1: Canceling acoustic echo (to handle acoustic echo from line input) MSM7602 ROUT Acoustic echo RIN AFF CODEC + SIN Example 2: H CODEC – Line input SOUT + Canceling line echo (to handle line echo from microphone input) MSM7602 Microphone input RIN ROUT AFF CODEC – SOUT + H CODEC + SIN Line echo Example 3: Canceling line echo in a cascade connection (to handle line echo from microphone input) Microphone input RIN MSM7602 ROUT Master AFF CODEC SOUT – + CODEC + H H SIN Line echo PD0 - 15 Slave AFF 17/29 ¡ Semiconductor MSM7602 Example 4: Canceling of both acoustic echo and line echo (to handle both acoustic echo from line input and line echo from microphone input) MSM7602 SOUT + RIN – AFF Acoustic echo CODEC SIN Microphone input + – + SOUT CODEC AFF RIN Line input SIN + MSM7602 ROUT H ROUT Line echo For line echo For acoustic echo Control Pin Connection Example Single chip connection +5 V MS * * PD15 NLP * PD 0 HCL ADP ATT GC HD PWDWN RST INT IRLD SF1 * * OF1 SF2 * * OF2 – NLP HCL ADP ATT GC HD PWDWN RST Asterisk (*) indicates a pin only for the MSM7602-011 2-stage cascade connection Master + (slave ¥ 1) +5 V Slave chip MS PD15 NLP HCL PD 0 ADP ATT GC HD PWDWN RST INT IRLD OF1 SF1 OF2 SF2 – +5 V – NLP HCL ADP ATT GC HD PWDWN RST Master chip MS PD15 NLP HCL PD 0 ADP ATT GC HD PWDWN RST INT IRLD OF1 SF1 OF2 SF2 18/29 ¡ Semiconductor MSM7602 4-stage cascade connection Master + (slave ¥ 3) +5 V Slave chip 2 MS PD15 NLP HCL PD 0 ADP ATT GC HD PWDWN RST INT IRLD OF1 SF1 OF2 SF2 +5 V Slave chip 3 MS PD15 NLP HCL PD 0 ADP ATT GC HD PWDWN RST INT IRLD OF1 SF1 OF2 SF2 – +5 V Slave chip 1 MS PD15 NLP HCL PD 0 ADP ATT GC HD PWDWN RST INT IRLD OF1 SF1 OF2 SF2 – – NLP HCL ADP ATT GC HD PWDWN RST +5 V – Master chip MS PD15 NLP HCL PD 0 ADP ATT GC HD PWDWN RST INT IRLD OF1 SF1 OF2 SF2 Internal Clock Generator Circuit Example MSM7602 X1/CLKIN X2 XTAL : 19.2 MHz R : 1 MW C1 : 27 pF C2 : 27 pF R XTAL C1 C2 GND GND External Clock Input Circuit Example MSM7602 X1/CLKIN CLK X2 5pF GND 19/29 ¡ Semiconductor MSM7602 ECHO CANCELER CHARACTERISTICS DIAGRAM RIN input level vs. echo attenuation 40 40 30 30 Echo attenuation [dB] Echo attenuation [dB] ERL vs. echo attenuation 20 10 0 40 30 20 10 20 10 0 –10 0 –50 –40 –30 –20 –10 ERL [dB] RIN input level [dBm] 0 dBm = 2.2 dBm0 Measurement Conditions RIN input: 5 kHz band white noise Echo delay time TD = 20 ms ERL = 6 dB ATT, GC, NLP = OFF Power supply voltage 5 V Measurement Conditions RIN input = –10 dBm 5 kHz band white noise (0 dBm = 2.2 dBm0) Echo delay time TD = 20 ms ATT, GC, NLP = OFF Power supply voltage 5 V Echo delay time vs. echo attenuation Measurement Conditions RIN input = –10 dBm 5 kHz band white noise (0 dBm = 2.2 dBm0) 30 Echo attenuation [dB] 0 20 ERL = 6 dB ATT, GC, NLP = OFF The second through seventh chips are connected in a cascade. Power supply voltage 5 V 10 0 1 0 2 50 3 100 4 5 150 6 7chip 200 Echo delay time [ms] Note: The characteristics above are for the MSM7543 (VDD 5 V, m-law interface). The MSM7566 (VDD 3 V, m-law interface) provides the same characleristics without input and output levels. Refer to are PCM CODEC data sheet. MSM7543 (for both transmit and receive) 0 dBm0 = 0.6007 Vrms = –2.2 dBm (600 W) MSM7566 (for transmit side) 0 dBm0 = 0.35 Vrms = –6.9 dBm (600 W) (for receive side) 0 dBm0 = 0.5 Vrms = –3.8 dBm (600 W) 20/29 ¡ Semiconductor MSM7602 Measurement System Block Diagram White noise generator MSM7543 L. P. F. RIN 5 kHz A PCM m-law CODEC Level meter SOUT A PCM MSM7543 RIN ROUT MSM7602 SOUT SIN Power supply voltage 5 V PCM A m-law CODEC PCM A TD Delay Echo delay time ATT ERL (echo return loss) 21/29 ¡ Semiconductor MSM7602 APPLICATION CIRCUIT Bidirectional Connection Example Use the MSM7704-01GS-VK for PCM CODEC when VDD 3V. The MSM7533 and MSM7704 are pin compatible. Microphone input C1 2ch CODEC MSM7533VGS-K R1 R2 R3 DV Speaker output 21 AIN1 22 GSX1 4 AOUT1 13 12 15 10 16 19 5 6 DV For cancellation of acoustic echo MSM7602-001GS-K DV R4 8 SIN 13 ROUT 11 10 22 23 6 7 20 24 28 PWDWN RST DV SCK SYNCO SCKO INT IRLD PWDWN RST MCKO 4 VDD 19 V DD 27 V DD + R1 = 20 kW R2 = 20 kW R3 = 2.2 kW R4 = 10 kW R10 = 10 kW 1 2 3 5 26 16 25 17 R9 18 X2 VSS 14 VSS 15 VSS 21 NLP HCL ADP ATT GC HD WDT X1 C1 = 1 mF C2 = 10 mF C3 = 0.1 mF C4 = 0.1 mF Line input Line output R7 8 VDD 1 SGC AG C5 R6 DV 14 DOUT2 DIN2 11 DOUT1 DIN1 XSYNC RSYNC BCLK A/m PDN CHP AV + 18 C9 C10 C11 (AG) DG 9 DV DV R10 R11 For cancellation of line echo MSM7602-001GS-K DV DV C12 C13 X1 1 2 3 5 26 16 25 17 C14 18 14 15 21 SYNC SCK SYNCO SCKO INT IRLD PWDWN RST NLP HCL ADP ATT GC HD WDT X1 X2 VSS VSS VSS R8 11 10 22 23 6 7 20 24 28 4 VDD VDD 19 VDD 27 C2 C6 C3 C7 R5 = 20 kW R6 = 20 kW R7 = 2.2 kW R8 = 10 kW R11 = 10 kW DV 8 SIN 13 ROUT 12 SOUT 9 RIN 12 SOUT 9 RIN SYNC R5 24 AIN2 GSX2 23 2 AOUT2 C5 = 1 mF C6 = 10 mF C7 = 0.1 mF C8 = 0.1 mF DV + C9 = 0.1 mF C10 = 10 mF C11 = 0.1 mF R9 = 1 MW C12 = 27 pF C13 = 27 pF X1 = 19.2 MHz C14 = 5 pF 22/29 R3 C2 + R12 C3 R1 R2 C9 PWI SGC 16 AG 8V DD 24 C12 C11 1 SG 3 AOUT– 5 22 AIN– 10 13 12 15 11 14 9 C4 X1 DG TMC 19 PDM XSYNC RSYNC BCLOCK PCMIN PCMOUT + MSM7543GS-VK R4 23 AIN + 6 VFRO 21 GSX R5 Master 1 2 3 4 5 40 28 37 36 31 R11 32 33 41 42 55 54 51 14 21 X2 VDD VDD VDD VDD VDD VSS VSS VSS MSM7602-011GS-2K 12 9 45 44 30 29 27 26 25 24 23 22 20 19 18 17 16 15 53 47 48 52 6 7 46 MCKO 39 WDT 35 VSS 49 VSS SOUT RIN PD15 PD14 PD13 PD12 PD11 PD10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 OF2 SF2 OF1 SF1 INT IRLD 56-Pin QFP NLP HCL ADP MS ATT GC HD SCKO SYNCO X1 38 RST 34 PWDWN 8 SIN 13 ROUT 10 SCK 11 SYNC SOUT RIN PD15 PD14 PD13 PD12 PD11 PD10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 OF2 SF2 OF1 SF1 INT IRLD 8 SIN 13 ROUT 10 SCK 11 SYNC X2 VDD VDD VDD VDD VDD VSS VSS VSS NLP HCL ADP MS ATT GC HD SCKO SYNCO X1 32 33 41 42 55 54 51 14 21 1 2 3 4 5 40 28 37 36 31 38 RST 34 PWDWN Slave 56-Pin QFP 46 MCKO 39 WDT 35 VSS 49 VSS 12 9 45 44 30 29 27 26 25 24 23 22 20 19 18 17 16 15 53 47 48 52 6 7 MSM7602-011GS-2K RST PWDWN ROUT SIN C1 XSYNC RSYNC BCLOCK PCMIN PCMOUT + C8 C13 9 DG 1 24 16 C10 + C6 C7 R13 R6 RIN SOUT When VDD is 3 V, use the MSM7566 for PCM CODEC. The MSM7543 and MSM7566 are pin compatible. R7 > 20 kW R8 > 20 kW R9 = 2.2 kW R10 = 10 kW R12 = 0-22 W R13 = 0-22 W C6 = 10 mF C7 = 0.1 mF C8 = 10 mF C9 = 0.1 mF C10 = 0.1 mF R8 R7 C5 R11 = 1 MW C13 = 5 pF C11 = 27 pF C12 = 27 pF X1 = 19.2 MHz R1 > 50 kW R2 > 20 kW R3 > 20 kW R4 = 2.2 kW R5 = 10 kW R6 > 50 kW C1 = 0.1 mF C2 = 10 mF C3 = 0.1 mF C4 = 10 mF C5 = 0.1 mF AG VDD 8 SGC 3 AOUT– 5 PWI SG AIN 22 23 6 GSX 21 VFRO AIN+ MSM7543GS-VK 10 PDM 19 TMC 13 12 15 11 14 R9 R10 ¡ Semiconductor MSM7602 Cascade Connection Example 23/29 ¡ Semiconductor MSM7602 NOTES ON USE 1. Set echo return loss (ERL) to be attenuated. If the echo return loss is set to be amplified, the echo can not be eliminated. Refer to the characteristics diagram for ERL vs. echo attenuation quantity. 2. Set the level of the analog input so that the PCM CODEC does not overflow. 3. The recommended input level is –10 to –20 dBm0. Refer to the characteristics diagram for the RIN input level vs. echo attenuation quantity. 4. Applying the tone signal to this echo canceler for long duration may decrease echo attenuation. When used with the HD pin "L" (howling detector ON), this echo canceler may operate faultily if, while a signal is input to the RIN pin, a tone signal with a higher level than the signal being input to RIN is input to the SIN pin. A signal should therefore be input either to the RIN pin or to the SIN pin. If, however, the tone signal is input to the SIN pin while a signal is input to the RIN pin, the ADP, HD, or HCL pin must be set to "H". 5. For changes in the echo path (retransmit, circuit switching during transmission, and so on), convergence may be difficult. Perform a reset, to make it converge. If the state of the echo path changes after a reset, convergence may again be difficult. In cases such as a change in the echo path, perform a reset each time. 6. When turning the power ON, set the PWDWN pin to "1" and input the basic clock simultaneously with power ON. If powering down immediately after power ON, be sure fast input 10 or more clocks of the basic clock. 7. After powering ON, be sure to reset. 8. After the power down mode is released (when the PWDWN pin is changed to "H" from "L"), be sure to reset the device. 9. If this canceler is used to cancel acoustic echoes, an echo attenuation may be less than 30 dB. 24/29 ¡ Semiconductor MSM7602 EXPLANATION OF TERMS Attenuating Function : This function prevents howling and controls the noise level with the attenuator for the RIN input and SOUT output. Refer to the explanation of pins (ATT pin). Echo Attenuation : If there is talking (input only to RIN) in the path of a rising echo arises, the echo attenuation refers to the difference in the echo return loss (canceled amount) when the echo canceler is not used and when it is used. Echo attenuation = (SOUT level during through mode operation) – (SOUT level during echo canceler operation) [dB] Echo Delay Time : This is the time from when the signal is output from ROUT until it returns to SIN as an echo. Acoustic Echo : When using a hands free phone, and so on, the signal output from the speaker echoes and is input again to the microphone. The return signal is referred to as acoustic echo. Telephone Line Echo : This is a signal which is delayed midway in a telephone line and returns as an echo, due to reasons such as a hybrid impedance mismatch. Gain Control Function : This function prevents howling and controls the sound level with a gain controller for the RIN input. Refer to the explanation of pins (GC pin). Center Clipping Function : This function forces the SOUT output to a minimum value when the signal is below –57 dBm0. Refer to the explanation of pins (NLP pin). Double Talk Detection : Double talk refers to a state in which the SIN and RIN signals are input simultaneously. In a double talk state, a signal outside the echo signal which is to be canceled can be input to the SIN input, resulting in misoperation. The double talk detector prevents such misoperation of the canceler. Howling Detection : This is the oscillating state caused by the acoustic coupling between the loud speaker and the microphone during hands free talking. Howling not only interferes with talking, but can also cause in misoperation of the echo canceler. The howling detector prevents such misoperation and prevents howling. Echo Return Loss (ERL) : When the signal output from ROUT returns to SIN as an echo, ERL refers to how much loss there is in the signal level during ROUT. ERL = (ROUT level) – (SIN level of the ROUT signal which returns as an echo) [dB] If ERL is positive (ROUT > SIN), the system is an attenuator system. If ERL is negative (ROUT < SIN), the system is an amplifier system. PHS : Personal Handy Phone System. 25/29 ¡ Semiconductor APPENDIX MSM7602 Differences Between the MSM7602 and the MSM7520/7620 Introduction The MSM7602 is the improved version of the MSM7520 with improved usage. Thus, there are no differences in echo canceling characteristics. Enhancements • A new clock frequency of 19.2 MHz. The basic clock frequency of the MSM7520/7620 was 18 or 38 MHz, while the basic clock frequency of MSM7602 is 19.2 MHz. (MSM7602 can be applied at a frequency of 18 MHz. However, external SYNC and SCK are required because the periods of SYNCO and SCKO are varied.) • Adoption of full-fledged 8-bit data through-mode In the through-mode for the MSM7520 (HCL pin: "H"), an internally processed PCM signal was used. Therefore, only the negative minimum value (7FHEX) was converted into the corresponding positive minimum value (FFHEX). Analog to analog conversion causes no problem since both values are the minimum ones, but data transfer in the through-mode encounters problems. Hence, in the MSM7620/7602, the complete data trough-mode has been implemented. • Control of input timing to control pins (NLP, HCL, ADP, ATT and GC) In MSM7520, asynchronous changes in a control pin may result in malfunctioning. This problem stems from the fact that information on control pins is checked several times during the execution of a program over one cycle and the state of a control pin is changed between the first and second half periods. The MSM7620/7602 provides an internal circuit for using an INT signal to hold control pin information for one cycle. Thus, external timing control is not needed. The howling detector control pin (HD) is added. The MSM7602 can prevent the false detection of the howling detecter cause by tone signals by providing the howling detecter control pins. • Introduction of 256 kHz internal clock output (SCKO) for PCM transmission Internal sync signals (SYNCO and SCKO) in MSM7520/7620 are rated at 8 kHz and 200 kHz, respectively. At a frequency of 8 kHz, PCM multiplexing can be applied to no more than three channels. In the MSM7602, SCKO is rated at 256 kHz, while SYNCO at 8 kHz. Thus, PCM multiplexing can be applied with up to four channels. • Addition of basic clock output The use of a crystal oscillator for a clock in the MSM7520/7620 requires an oscillating circuit installed in each of two or more cascade-connected IC chips. Since the MSM7602 supports basic clock output, only one IC chip requires an oscillating circuit. (The MSM7602-001TS-K does not provide the basic clock output.) 26/29 ¡ Semiconductor MSM7602 • Small-sized package MSM7602 MSM7602-001GS-K :28-pin SSOP MSM7602-011GS-2K :56-pin QFP MSM7520 : 14.0 ¥ 14.0 ¥ 3.75 mm MSM7620 : 14.0 ¥ 14.0 ¥ 2.1 mm • Supply voltage rated at 3 volts MSM7520/7620 4.5 V to 5.5 V MSM7602 2.7 V to 5.5 V Package code Package size (mm) :SSOP28-P-485-0.65-K :9.5 ¥ 10.5 ¥ 1.85 :QFP56-P-910-0.65-2K :9.5 ¥ 10.5 ¥ 1.85 5 V typ. 3.3 V or 5 V typ. 27/29 ¡ Semiconductor MSM7602 PACKAGE DIMENSIONS (Unit : mm) SSOP28-P-485-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.39 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 28/29 ¡ Semiconductor MSM7602 (Unit : mm) QFP56-P-910-0.65-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 29/29