TI SN54ALS534J

SN54ALS534A, SN74ALS534A, SN74AS534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JULY 1996
SN54ALS534A . . . J PACKAGE
SN74ALS534A, SN74AS534 . . . DW OR N PACKAGE
(TOP VIEW)
3-State Bus Driving Inverting Outputs
Buffered Control Inputs
Package Options Include Plastic
Small-Outline (DW), Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) 300-mil DIPs
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
description
These octal D-type edge-triggered flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively lowimpedance loads. They are particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
1D
1Q
2D
2Q
3Q
3D
4D
4
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
3
8Q
SN54ALS534A . . . FK PACKAGE
(TOP VIEW)
On the positive transition of the clock (CLK) input,
the Q outputs are set to the complement of the
logic states set up at the data (D) inputs. The
’ALS534A and SN74AS534 have inverted outputs, but otherwise are functionally equivalent to
the ’ALS374A and SN74AS374.
OE
VCC
D
D
D
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are off.
The SN54ALS534A is characterized for operation over the full military temperature range of – 55°C to 125°C.
The SN74ALS534A and SN74AS534 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
CLK
D
L
↑
H
L
L
↑
L
H
L
H or L
X
Q0
H
X
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ALS534A, SN74ALS534A, SN74AS534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JULY 1996
logic symbol†
1
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
11
3
logic diagram (positive logic)
OE
EN
C1
1D
CLK
2
4
5
7
6
8
9
13
12
14
15
17
16
18
19
1
11
C1
1Q
2Q
1D
3
C1
5Q
2D
4
5
2Q
1D
6Q
C1
7Q
8Q
3D
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
7
8
5D
6D
7D
8D
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
12
5Q
15
6Q
16
7Q
1D
C1
18
4Q
1D
C1
17
9
1D
C1
14
3Q
1D
C1
13
6
1D
C1
4D
2
1Q
1D
3Q
4Q
2
1D
19
8Q
SN54ALS534A, SN74ALS534A, SN74AS534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JULY 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA: SN54ALS534A . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74ALS534A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS534A
SN74ALS534A
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.7
0.8
High-level output current
–1
– 2.6
mA
IOL
fclock
Low-level output current
12
24
mA
35
MHz
tw
tsu
Pulse duration, CLK high or low
th
TA
Hold time, data after CLK↑
High-level input voltage
2
Clock frequency
2
0
Setup time, data before CLK↑
Operating free-air temperature
30
V
V
0
V
16.5
14
ns
10
10
ns
0
0
– 55
125
ns
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 0.4 mA
5V
VCC = 4
4.5
IOH = – 1 mA
IOH = – 2.6 mA
VOL
VCC = 4
4.5
5V
IOL = 12 mA
IOL = 24 mA
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.4 V
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
VCC = 5
5.5
5V
V,
VI = 0
0.4
4V
VCC = 5.5 V,
VO = 2.25 V
Outputs high
VOH
IIL
IO§
ICC
CLK, OE
D
VCC = 5.5 V
SN54ALS534A
MIN TYP‡
MAX
SN74ALS534A
MIN TYP‡
MAX
– 1.5
VCC – 2
2.4
– 1.5
V
VCC – 2
V
3.3
2.4
0.25
– 20
Outputs low
UNIT
0.4
3.2
0.25
0.4
0.35
0.5
V
µA
20
20
– 20
– 20
µA
0.1
0.1
mA
20
20
µA
– 0.1
– 0.1
– 0.2
– 0.2
– 112
– 30
– 112
11
19
11
19
19
28
19
28
mA
mA
mA
Outputs disabled
10
31
20
31
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
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• DALLAS, TEXAS 75265
3
SN54ALS534A, SN74ALS534A, SN74AS534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JULY 1996
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†
SN54ALS534A
MIN
fmax
tPLH
UNIT
SN74ALS534A
MAX
MIN
30
MAX
35
MHz
3
17
3
12
4
18
4
16
3
19
3
17
4
20
4
18
1
12
1
OE
Any Q
tPLZ
1
25
2
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
10
tPHL
tPZH
tPZL
tPHZ
CLK
An Q
Any
OE
An Q
Any
14
ns
ns
ns
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA: SN74AS534 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature rang, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN74AS534
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
– 15
mA
IOL
fclock
Low-level output current
48
mA
125
MHz
High-level input voltage
2
Clock frequency
0
CLK high
4
CLK low
3
V
V
tw
Pulse duration
tsu
th
Setup time, data before CLK↑
2
ns
Hold time, data after CLK↑
2
ns
TA
Operating free-air temperature
0
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
70
°C
SN54ALS534A, SN74ALS534A, SN74AS534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JULY 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
SN74AS534
TYP†
MAX
TEST CONDITIONS
MIN
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 2 mA
VCC = 4.5 V,
VCC = 4.5 V,
IOH = – 15 mA
IOL = 48 mA
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VI = 0.4 V
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
VCC = 5
5.5
5V
V,
VI = 0
0.4
4V
IO‡
VCC = 5.5 V,
VO = 2.25 V
Outputs high
77
120
ICC
VCC = 5.5 V
Outputs low
84
128
Outputs disabled
84
128
VOH
VOL
IOZH
IOZL
II
IIH
IIL
OE, CLK
D
– 1.2
VCC – 2
2.4
V
V
3.3
0.34
0.5
V
50
µA
– 50
µA
0.1
mA
20
µA
– 0.5
–2
– 30
UNIT
– 112
mA
mA
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX§
SN74AS534
MIN
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
MAX
125
CLK
An Q
Any
OE
An Q
Any
OE
Any Q
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MHz
3
8
4
9
2
6
3
10
2
6
tPLZ
2
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
UNIT
6
ns
ns
ns
5
SN54ALS534A, SN74ALS534A, SN74AS534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS168B – APRIL 1982 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
[3.5 V
3.5 V
tPHZ
VOL
0.3 V
0.3 V
[0 V
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
1.3 V
1.3 V
Input
1.3 V
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
VOH
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
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• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN54ALS534J
OBSOLETE
CDIP
J
20
TBD
Call TI
SN74ALS534ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS534ADWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS534ADWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS534ADWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS534AN
ACTIVE
PDIP
N
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS534AN3
OBSOLETE
PDIP
N
20
TBD
Call TI
SN74ALS534ANE4
ACTIVE
PDIP
N
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS534ANSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS534ANSRE4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS534DW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN74AS534DWR
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN74AS534N
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
SNJ54ALS534FK
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
SNJ54ALS534J
OBSOLETE
CDIP
J
20
TBD
Call TI
Call TI
20
20
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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