TMDS341A www.ti.com SLLS702 – MAY 2006 3-TO-1 DVI/HDMI SWITCH FEATURES • • • • • • • • Differential Interface Compatible with Transition Minimized Differential Signaling (TMDS) Electrical Specification Allows AC-Coupled Input Designed for Signaling Rates up to 1.65 Gbps in Support of 480 I/P, 720 I/P, 1080 I/P or UXGA Resolutions Each Port Supports HDMI or DVI Inputs Isolated Digital Display Control (DDC) Bus for Unused Ports 5-V Tolerance to all DDC and HPD_SINK Inputs Integrated Receiver Termination Inter-Pair Output Skew < 100 ps • • • • • • • Intra-Pair Skew < 50 ps 8-dB Receiver Equalization to Compensate for 5-m DVI Cable Losses High Impedance Outputs When Disabled HBM ESD Protection Exceeds 3 kV 3.3-V Supply Operation 80-Pin TQFP Package ROHS Compatible and 260°C Reflow Rated APPLICATIONS • • • • Switching From Three Digital-Video (DVI) or Digital-Audio Visual (HDMI) Sources Digital TV Digital Projector Audio Video Receiver DESCRIPTION The TMDS341A is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug detector, and an I2C interface are supported on each port. Each TMDS channel allows signaling rates up to 1.65 Gbps. The active source is selected by configuring source selectors, S1, S2, and S3. The selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I2C interface of the selected input port is linked to the I2C interface of the output port, and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused ports, the I2C interfaces are isolated, and the HPD pins are kept low. Termination resistors (50-Ω), pulled up to VCC, are integrated at each receiver input pin. External terminations are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard. When the output is connected to a standard TMDS termination and OE is high, the output is high impedance. The TMDS341A provides fixed 8-dB input equalization and selectable 3-dB output de-emphasis to optimize system performance through 5-meter or longer DVI compliant cables. The device is characterized for operation from 0°C to 70°C. TYPICAL APPLICATION DVD Player Digital TV PC or Game Machine TMDS 341A STB Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TMDS341A www.ti.com SLLS702 – MAY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM A14 B14 A13 B13 A12 B12 A11 B11 VCC (3.3 V) RINT Rx w/ EQ RINT Rx w/ EQ RINT Rx w/ EQ RINT Rx w/ EQ PRE VSADJ VCC (3.3 V) RINT A24 B24 Y4 Rx w/ EQ VCC RINT 3−to−1 MUX TMDS Drive Z4 A23 B23 Rx w/ EQ Y3 VCC TMDS Drive RINT A22 B22 Z3 Rx w/ EQ VCC RINT Y2 A21 TMDS Drive Rx w/ EQ B21 Z2 VCC (3.3 V) RINT Y1 A34 B34 TMDS Drive Rx w/ EQ Z1 VCC RINT OE A33 B33 Rx w/ EQ VCC S1 RINT S2 A32 B32 Rx w/ EQ S3 VCC RINT A31 B31 Rx w/ EQ HPD1 HPD2 Control Logic HPD_SINK HPD3 SCL1 SCL_SINK SDA1 SDA_SINK SCL2 SDA2 SCL3 SDA3 2 Submit Documentation Feedback TMDS341A www.ti.com SLLS702 – MAY 2006 NC V CC HP D3 SD A 3 S C L3 GN D B 31 A 31 B 32 VCC A 32 GN D B 33 A 33 B 34 OE 60 59 58 VCC A 34 GN D NC PFC PACKAGE (TOP VIEW) 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 GND GND 65 36 GND GND 66 35 Z1 B21 67 34 Y1 A21 68 33 V CC VCC 69 32 Z2 B22 70 31 Y2 A22 71 30 GND GND 72 29 Z3 B23 73 28 Y3 A23 74 27 V CC VCC 75 26 Z4 B24 76 25 Y4 A24 77 24 GND GND 78 23 S3 VCC 79 22 S2 HPD1 80 21 S1 Submit Documentation Feedback 20 NC 14 15 16 17 18 19 PR E 10 11 12 13 VSADJ 9 VC C 8 GND 7 A14 6 B1 4 5 VC C 4 A1 3 3 B1 3 2 C 1 GND 37 B1 2 64 A1 2 SCL_SINK SCL2 A1 1 38 VC 63 B1 1 SDA_SINK SDA2 GND HPD_SINK 39 SC L 1 40 62 NC 61 HPD2 SD A 1 VCC 3 TMDS341A www.ti.com SLLS702 – MAY 2006 TERMINAL FUNCTIONS TERMINAL NAME I/O DESCRIPTION A11, A12, A13, A14 6, 9, 12, 15 I Port 1 TMDS positive inputs A21, A22, A23, A24 68, 71, 74, 77 I Port 2 TMDS positive inputs A31, A32, A33, A34 49, 52, 55, 58 I Port 3 TMDS positive inputs B11, B12, B13, B14 5, 8, 11, 14 I Port 1 TMDS negative inputs B21, B22, B23, B24 67, 70, 73, 76 I Port 2 TMDS negative inputs B31, B32, B33, B34 48, 51, 54, 57 I Port 3 TMDS negative inputs GND 4, 10, 16 24, 30, 36, 37, 47, 53, 59, 65, 66, 72, 78 HPD1 80 O Port 1 hot plug detector output HPD2 62 O Port 2 hot plug detector output HPD3 44 O Port 3 hot plug detector output HPD_SINK 40 I Sink side hot plug detector input High: 5-V power signal asserted from source to sink and EDID is ready Low: No 5-V power signal asserted from source to sink, or EDID is not ready Ground NC 1, 20, 41,60 OE 42 I Output enable, active low PRE 19 I Output de-emphasis adjustment High: 3 dB Low: 0 dB SCL1 3 I/O Port 1 DDC bus clock line SCL2 64 I/O Port 2 DDC bus clock line SCL3 46 I/O Port 3 DDC bus clock line SCL_SINK 38 I/O Sink side DDC bus clock line SDA1 2 I/O Port 1 DDC bus data line SDA2 63 I/O Port 2 DDC bus data line SDA3 45 I/O Port 3 DDC bus data line SDA_SINK 39 I/O Sink side DDC bus data line S1, S2, S3 21, 22, 23 I VCC VSADJ 4 NO. No connect 7, 13, 17 27, 33, 43, 50, 56 61, 69, 75, 79 Source selector input Power supply 18 I TMDS compliant voltage swing control Y1, Y2, Y3, Y4 34, 31, 28, 25 O TMDS positive outputs Z1, Z2, Z3, Z4 35, 32, 29, 26 O TMDS negative outputs Submit Documentation Feedback TMDS341A www.ti.com SLLS702 – MAY 2006 Table 1. Source Selection Lookup CONTROL PINS (1) (1) I/O SELECTED HOT PLUG DETECT STATUS S1 S2 S3 Y/Z SCL_SINK SDA_SINK HPD1 HPD2 HPD3 H x x A1/B1 SCL1 SDA1 HPD_SINK L L L H x A2/B2 SCL2 SDA2 L HPD_SINK L L L H A3/B3 SCL3 SDA3 L L HPD_SINK L L L None (Z) None (Z) L L L H: Logic high; L: Logic low; X: Don't care; Z: High impedance Submit Documentation Feedback 5 TMDS341A www.ti.com SLLS702 – MAY 2006 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS TMDS Input Stage TMDS Output Stage Vcc 25 Ω 25 Ω 50Ω Y Z 50Ω A B 10 mA Control Input Stage HPD output stage Vcc OE HPD_SINK PRE S1, S2, S3 Vcc HPD1 HPD2 HPD3 400Ω DDC pass gate Vcc SCL/SCA Source SCL/SCA Sink 8V 8V ORDERING INFORMATION (1) (1) 6 PART NUMBER PART MARKING PACKAGE TMDS341APFC TMDS341A 80-PIN TQFP TMDS341APFCR TMDS341A 80-PIN TQFP Tape/Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Submit Documentation Feedback TMDS341A www.ti.com SLLS702 – MAY 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range, VCC (2) –0.5 V to 4 V Anm (3), Bnm Voltage range 2.5 V to 4 V Ym, Zm, VSADJ, PRE, Sn, OE, HPDn –0.5V to 4 V SCLn, SCL_SINK, SDAn, SDA_SINK, HPD_SINK –0.5 V to 6 V Anm, Bnm Human body model (4) Electrostatic discharge 5 kV All pins 4 kV Charged-device model (5) (all pins) 1000 V (6) 250 V Machine model (all pins) See Dissipation Rating Table Continuous power dissipation (1) (2) (3) (4) (5) (6) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. n = 1, 2, 3; m = 1, 2, 3, 4 Tested in accordance with JEDEC Standard 22, Test Method A114-B Tested in accordance with JEDEC Standard 22, Test Method C101-A Tested in accordance with JEDEC Standard 22, Test Method A115-A DISSIPATION RATINGS (1) PACKAGE TA ≤ 25°C 80-TQFP 1342 mW DERATING FACTOR ABOVE TA = 25°C (1) TA = 70°C POWER RATING 13.42 mW/°C 738 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VCC Supply voltage 3 3.3 3.6 UNIT V TA Operating free-air temperature 0 70 °C TMDS DIFFERENTIAL PINS (A/B) VID Receiver peak-to-peak differential input voltage VIC Input common mode voltage RVSADJ Resistor for TMDS compliant voltage swing range AVCC TMDS output termination voltage, see Figure 1 RT Termination resistance, see Figure 1 Signaling rate 150 1560 VCC–0.4 VCC+0.01 mVp-p V 4.6 4.64 4.68 kΩ 3 3.3 3.6 V 45 50 55 Ω 0 1.65 Gbps CONTROL PINS (PRE; S, OE) VIH LVTTL High-level input voltage 2 VCC V VIL LVTTL Low-level input voltage GND 0.8 V GND 5.5 V DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) VI(DDC) Input voltage STATUS PINS (HPD_SINK) VIH LVTTL High-level input voltage 2 5.3 V VIL LVTTL Low-level input voltage GND 0.8 V Submit Documentation Feedback 7 TMDS341A www.ti.com SLLS702 – MAY 2006 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ICC Supply current VIH = VCC, VIL = VCC – 0.4 V, RVSADJ = 4.64 kΩ, RT = 50 Ω, AVCC = 3.3 V Am/Bm = 1.65 Gbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 165 MHz clock PD Power dissipation VIH = VCC, VIL = VCC – 0.4 V, RVSADJ = 4.64 kΩ, RT = 50 Ω, AVCC = 3.3 V Am/Bm = 1.65 Gbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 165 MHz clock MIN TYP (1) MAX UNIT 190 230 mA 394 657 mW TMDS DIFFERENTIAL PINS (A/B; Y/Z) VOH Single-ended high-level output voltage AVCC–10 AVCC+10 mV VOL Single-ended low-level output voltage AVCC–600 AVCC–400 mV Vswing Single-ended output swing voltage 400 600 mV VOD(O) Overshoot of output differential voltage VOD(U) Undershoot of output differential voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states I(O)OFF Single-ended standby output current 0 V ≤ VCC ≤ 1.5 V, AVCC = 3.3 V, RT = 50 Ω |I(OS)| Short circuit output current See Figure 3 VODE(SS) Steady state output differential voltage with de-emphasis VODE(pp) Peak-to-peak output differential voltage See Figure 4, PRE = VCC, Am/Bm = 250 Mbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 25 MHz clock VI(open) Single-ended input voltage under high impedance input or open input II = 10 µA RINT Input termination resistance VIN = 2.9 V See Figure 2, AVCC = 3.3 V, RT = 50 Ω, PRE = 0 V 6% 15% 2× Vswing 12% 25% 2× Vswing 0.5 5 mV 10 µA 12 mA 560 840 mVp-p 800 1200 mVp-p VCC–10 VCC+10 –10 45 mV 50 55 Ω 2 µA DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) |Ilkg| Input leakage current VI = 0.1 VCC to 0.9 VCC to isolated DDC ports 0.1 CIO Input/output capacitance VI = 0 V 7.5 RON Switch resistance IO = 3 mA, VO = 0.4 V VPASS Switch output voltage VI = 3.3 V, IO = 100 µA 1.5 (2) pF 25 50 Ω 2.0 2.5 (3) V STATUS PINS (HPD) VOH(TTL) TTL High-level output voltage IOH = –8 mA VOL(TTL) TTL Low-level output voltage IOL = 8 mA 2.4 V 0.4 V CONTROL PINS (PRE, S, OE) |IIH| High-level digital input current VIH = 2 V or VCC 0.1 2 µA |IIL| Low-level digital input current VIL = GND or 0.8 V 0.1 2 µA VIH = 5.3 V 23 100 VIH = 2 V or VCC 0.1 2 VIL = GND or 0.8 V 0.1 2 STATUS PINS (HPD_SINK) |IIH| High-level digital input current |IIL| Low-level digital input current (1) (2) (3) 8 All typical values are at 25°C and with a 3.3-V supply. The value is tested in full temperature range at 3.0 V. The value is tested in full temperature range at 3.6 V. Submit Documentation Feedback µA µA TMDS341A www.ti.com SLLS702 – MAY 2006 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT TMDS DIFFERENTIAL PINS (Y/Z) tPLH Propagation delay time, low-to-high-level output 250 800 ps tPHL Propagation delay time, high-to-low-level output 250 800 ps tr Differential output signal rise time (20% - 80%) 75 240 ps tf Differential output signal fall time (20% - 80%) 75 240 ps tsk(p) Pulse skew (|tPHL– tPLH|) 7 50 ps tsk(D) Intra-pair differential skew, see Figure 5 23 50 ps tsk(o) Inter-pair channel-to-channel output skew (2) 100 ps tsk(pp) Part-to-part skew (3) 200 ps tjit(pp) Peak-to-peak output jitter from Y/Z(1) residual jitter 15 30 ps tjit(pp) Peak-to-peak output jitter from Y/Z(2:4) residual jitter 18 50 ps tPRE De-emphasis duration tSX Select to switch output ten Enable time tdis Disable time See Figure 2, AVCC = 3.3 V, RT = 50 Ω, PRE = 0 V See Figure 8, PRE = 0 V Am/Bm = 1.65 Gbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 165 MHz clock See Figure 4, PRE = VCC Am/Bm = 250 Mbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 25 MHz clock See Figure 6 240 (4) ps 6 10 ns 6 10 ns 6 10 ns 0.4 2.5 ns 2 6.0 ns 3 6.5 ns DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) tpd(DDC) Propagation delay from SCLn to SCL_SINK or SDAn to SDA_SINK or SDA_SINK to SDAn See Figure 7, CL = 10 pF CONTROL AND STATUS PINS (S, HPD_SINK, HPD) tpd(HPD) Propagation delay (from HPD_SINK to the active port of HPD) tsx(HPD) Switch time (from port select to the latest valid status of HPD) (1) (2) (3) (4) See Figure 7, CL = 10 pF All typical values are at 25°C and with a 3.3-V supply. tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of a device when inputs are tied together. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of two devices, or between channel 1 of two devices, when both devices operate with the same source, the same supply voltages, at the same temperature, and have identical packages and test circuits. The typical value is ensured by simulation. Submit Documentation Feedback 9 TMDS341A www.ti.com SLLS702 – MAY 2006 PARAMETER MEASUREMENT INFORMATION AVcc RT RT ZO = RT TMDS Driver TMDS Receiver ZO = RT Figure 1. Termination for TMDS Output Driver Vcc R R INT INT RT Y A VA TMDS Receiver VID TMDS Driver CL 0.5 pF B VB V ID VY AVcc RT Z = VA − VB Vswing = VY − VZ VZ VA VB DC Coupled Vcc AC Coupled Vcc+0.2 V Vcc−0.4 V Vcc−0.2 V 0.4 V VID V VID(pp) ID 0V −0.4 V t PHL t PLH 100% 80% V OD(O) 0V Differential VOD(pp) 20% 0% tf tr VOD(U) V OC VOC(SS) NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf < 100 ps, 100 MHz from Agilent 81250. CL includes instrumentation and fixture capacitance within 0.06 m of the D.U.T. Measurement equipment provides a bandwidth of 20 GHz minimum. Figure 2. Timing Test Circuit and Definitions 10 Submit Documentation Feedback TMDS341A www.ti.com SLLS702 – MAY 2006 PARAMETER MEASUREMENT INFORMATION (continued) 50 IOS TMDS Driver 50 + _ 0 V or 3.6 V Figure 3. Short Circuit Output Current Test Circuit 1 bit 1 to N bit VODE(SS) VOD(pp) 80% 20% t PRE Figure 4. De-Emphasis Output Voltage Waveforms and Duration Measurement Definitions VOH VY 50% VZ tsk(D) VOL Figure 5. Definition of Intra-Pair Differential Skew Submit Documentation Feedback 11 TMDS341A www.ti.com SLLS702 – MAY 2006 PARAMETER MEASUREMENT INFORMATION (continued) Input−1 Kept High A B Input−2/Input−3 A Kept Low B 3.3 V VCC 2 0V S1 Clocking S2 or S3 Kept High tsx Output tsx Y 75 mV Z −75 mV Hi−Z 75 mV −75 mV 3.3 V VCC 2 0V OE tdis ten Figure 6. TMDS Outputs Control Timing Definitions VCC 2 HPD_SINK VCC 2 0.4 V HPD1 tsx(HPD) tpd(HPD) tpd(HPD) 2.4 V HPD2 HPD3 0V S1 VCC 2 S2 S3 0V SDA_SINK VCC 2 tpd(DDC) tpd(DDC) VCC 2 SDA1 SDA2 SDA3 Figure 7. HPD Timing Definitions 12 Submit Documentation Feedback TMDS341A www.ti.com SLLS702 – MAY 2006 PARAMETER MEASUREMENT INFORMATION (continued) AVcc RT Data + Data − Video Patterm Generator Coax Coax SMA RX SMA EQ 5m 28AWG HDMI Cable 1000 mVpp Differential M U X + OUT 0dB <2” 50 Ω Transmission Line SMA <2” 50 Ω Transmission Line SMA Coax Coax Jitter Test Instrument TMDS341A AVcc RT Clk+ Clk− Coax Coax SMA RX M U X + SMA EQ OUT 0dB RT <2” 50 Ω Transmission Line SMA <2” 50 Ω Transmission Line SMA RT Coax Coax Jitter Test Instrument TP1 TP2 TP3 10-12 A. All jitters are measured in BER of B. The residual jitter reflects the total jitter measured at the TMDS341A output, TP3, subtract the total jitter from the signal generator, TP1 Figure 8. Jitter Test Circuit Figure 9 shows the frequency loss response from a 5m 28AWG HDMI cable and a 5m 28AWG DVI cable. The TMDS341A built-in passive input equalizer compensates for ISI. For an 8-dB loss HDMI cable, the TMDS341A typically reduces jitter by 60 ps from the device input to the device output. TMDS341 input equalization gain vs. 5m DVI/HDMI cable response 0 Inversed TMDS341 EQ Gain −2 −4 Gain − dB −6 28 AWG 5m HDMI Cable −8 −10 −12 28 AWG 5m DVI Cable −14 −16 −18 0 200 400 600 800 1000 1200 1400 1600 1800 2000 f − Frequency − MHz Figure 9. S-Parameter Plots of 5-m DVI and HDMI Cables Submit Documentation Feedback 13 TMDS341A www.ti.com SLLS702 – MAY 2006 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 230 195 VCC = AVCC = 3.3 V, TA = 25 C, 210 TP1 VID(PP) = 800 mVp-p, RVSADJ = 4.64 KW PRE = OE = Low Input (2:4) HDMI Data Pattern, 250 Mbps - 1.65 Gbps Input (1) Clock, 25 MHz - 165 MHz 200 190 180 VCC = AVCC = 3.3 V, TP1 VID(PP) = 800 mV, RVSADJ = 4.64 KW Input (2:4)1.65 Gbps HDMI Data Pattern Input (1) 165 Mhz Clock 193 ICC - Supply Current - mA ICC - Supply Current - mA 220 191 189 187 170 185 160 25 45 65 75 85 105 145 0 165 10 f - Frequency - MHz Figure 10. Figure 11. RESIDUAL DETERMINISTIC JITTER vs DATA RATE RESIDUAL PEAK-TO-PEAK JITTER vs CLOCK FREQUENCY VCC = AVCC = 3.3 V, TA = 25°C, VCC = AVCC = 3.3 V, TA = 25°C, TP1 VID(PP) = 800 mV, RVSADJ = 4.64 KW PRE = OE = Low, Source jitter = 180 ps 6 3 m HDMI Cable 1 m HDMI Cable 4 5 m HDMI Cable 2 0 200 250 450 650 750 850 1050 1250 1450 1650 Residual Peak-Peak Jitter - % Unit Interval Residual Deterministic Jitter - % Unit Interval 70 3 8 TP1 VID(PP) = 800 mVp-p, RVSADJ = 4.64 KW PRE = OE = Low, Source jitter = 150 ps 3 m HDMI Cable 2 1 m HDMI Cable 5 m HDMI Cable 1 0 20 Data Rate - Mbps 25 45 65 75 85 105 125 145 165 Clock Frequency - MHz Figure 12. 14 20 30 40 50 60 TA - Free-Air Temperature - C Figure 13. Submit Documentation Feedback TMDS341A www.ti.com SLLS702 – MAY 2006 TYPICAL CHARACTERISTICS (continued) RESIDUAL DETERMINISTIC JITTER vs DIFFERENTIAL INPUT VOLTAGE RESIDUAL PEAK-TO-PEAK JITTER vs DIFFERENTIAL INPUT VOLTAGE 4 9 270 Mbps 8 742.5 Mbps 7 6 1485 Mbps 5 4 3 2 1 0 VCC = AVCC = 3.3 V, TA = 25°C, -1 RVSADJ = 4.64 KW, PRE = OE = Low -2 -3 Residual Peak-Peak Jitter - % Unit Interval Residual Deterministic Jitter - % Unit Interval 10 550 750 12 11 1 0 -1 74.25 MHz -2 27 MHz -3 -4 -5 -6 -7 -8 VCC = AVCC = 3.3 V, TA = 25°C, -9 RVSADJ = 4.64 KW, PRE = OE = Low -10 950 1150 1350 1550 150 350 550 750 950 1150 1350 1550 Peak-to-Peak Differential Input Voltage - mVp-p Peak-to-Peak Differential Input Voltage - mVp-p Figure 14. Figure 15. RESIDUAL DETERMINISTIC JITTER vs FR4 PCB TRACE (at 3dB Pre-Emphasis) RESIDUAL PEAK-TO-PEAK JITTER vs FR4 PCB TRACE (at 3dB Pre-Emphasis) 4 VCC = AVCC = 3.3 V, TA = 25°C, Residual Peak-Peak Jitter - % Unit Interval Residual Deterministic Jitter - % Unit Interval 13 148.5 MHz 2 -11 150 350 15 14 3 TP1 VID(PP) = 800 mV, RVSADJ = 4.64 KW PRE = High, OE = Low, 5-m 28 AWG HDMI Cable 10 1485 Mbps 9 8 7 6 5 742.5 Mbps 4 3 2 270 Mbps 1 VCC = AVCC = 3.3 V, TA = 25°C, TP1 VID(PP) = 800 mV, RVSADJ = 4.64 KW PRE = High, OE = Low, 5-m 28 AWG HDMI Cable 3.5 2.5 148.5 MHz 2.0 74.25 MHz 0.5 27 MHz 0 0 5 7 11 15 19 5 FR4 PCB Trace - Inch Figure 16. 7 11 15 FR4 PCB Trace - Inch 19 Figure 17. Submit Documentation Feedback 15 TMDS341A www.ti.com SLLS702 – MAY 2006 TYPICAL CHARACTERISTICS (continued) HDMI Cables Running at 165-MHz Pixel Clock TP1 TP2 TP3 TMDS341A Test Board Video 28 AWG HDMI Cable TMDS 341 Format Generator Figure 18. 1-m and 5-m HDMI Cable Test Point Configuration 1-m Cable Length Eye Patterns 16 Figure 19. Clock at TP1 Figure 20. Clock at TP2 Figure 21. Clock at TP3 Figure 22. Data at TP1 Figure 23. Data at TP2 Figure 24. Data at TP3 Submit Documentation Feedback TMDS341A www.ti.com SLLS702 – MAY 2006 TYPICAL CHARACTERISTICS (continued) 5-m Cable Length Eye Patterns Figure 25. Clock at TP1 Figure 26. Clock at TP2 Figure 27. Clock at TP3 Figure 28. Data at TP1 Figure 29. Data at TP2 Figure 30. Data at TP3 (DC-Coupled Input) Figure 31. Data at TP3 (AC-Coupled Input) Submit Documentation Feedback 17 TMDS341A www.ti.com SLLS702 – MAY 2006 APPLICATION INFORMATION Supply Voltage All VCC pins can be tied to a single 3.3-V power source. A 0.01-µF capacitor is connected from each VCC pin directly to ground to filter supply noise. TMDS Inputs Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each input channel contains an 8-dB equalization circuit to compensate for cable losses. The voltage at the TMDS input pins must be limited per the absolute maximum ratings. An unused input should not be connected to ground as this would result in excessive current flow damaging the device. TMDS Input Fail-Safe TMDS input pins do not incorporate fail-safe circuits. An unused input channel can be externally biased to prevent output oscillation. One pin can be left open with the other grounded through a 1-kΩ resistor as shown in Figure 32. TMDS341A VCC RINT RINT RT A TMDS Receiver TMDS Driver B Y AVCC Z RT Figure 32. TMDS Input Fail-Safe Recommendation TMDS Outputs A 1% precision resister, 4.64-kΩ, connected from VSADJ to ground is recommended to allow the differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10-mA current sink capability, which provides a typical 500-mV voltage drop across a 50-Ω termination resistor. AVCC VCC TMDS341A ZO = RT TMDS Driver RT RT ZO = RT TMDS Receiver GND Figure 33. TMDS Driver and Termination Circuit As shown in Figure 33, if VCC (TMDS341A supply) and AVCC (sink termination supply) are powered, the TMDS output signals are high impedance when OE is high. Normal operation is with both supplies active. Also shown in Figure 33, if VCC is on and AVCC is off, the TMDS outputs source a typical 5-mA current through each termination resistor to ground. The terminations consume a total of 10 mW of power independent of the OE logical selection. When AVCC is powered on, normal operation (OE controls output impedance) is resumed. 18 Submit Documentation Feedback TMDS341A www.ti.com SLLS702 – MAY 2006 APPLICATION INFORMATION (continued) When the power source of the device, VCC, is off and the power source to termination, AVCC, is on, the output leakage current (Io(off)) specification ensures leakage current is limited to 10-µA or less. The PRE pin provides 3-dB de-emphasis, allowing output signal pre-conditioning to offset interconnect losses from the TMDS341A outputs to a TMDS receiver. PRE is recommended to be low to the circuit design of a stand-alone switch box. HPD Pins The input of the HPD_SINK is 5-V tolerant, allowing direct connection to 5-V signals. The HPD pin output resistance is 35-Ω typically. A 1-kΩ 10% resistor is recommended to be connected from an HPD pin at the TMDS341A to the HPD pin of the HDMI connector. DDC Channels The DDC channels are designed with a bi-directional pass gate, providing 5-V signal tolerance. The 5-V tolerance allows direct connection to a standard I2C bus. The level shifter between 3.3 V and 5 V I2C interface can be eliminated. Configuring the TMDS341A as a 2:1 Switch The TMDS341A can be configured as a 2-to-1 switch by pulling the source selector pin (S1, S2, S3) of the non-active port low and leaving the corresponding TMDS inputs, SCL, SDA, and HPD pins open. Layout Considerations The high-speed TMDS inputs are the most critical paths for the TMDS341A. There are several considerations to minimize discontinuities on these transmission lines between the connectors and the device: • Maintain 100-Ω differential transmission line impedance into and out of the TMDS341A • Keep an uninterrupted ground plane beneath the high-speed I/Os • Keep the ground-path vias to the device as close as possible to allow the shortest return current path • Layout of the TMDS differential inputs should be with the shortest stubs from the connectors Connecting Cables Longer Than 5 m When using the TMDS341A with cables longer than 5 m, the impact to the TMDS signal path as well as the DDC signal path must be considered. TMDS Signal Path The TMDS341A receiver equalization circuit provides the capability of compensating inter-symbol interference (ISI) losses in a 5-m 28-AWG DVI cable. Typical cable measurements indicate that the TMDS341A can drive a 5-m 28-AWG HDMI cable and pass the eye mask at the output of a HDMI source (TP1) and a 10-m 28-AWG HDMI cable and pass the eye mask at the input of a HDMI sink (TP2). Figure 34 through Figure 37 show the eye mask measurement results. Figure 34. Eye Diagram at Output 5-m 28-AWG Cable vs TP1 Eye Mask Figure 35. Eye Diagram Recovered by TMDS341A vs TP1 Eye Mask Submit Documentation Feedback 19 TMDS341A www.ti.com SLLS702 – MAY 2006 APPLICATION INFORMATION (continued) Figure 36. Eye Diagram at Output 10-m 28-AWG Cable vs TP2 Eye Mask Figure 37. Eye Diagram Recovered by TMDS341A vs TP2 Eye Mask DDC Signal Path Observed I2C bus voltage is dependent on bus resistance, capacitance, and time. The transient bus voltage, when charging from a low state to a high state, can be calculated using equation (1). V(t) = VDD(1 – e–t/RC) (1) Where: t is the time since the charging started VDD is the pull-up termination voltage R is the total resistance on the I2C link C is the total capacitance on the I2C link In the I2C bus specification, version 2.1, the high-level threshold voltage is VIH = 0.7 VDD, and the low-level threshold voltage is VIL = 0.3 VDD. From equation (1), the times to charge from a bus voltage of 0 V to the VIH and VIL levels are: tIH = 1.204 × RC tIL = 0.357 × RC The bus rise time (from 0.3 VDD to 0.7 VDD) is then given by equation (2): tr(30-70) = tIH– tIL = 0.847 × RC (2) The TMDS341A can be easily applied in stand-alone switch boxes and digital displays. The following sections show the bus lengths that can be supported in each case. Maximum Bus Lengths for Switch Applications Figure 38 shows the TMDS341A being used as a stand-alone switch. Both pull-up resistors are decided by the source and sink equipment. A 1.5-kΩ resistor at the source and a 47-kΩ resistor at the sink are recommended. 20 Submit Documentation Feedback TMDS341A www.ti.com SLLS702 – MAY 2006 APPLICATION INFORMATION (continued) Sink Switch Box Source VDDsource VDDsink Rupsource Rupsink TMDS341A SDAn Csource SDA_Sink Ccable1 CI CO Ccable2 Csink Figure 38. DDC Link from Source to Sink With External Switch Box Rupsource = 1.5-kΩ pull-up to 5 V Rupsink = 47-kΩ pull-up to 5 V Rtotal = Rupsource // Rupsink = 1.45 kΩ Ctotal = Csource // Ccable1 // Ci // Co // Ccable2 // Csink For standard mode I2C, the frequency is at 100 kHz, and the transition time must be less than 1 µs. The total allowable capacitance, Ctotal, is then 814-pF. Csource and Csink are limited by the HDMI specification to 50 pF. Ci/o for the TMDS341A is 10 pF max. The total capacitance from DVI or HDMI cables, Ccable1 and Ccable2, should then be less than 704 pF. Typical capacitance is 200 pF for a 28-AWG 5-m HDMI cable and 300 pF for a 28-AWG 5-m DVI cable. The recommended total cable length is the length of cable 1, Lcable1, plus the length of cable 2, Lcable2. For a 28-AWG DVI cable, the total cable length is 11 m; and for a 28-AWG HDMI cable, the total cable length is 17 m. This calculation is applicable to VIH ≤ Vpass. Maximum Bus Lengths for DTV Applications Figure 39 shows the TMDS341A being used as a switch in a DTV and being placed on the same PCB board as the DVI/HDMI receiver. Unlike Figure 38, the output connector of the TMDS341A stand-alone switch and the input connector of the sink are removed, which results in a lower capacitance in the DDC link and eliminates the impedance discontinuity. However, the capacitance of the removed connectors is relatively small, relative to the total allowable capacitance. The results from the previous section Maximum Bus Lengths for Switch Applications can be reused if the pull-up resistors and capacitances have the same values. The recommended total cable length is the length from source to sink. Source Sink VDDsource VDDsink Rupsource Rupsink TMDS341A SDAn Csource Ccable DVI/HDMI RX SDA_Sink Csink Figure 39. DDC Link From Source to Sink Without External Switch Box Submit Documentation Feedback 21 TMDS341A www.ti.com SLLS702 – MAY 2006 APPLICATION INFORMATION (continued) Table 2 summarizes the recommended cable lengths based on threshold voltages VIH = 0.7 VDD and VIL = 0.3 VDD. Table 2. Recommended Cable Lengths Under General Threshold Voltages, 0.7 VDD and 0.3 VDD, of a DDC Interface DDC THRESHOLD VOLTAGE, VIH = 0.7 VDD, VIL = 0.3 VDD SUGGESTED PULL-UP RESISTANCE (kΩ) Rupsource = 1.5 kΩ Rupsink = 47 kΩ CABLE TYPE TOTAL CABLE LENGTH (m) SWITCH BOX Lcable1 + Lcable2 DIGITAL DISPLAY Lcable 28-AWG DVI 11 11 28-AWG HDMI 17 17 Applying the same methodology to the case of VIH = 1.9 V and VIL = 0.7 V, Table 3 summarizes the recommended cable lengths to meet the timing requirement of the DDC interface. Table 3. Recommended Cable Lengths Under General Threshold Voltages, 1.9 V and 0.7 V, of a DDC Interface DDC THRESHOLD VOLTAGE, VIH = 1.9 V, VIL = 0.7 V SUGGESTED PULL-UP RESISTANCE (kΩ) Rupsource = 1.5 kΩ Rupsink = 47 kΩ 22 CABLE TYPE TOTAL CABLE LENGTH (m) SWITCH BOX Lcable1 + Lcable2 DIGITAL DISPLAY Lcable 28-AWG DVI 16 16 28-AWG HDMI 24 24 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TMDS341APFC ACTIVE TQFP PFC 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMDS341APFCG4 ACTIVE TQFP PFC 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMDS341APFCR ACTIVE TQFP PFC 80 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMDS341APFCRG4 ACTIVE TQFP PFC 80 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996 PFC (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 60 0,08 M 41 61 40 80 21 1 0,13 NOM 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 0,25 14,20 SQ 13,80 0,05 MIN 0°– 7° 0,75 0,45 1,05 0,95 Seating Plane 0,08 1,20 MAX 4073177 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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