PI74FCT3573 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Fast CMOS 3.3V 8-Bit Transparent Latch Features Description • • • • Pericom Semiconductor’s PI74FCT3 series of logic circuits are produced in the Company’s advanced 0.6 micron CMOS technology, achieving industry leading speed grades. • • • • • • Advanced Low Power CMOS Operation Compatible with LVC class of products Compatible with industry standard octal pinouts Excellent output drive capability: Balanced drives (24 mA sink and source) Can serve as a 5V to 3V translator Inputs can be driven by 3.3V or 5V devices Low ground bounce outputs Hysteresis on all inputs Industrial operating temperature range: –40°C to +85°C Packages available: – 20-pin 173 mil wide plastic TSSOP (L20) – 20-pin 150 mil wide plastic QSOP (Q20) – 20-pin 150 mil wide plastic TQSOP (R20) – 20-pin 300 mil wide plastic SOIC (S20) The PI74FCT3573 is an 8-bit transparent latch designed with 3-state outputs and is intended for bus oriented applications. When Latch Enable (LE) is HIGH, the flip-flops appear transparent to the data. The data that meets the set-up time when LE is LOW is latched. When OE is HIGH, the bus output is in the high impedance state. The PI74FCT3573 can be driven from either 3.3V or 5.0V devices allowing this device to be used as a translator in a mixed 3.3/5.0V system. Pinout Logic Block Diagram OE OE D0 D1 D2 D3 D4 D5 D6 D7 GND LE D0 D O0 O G 20 1 19 2 18 3 20-Pin 17 4 L20 16 5 R20 15 6 Q20 7 S20 14 13 8 12 9 11 10 Vcc O0 O1 O2 O3 O4 O5 O6 O7 LE TO 7 OTHER CHANNELS Truth Table Pin Description (1) DN H L X Note: 1. H = X = L = Z = Inputs LE H H X OE L L H Outputs ON H L Z (1) Pin Name OE LE D7-D0 O7-O0 GND VCC High Voltage Level Don’t Care Low Voltage Level High Impedance 1 Description Output Enable Input (Active LOW) Latch Enable Input (Active HIGH) Data Inputs 3-State Outputs Ground Power PS8121A 07/21/97 PI74FCT3573 3.3V 8-BIT TRANSPARENT LATCH 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................–65°C to +150°C Ambient Temperature with Power Applied ............................ –40°C to +85°C Supply Voltage to Ground Potential (Inputs & Vcc Only) ..... –0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) .. –0.5V to +7.0V DC Input Voltage .................................................................... –0.5V to +7.0V DC Output Current .............................................................................. 120 mA Power Dissipation .................................................................................... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 2.7V to 3.6V) Parameters IOZH IOZL VIK IODH IODL VOH Input HIGH Voltage (Input pins) Input HIGH Voltage (I/O pins) Input LOW Voltage (Input and I/O pins) Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage VOL Output LOW Voltage IOS IOFF VH Short Circuit Current(4) Power Down Disable Input Hysteresis VIH VIL IIH IIL Test Conditions(1) Description Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VIN = 5.5V VCC = Max. VIN = VCC VCC = Max. VIN = GND VCC = Max. VIN = GND VCC = Max. VOUT = 5.5V VCC = Max. VOUT = GND VCC = Min., IIN = –18mA VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) VCC = Min. IOH = –0.1mA VIN = VIH or VIL IOH = –3mA VCC = 3.0V, IOH = –8mA VIN = VIH or VIL IOH = –24mA VCC = Min. IOL = 0.1mA VIN = VIH or VIL IOL = 16mA IOL = 24mA VCC = Max.(3), VOUT = GND –60 VCC = 0V, VIN or VOUT ≤ 4.5V Min. Typ(2) Max. Units 2.2 2.0 –0.5 — — — 5.5 5.5 0.8 V V V ±1 ±1 ±1 ±1 ±1 ±1 –1.2 –110 200 — — — — 0.2 0.4 0.5 mA ±100 — µA µA µA µA µA µA V mA mA V V V — — — — — — — — — — — — — –0.7 –36 –60 50 90 Vcc-0.2 — 2.4 3.0 2.4(5) 3.0 2.0 — — — — 0.2 — 0.3 –85 –240 — — — 150 V V V µA mV Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC – 0.6V at rated current. Capacitance (TA = 25°C, f = 1 MHz) Parameters(1) CIN COUT Description Test Conditions Typ Max. Units Input Capacitance Output Capacitance VIN = 0V VOUT = 0V 4.5 5.5 6 8 pF pF Note: 1. This parameter is determined by device characterization but is not production tested. 2 PS8121A 07/21/97 PI74FCT3573 3.3V 8-BIT TRANSPARENT LATCH 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Power Supply Characteristics Parameters Description Test Conditions(1) Min. Typ(2) Max. Units ICC Quiescent Power Supply Current VCC = Max. VIN = GND or VCC 0.1 10 µA ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = VCC – 0.6V(3) 2.0 30 µA ICCD Dynamic Power Supply(4) VCC = Max., Outputs Open OE = GND One Bit Toggling 50% Duty Cycle VIN = VCC VIN = GND 95 100 µA/ MHz VCC = Max., Outputs Open fI = 10 MHZ 50% Duty Cycle OE = GND One Bit Toggling VIN = VCC – 0.6V VIN = GND VCC = Max., Outputs Open fI = 2.5 MHZ 50% Duty Cycle OE = GND 8 Bits Toggling VIN = VCC – 0.6V VIN = GND IC Total Power Supply Current(6) 0.97 2.3 mA 1 2 3 4 5 1.9 4.7(5) 6 7 Notes: 1. ForMax. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 3.3V, +25°C ambient. 3. Per TTL driven input; all other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz. 8 9 10 11 12 13 14 15 3 PS8121A 07/21/97 PI74FCT3573 3.3V 8-BIT TRANSPARENT LATCH 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics over Operating Range(1) FCT3573 Com. Parameters Description Conditions tPLH tPHL Propagation Delay Dx to Ox CL = 50pF RL = 500Ω tPLH tPHL (2) (3) Min Max Units 1.5 4.2 ns Propagation Delay LE to Ox 2.0 5.5 ns tPZH tPZL Output Enable Time OE to Ox 1.5 5.5 ns tPHZ tPLZ Output Disable Time(4) OE to Ox 1.5 5.0 ns tSU Setup Time HIGH or LOW, Dx to LE 2.0 ns tH Hold Time HIGH or LOW, Dx to LE 1.5 ns tW LE Pulse Width(4) HIGH 5.0 ns tSK(o) Output Skew(5) 0.5 ns Notes: 1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±0.3V, normal range. For Vcc = 2.7V, extended range, all Propagation Delays and Enable/Disable times should be degraded by 20%. 2. See test circuit and wave forms. 3. Minimum limits are guaranteed but not tested on Propagation Delays. 4. This parameter is guaranteed but not production tested. 5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 4 PS8121A 07/21/97