TI SN74AC534DB

SN54AC534, SN74AC534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS554A – NOVEMBER 1995 – REVISED MAY 1996
D
D
D
SN54AC534 . . . J OR W PACKAGE
SN74AC534 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
3-State Inverting Outputs Drive Bus Lines
Directly
Full Parallel Access for Loading
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
description
These octal edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
1D
1Q
OE
VCC
SN54AC534 . . . FK PACKAGE
(TOP VIEW)
2D
2Q
3Q
3D
4D
On the positive transition of the clock (CLK) input,
the Q outputs are set to the complements of the
logic levels set up at the data (D) inputs.
8Q
D
4
3 2 1 20 19
18
5
17
6
16
7
15
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
14
8
A buffered output-enable (OE) input can be used
9 10 11 12 13
to place the eight outputs in either a normal logic
state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without need for interface or pullup components.
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54AC534 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AC534 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
CLK
D
L
↑
H
L
L
↑
L
H
L
H or L
X
Q0
H
X
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54AC534, SN74AC534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS554A – NOVEMBER 1995 – REVISED MAY 1996
logic symbol†
1
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
11
3
4
logic diagram (positive logic)
OE
EN
LE
C1
1D
1
2
5
7
6
8
9
13
12
14
15
17
16
18
19
1
11
C1
1Q
2Q
1D
3
2
1Q
1D
3Q
4Q
5Q
To Seven Other Channels
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . 0.6 W
DW package . . . . . . . . . . . . . . . . . . 1.6 W
N package . . . . . . . . . . . . . . . . . . . . 1.3 W
PW package . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54AC534, SN74AC534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS554A – NOVEMBER 1995 – REVISED MAY 1996
recommended operating conditions (see Note 3)
SN54AC534
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
Low-level input voltage
VI
VO
∆t/∆v
2
6
MAX
2
6
3.15
3.15
0
Low-level output current
MIN
2.1
0
High-level output current
SN74AC534
2.1
VCC = 4.5 V
VCC = 5.5 V
Output voltage
IOL
MAX
3.85
Input voltage
IOH
MIN
3.85
0.9
0.9
1.35
1.35
1.65
1.65
VCC
VCC
0
0
VCC
VCC
–12
–12
–24
–24
VCC = 5.5 V
VCC = 3 V
–24
–24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
24
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
V
V
VCC = 3 V
VCC = 4.5 V
Input transition rise or fall rate
UNIT
V
V
V
mA
mA
0
8
0
8
ns/V
–55
125
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 µA
VOH
IOH = –12 mA
IOH = –24
24 mA
IOL = 50 µA
VOL
IOL = 12 mA
IOL = 24 mA
IOZ
II
VO = VCC or GND
VI = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
IO = 0
VCC
MIN
TA = 25°C
TYP
MAX
SN54AC534
MIN
MAX
SN74AC534
MIN
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.56
2.4
2.46
4.5 V
3.86
3.7
3.76
5.5 V
4.86
4.7
MAX
UNIT
V
4.76
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
5.5 V
±0.5
±5
±2.5
µA
5.5 V
±0.1
±1
±1
µA
5.5 V
4
80
40
µA
5V
4.5
V
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54AC534, SN74AC534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS554A – NOVEMBER 1995 – REVISED MAY 1996
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
SN54AC534
MIN
SN74AC534
MAX
MIN
MAX
UNIT
tw
tsu
Pulse duration, CLK high or low
5
8
6.5
ns
Setup time, data before CLK↑
5
8
6.5
ns
th
Hold time, data after CLK↑
1
3
1.5
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
SN54AC534
MIN
SN74AC534
MAX
MIN
MAX
UNIT
tw
tsu
Pulse duration, CLK high or low
3.5
5.5
4
ns
Setup time, data before CLK↑
3.5
5.5
4
ns
th
Hold time, data after CLK↑
1
3
1.5
ns
switching characteristics over recommended operating
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
MAX
70
CLK
Q
OE
Q
OE
Q
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
Q
OE
Q
OE
Q
SN54AC534
MIN
SN74AC534
MAX
MIN
MAX
70
14
2
17.5
2.5
16
3
13
2
16.5
2.5
15
3
12.5
2
15.5
2.5
14
3
12.5
2
15.5
2.5
14
2
13.5
1
16.5
1.5
15
2
12
1
15
1.5
13.5
free-air
TA = 25°C
MIN
MAX
temperature
SN54AC534
MIN
SN74AC534
MAX
75
MIN
range,
UNIT
MHz
3
150
CLK
temperature
60
switching characteristics over recommended operating
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
free-air
MAX
140
ns
ns
ns
range,
UNIT
MHz
2.5
10.5
1.5
13.5
2
12
2.5
9.5
1.5
12.5
2
11
2.5
10
1.5
13
2
11.5
2.5
10
1.5
13
2
11.5
1.5
11.5
1
14
1
12.5
1.5
10
1
12.5
1
11
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TEST CONDITIONS
TYP
UNIT
CL = 50 pF, f = 1 MHz
40
pF
SN54AC534, SN74AC534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS554A – NOVEMBER 1995 – REVISED MAY 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
500 Ω
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
LOAD CIRCUIT
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
th
50% VCC
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
VCC
50% VCC
Input
50% VCC
0V
tPHL
tPLH
50% VCC
In-Phase
Output
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
Output
Waveform 2
S1 at Open
(see Note B)
50% VCC
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
VCC
50% VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
tPZH
50% VCC
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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• DALLAS, TEXAS 75265
5
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Copyright  1998, Texas Instruments Incorporated