1CY2308 CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps — Device-device skew less than 700 ps — Two banks of four outputs, three-stateable by two select inputs • 10-MHz to 133-MHz operating range • Low jitter, less than 200 ps cycle-cycle (–1, –1H, –4, –5H) • Space-saving 16-pin 150-mil SOIC package or 16-pin TSSOP • 3.3V operation • Industrial Temperature available Functional Description The CY2308 is a 3.3V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 200 ps. The CY2308 has two banks of four outputs each, which can be controlled by the Select inputs as shown in the table “Select Input Decoding.” If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The CY2308 PLL enters a power-down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 50 µA of current draw. The PLL shuts down in two additional cases as shown in the “Select Input Decoding” table. Multiple CY2308 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. The CY2308 is available in five different configurations, as shown in the “Available CY2308 Configurations” table on page 2. The CY2308–1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The CY2308–1H is the high-drive version of the –1, and rise and fall times on this device are much faster. The CY2308–2 allows the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The CY2308–3 allows the user to obtain 4X and 2X frequencies on the outputs. The CY2308–4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile, and can be used in a variety of applications. The CY2308–5H is a high-drive version with REF/2 on both banks. Pin Configuration Block Diagram /2 REF PLL FBK MUX /2 CLKA2 Extra Divider (–3, –4) CLKA3 Extra Divider (–5H) S2 S1 SOIC Top View CLKA1 CLKA4 Select Input Decoding /2 CLKB1 REF CLKA1 1 16 2 15 CLKA2 VDD 3 14 4 13 GND CLKB1 CLKB2 S2 5 12 6 11 7 10 8 9 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 CLKB2 CLKB3 Extra Divider (–2, –3) Cypress Semiconductor Corporation Document #: 38-07146 Rev. *C CLKB4 • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised June 16, 2004 CY2308 Pin Description Pin Signal Description [1] Input reference frequency, 5V tolerant input 1 REF 2 CLKA1[2] Clock output, Bank A 3 [2] CLKA2 Clock output, Bank A 4 VDD 3.3V supply 5 GND Ground 6 CLKB1[2] Clock output, Bank B 7 [2] CLKB2 Clock output, Bank B 8 S2[3] Select input, bit 2 9 [3] S1 Select input, bit 1 10 [2] CLKB3 Clock output, Bank B 11 CLKB4[2] Clock output, Bank B 12 GND Ground 13 VDD 3.3V supply 14 CLKA3[2] Clock output, Bank A 15 CLKA4[2] Clock output, Bank A 16 FBK PLL feedback input Select Input Decoding S2 S1 CLOCK A1–A4 CLOCK B1–B4 Output Source PLL Shutdown 0 0 Three-State Three-State PLL Y 0 1 Driven Three-State PLL N Driven[4] Reference Y Driven PLL N 1 0 1 1 [4] Driven Driven Available CY2308 Configurations Device Feedback From Bank A Frequency Bank B Frequency CY2308–1 Bank A or Bank B Reference Reference CY2308–1H Bank A or Bank B Reference Reference CY2308–2 Bank A Reference Reference/2 CY2308–2 Bank B 2 X Reference Reference CY2308–3 Bank A 2 X Reference Reference or Reference[5] CY2308–3 Bank B 4 X Reference 2 X Reference CY2308–4 Bank A or Bank B 2 X Reference 2 X Reference CY2308–5H Bank A or Bank B Reference /2 Reference /2 Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. Outputs inverted on 2308–2 and 2308–3 in bypass mode, S2 = 1 and S1 = 0. 5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2. Document #: 38-07146 Rev. *C Page 2 of 14 CY2308 Zero Delay and Skew Control REF. Input to CLKA/CLKB Delay v/s Difference in Loading between FBK pin and CLKA/CLKB Pins To close the feedback loop of the CY2308, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the inputoutput delay. This is shown in the graph above. Maximum Ratings For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. Storage Temperature.................................. –65°C to +150°C Supply Voltage to Ground Potential ...............–0.5V to +7.0V DC Input Voltage (Except Ref) .............. –0.5V to VDD + 0.5V DC Input Voltage REF ........................................... –0.5 to 7V Junction Temperature...................................................150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V For zero output-output skew, be sure to load outputs equally. For further information on using CY2308, refer to the application note “CY2308: Zero Delay Buffer.” Operating Conditions for CY2308SC-XX Commercial Temperature Devices Parameter Description Min. Max. Unit 3.0 3.6 V 0 70 °C VDD Supply Voltage TA Operating Temperature (Ambient Temperature) CL Load Capacitance, below 100 MHz 30 pF Load Capacitance, from 100 MHz to 133 MHz 15 pF Capacitance[6] CIN Input tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 7 pF 50 ms Note: 6. Applies to both Ref Clock and FBK. Document #: 38-07146 Rev. *C Page 3 of 14 CY2308 Electrical Characteristics for CY2308SC-XX Commercial Temperature Devices Parameter Description VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current IIH Input HIGH Current Test Conditions Min. Max. Unit 0.8 V VIN = 0V 50.0 µA VIN = VDD 100.0 µA 0.4 V 2.0 [7] VOL Output LOW Voltage VOH Output HIGH Voltage[7] IOL = 8 mA (–1, –2, –3, –4) IOL = 12 mA (–1H, –5H) IOH = –8 mA (–1, –2, –3, –4) IOH = –12 mA (–1H, –5H) V 2.4 V IDD (PD mode) Power Down Supply Current REF = 0 MHz 12.0 µA IDD Supply Current 45.0 mA 70.0 (–1H,–5H) mA Unloaded outputs, 66-MHz REF (–1, –2, –3, –4) 32.0 mA Unloaded outputs, 33-MHz REF (–1, –2, –3, –4) 18.0 mA Unloaded outputs, 100-MHz REF, Select inputs at VDD or GND Note: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07146 Rev. *C Page 4 of 14 CY2308 Switching Characteristics for CY2308SC-XX Commercial Temperature Devices [8] Max. Unit t1 Parameter Output Frequency Name 30-pF load, All devices Test Conditions Min. 10 Typ. 100 MHz t1 Output Frequency 20-pF load, –1H, –5H devices[9] 10 133.3 MHz t1 Output Frequency 15-pF load, –1, –2, –3, –4 devices 133.3 MHz Duty Cycle[7] = t2 ÷ t1 (–1, –2, –3, –4, –1H, –5H) Measured at 1.4V, FOUT = 66.66 MHz 30-pF load 40.0 50.0 60.0 % Duty Cycle[7] = t2 ÷ t1 (–1, –2, –3, –4, –1H, –5H) Measured at 1.4V, FOUT <50.0 MHz 15-pF load 45.0 50.0 55.0 % t3 Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF load 2.20 ns t3 Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF load 1.50 ns t3 Rise Time[7] (–1H, –5H) Measured between 0.8V and 2.0V, 30-pF load 1.50 ns t4 Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF load 2.20 ns t4 Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF load 1.50 ns t4 Fall Time[7] (–1H, –5H) Measured between 0.8V and 2.0V, 30-pF load 1.25 ns t5 Output to Output Skew on same Bank (–1, –2, –3, –4)[7] All outputs equally loaded 200 ps Output to Output Skew (–1H, –5H) All outputs equally loaded 200 ps Output Bank A to Output All outputs equally loaded Bank B Skew (–1, –4, –5H) 200 ps Output Bank A to Output Bank B Skew (–2, –3) 400 ps 10 All outputs equally loaded t6 Delay, REF Rising Edge to Measured at VDD/2 FBK Rising Edge[7] 0 ±250 ps t7 Device to Device Skew[7] Measured at VDD/2 on the FBK pins of devices 0 700 ps t8 Output Slew Rate[7] Measured between 0.8V and 2.0V on –1H, –5H device using Test Circuit #2 tJ Cycle to Cycle Jitter[7] (–1, –1H, –4, –5H) Measured at 66.67 MHz, loaded outputs, 15-pF load 200 ps Measured at 66.67 MHz, loaded outputs, 30-pF load 200 ps Measured at 133.3 MHz, loaded outputs, 15-pF load 100 ps Measured at 66.67 MHz, loaded outputs 30-pF load 400 ps Measured at 66.67 MHz, loaded outputs 15-pF load 400 ps Stable power supply, valid clocks presented on REF and FBK pins 1.0 ms tJ tLOCK Cycle to Cycle Jitter[7] (–2, –3) PLL Lock Time[7] 1 V/ns Notes: 8. All parameters are specified with loaded outputs. 9. CY2308–5H has maximum input frequency of 133.33 MHz and maximum output of 66.67 MHz. Document #: 38-07146 Rev. *C Page 5 of 14 CY2308 Operating Conditions for CY2308SI-XX Industrial Temperature Devices Min. Max. Unit VDD Parameter Supply Voltage Description 3.0 3.6 V TA Operating Temperature (Ambient Temperature) –40 85 °C CL Load Capacitance, below 100 MHz 30 pF Load Capacitance, from 100 MHz to 133 MHz 15 pF CIN Input Capacitance[6] 7 pF tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 50 ms Max. Unit 0.8 V 0.05 Electrical Characteristics for CY2308SI-XX Industrial Temperature Devices Parameter Description VIL Input LOW Voltage VIH Input HIGH Voltage Test Conditions Min. 2.0 V IIL Input LOW Current VIN = 0V 50.0 µA IIH Input HIGH Current VIN = VDD 100.0 µA VOL Output LOW Voltage[7] IOL = 8 mA (–1, –2, –3, –4) IOL = 12 mA (–1H, –5H) 0.4 V VOH Output HIGH Voltage[7] IOH = –8 mA (–1, –2, –3, –4) IOH = –12 mA (–1H, –5H) IDD (PD mode) Power Down Supply Current REF = 0 MHz 25.0 µA IDD Supply Current Unloaded outputs, 100 MHz, Select inputs at VDD or GND 45.0 mA Document #: 38-07146 Rev. *C 2.4 V 70(–1H,–5H) mA Unloaded outputs, 66-MHz REF (–1, –2, –3, –4) 35.0 mA Unloaded outputs, 66-MHz REF (–1, –2, –3, –4) 20.0 mA Page 6 of 14 CY2308 Switching Characteristics for CY2308SI-XX Industrial Temperature Devices [8] Max. Unit t1 Parameter Output Frequency 30-pF load, All devices 10 100 MHz t1 Output Frequency 20-pF load, –1H, –5H devices[9] 10 133.3 MHz t1 Output Frequency 15-pF load, –1, –2, –3, –4 devices 133.3 MHz Duty Cycle[7] = t2 ÷ t1 (–1, –2, –3, –4, –1H, –5H) Measured at 1.4V, FOUT = 66.66 MHz 30-pF load 40.0 50.0 60.0 % Duty Cycle[7] = t2 ÷ t1 (–1, –2, –3, –4, –1H, –5H) Measured at 1.4V, FOUT <50.0 MHz 15-pF load 45.0 50.0 55.0 % t3 Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF load 2.50 ns t3 Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF load 1.50 ns t3 Rise Time[7] (–1H, –5H) Measured between 0.8V and 2.0V, 30-pF load 1.50 ns t4 Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF load 2.50 ns t4 Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF load 1.50 ns t4 Fall Time[7] (–1H, –5H) Measured between 0.8V and 2.0V, 30-pF load 1.25 ns t5 Output to Output Skew on All outputs equally loaded same Bank (–1, –2, –3, –4)[7] 200 ps Output to Output Skew (–1H, –5H) All outputs equally loaded 200 ps Output Bank A to Output Bank B Skew (–1, –4, –5H) All outputs equally loaded 200 ps Output Bank A to Output Bank B Skew (–2, –3) All outputs equally loaded 400 ps t6 Delay, REF Rising Edge to FBK Rising Edge[7] Measured at VDD/2 0 ±250 ps t7 Device to Device Skew[7] Measured at VDD/2 on the FBK pins of devices 0 700 ps t8 Output Slew Rate[7] Measured between 0.8V and 2.0V on –1H, –5H device using Test Circuit # 2 tJ Cycle to Cycle Jitter[7] (–1, –1H, –4, –5H) Measured at 66.67 MHz, loaded outputs, 15-pF load 200 ps Measured at 66.67 MHz, loaded outputs, 30-pF load 200 ps Measured at 133.3 MHz, loaded outputs, 15 pF load 100 ps Measured at 66.67 MHz, loaded outputs 30-pF load 400 ps Measured at 66.67 MHz, loaded outputs 15-pF load 400 ps Stable power supply, valid clocks presented on REF and FBK pins 1.0 ms tJ tLOCK Name Cycle to Cycle Jitter[7] (–2, –3) PLL Lock Time[7] Document #: 38-07146 Rev. *C Test Conditions Min. Typ. 10 1 V/ns Page 7 of 14 CY2308 Switching Waveforms Duty Cycle Timing t1 t2 1.4V 1.4V 1.4V All Outputs Rise/Fall Time OUTPUT 2.0V 0.8V 2.0V 0.8V 3.3V 0V t4 t3 Output-Output Skew OUTPUT 1.4V 1.4V OUTPUT t5 Input-Output Propagation Delay INPUT VDD/2 VDD/2 FBK t6 Device-Device Skew VDD/2 FBK, Device 1 VDD/2 FBK, Device 2 t7 Document #: 38-07146 Rev. *C Page 8 of 14 CY2308 Typical Duty Cycle[10] and IDD Trends[11] for CY2308–1,2,3,4 Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C) 60 60 58 58 56 56 54 52 33 MHz 50 66 MHz 48 100 MHz 46 Duty Cycle (% ) Duty Cycle (% ) Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C) 54 66 MHz 50 100 MHz 48 133 MHz 46 44 44 42 42 40 33 MHz 52 40 3 3.1 3.2 3.3 3.4 3.5 3.6 3 3.1 3.2 VDD (V) Duty Cycle Vs Frequency (for 30 pF Loads over Temperature - 3.3V) 3.4 3.5 3.6 Duty Cycle Vs Frequency (for 15 pF Loads over Temperature - 3.3V) 60 60 58 58 56 56 54 -40C 52 0C 50 25C 48 70C 46 85C Duty Cycle (%) Duty Cycle (%) 3.3 VDD (V) 54 -40C 52 0C 50 25C 48 70C 46 85C 44 44 42 42 40 40 20 40 60 80 100 120 140 20 40 60 Frequency (MHz) 80 100 120 140 Frequency (MHz) IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C) IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C) 140 140 120 120 100 100 80 33 M Hz 80 33 M Hz 66 M Hz 60 66 M Hz 40 40 1 00 M Hz 20 20 60 1 00 M Hz 0 0 0 2 4 6 8 0 # o f Lo ad ed Out p ut s 2 4 6 8 # o f Lo a de d Ou t p ut s Notes: 10. Duty Cycle is taken from typical chip measured at 1.4V. 11. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Voltage Supply (V); f = frequency (Hz)) Document #: 38-07146 Rev. *C Page 9 of 14 CY2308 Typical Duty Cycle[10] and IDD Trends[11] for CY2308–1H, 5H Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C) 60 60 58 58 56 56 54 52 33 MHz 50 66 MHz 48 100 MHz 46 Duty Cycle (% ) Duty Cycle (% ) Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C) 54 66 MHz 50 100 MHz 48 133 MHz 46 44 44 42 42 40 33 MHz 52 40 3 3.1 3.2 3.3 3.4 3.5 3.6 3 3.1 3.2 VDD (V) 3.4 3.5 3.6 Duty Cycle Vs Frequency Duty Cycle Vs VDD (for 15 15pF pFLoads Loadsover overFrequency Temperature - 3.3V) (for - 3.3V, 25C) Duty Cycle Vs Frequency (for 30 pF Loads over Temperature - 3.3V) 60 60 60 58 58 58 56 56 54 -40C 52 0C 50 25C 48 70C 46 85C Duty Cycle (% Duty Cycle (%)) 56 Duty Cycle (%) 3.3 VDD (V) 54 54 -40C 33 M Hz 0C 52 52 66 MHz 25C 100 MHz 70C 133 MHz 85C 50 50 48 48 46 46 44 44 44 42 42 42 40 40 40 20 40 60 80 100 120 320 140 40 3.1 60 3.2 80 3.3 100 3.4 120 3.5 140 3.6 Frequency VDD (V) (MHz) Frequency (MHz) IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C) IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C) 140 140 120 120 100 100 80 60 33 MHz 80 66 MHz 60 100 MHz 40 33 MHz 66 MHz 100 MHz 40 20 20 0 0 0 2 4 # o f Lo a de d Ou t put s Document #: 38-07146 Rev. *C 6 8 0 2 4 6 8 # o f Loa de d Out p ut s Page 10 of 14 CY2308 Test Circuits Test Circuit # 1 Test Circuit # 2 VDD V DD 0.1 µF OUTPUTS CLK OUT 0.1 µF GND Test Circuit for all parameters except t8 Document #: 38-07146 Rev. *C CLK out 10 pF V DD V DD GND OUTPUTS 1 KΩ C LOAD 0.1 µF 1 KΩ 0.1 µF GND GND Test Circuit for t8, Output slew rate on –1H, –5 device Page 11 of 14 CY2308 Ordering Information Ordering Code Package Name Package Type Operating Range CY2308SC–1 S16 16-pin 150-mil SOIC Commercial CY2308SI–1 S16 16-pin 150-mil SOIC Industrial CY2308SC–1H S16 16-pin 150-mil SOIC Commercial CY2308SI–1H S16 16-pin 150-mil SOIC Industrial CY2308ZC–1H Z16 16-pin 150-mil TSSOP Commercial CY2308ZI–1H Z16 16-pin 150-mil TSSOP Industrial CY2308SC–2 S16 16-pin 150-mil SOIC Commercial CY2308SI–2 S16 16-pin 150-mil SOIC Industrial CY2308SC–3 S16 16-pin 150-mil SOIC Commercial CY2308SI–3 S16 16-pin 150-mil SOIC Industrial CY2308SC–4 S16 16-pin 150-mil SOIC Commercial CY2308SI–4 S16 16-pin 150-mil SOIC Industrial CY2308SC–5H S16 16-pin 150-mil SOIC Commercial CY2308SI–5H S16 16-pin 150-mil SOIC Industrial CY2308ZC–5H Z16 16-pin 150-mil TSSOP Commercial CY2308ZI–5H Z16 16-pin 150-mil TSSOP Industrial CY2308SXC–1 S16 16-pin 150-mil SOIC Commercial CY2308SXI–1 S16 16-pin 150-mil SOIC Industrial CY2308SXC–1H S16 16-pin 150-mil SOIC Commercial CY2308SXI–1H S16 16-pin 150-mil SOIC Industrial CY2308ZXC–1H Z16 16-pin 150-mil TSSOP Commercial CY2308ZXI–1H Z16 16-pin 150-mil TSSOP Industrial CY2308SXC–2 S16 16-pin 150-mil SOIC Commercial CY2308SXI–2 S16 16-pin 150-mil SOIC Industrial CY2308SXC–3 S16 16-pin 150-mil SOIC Commercial CY2308SXI–3 S16 16-pin 150-mil SOIC Industrial CY2308SXC–4 S16 16-pin 150-mil SOIC Commercial CY2308SXI–4 S16 16-pin 150-mil SOIC Industrial CY2308SXC–5H S16 16-pin 150-mil SOIC Commercial CY2308SXI–5H S16 16-pin 150-mil SOIC Industrial CY2308ZXC–5H Z16 16-pin 150-mil TSSOP Commercial CY2308ZXI–5H Z16 16-pin 150-mil TSSOP Industrial Lead Free Document #: 38-07146 Rev. *C Page 12 of 14 CY2308 Package Drawings and Dimensions 16-Lead (150-Mil) SOIC S16.15 16 Lead (150 Mil) SOIC PIN 1 ID 8 1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012 PACKAGE WEIGHT 0.15gms 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] PART # S16.15 STANDARD PKG. 9 SZ16.15 LEAD FREE PKG. 16 0.386[9.804] 0.393[9.982] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0075[0.190] 0.0098[0.249] 0.016[0.406] 0.035[0.889] 0°~8° 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249] 51-85068-*B 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A All product and company names mentioned in this document may be the trademarks of their respective holders Document #: 38-07146 Rev. *C Page 13 of 14 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2308 .Document History Page Document Title: CY2308 3.3V Zero Delay Buffer Document Number: 38-07146 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110255 12/17/01 SZV Change from Spec number: 38-00528 to 38-07146 *A 118722 10/31/02 RGL Added Note 1 in page 2. *B 121832 12/14/02 RBI Power up requirements added to Operating Conditions Information *C 235854 See ECN RGL Added Lead Free Devices Document #: 38-07146 Rev. *C Page 14 of 14