Ordering number:ENN4033A Monolithic Linear IC LA4536M 5V CD Headphone-stereo Power Amplifier 10 0.625 [LA4536M] 6 5.15 6.4 • Less current drain. • Accept 16Ω load drive. • Excellent voltage reduction characteristic. • Excellent ripple rejection. • Power switch function and built-in muting circuit. • Low noise (7µV), low gain (11dB). unit:mm 3086A-MFP10S 4.4 Features Package Dimensions 5 1 1.8 max The LA4536M is a low noise, low distortion headphonestereo power IC designed for use on a portable CD. 0.15 0.1 1.5˚ 5.1 0.35 1.0 0.55 SANYO : MFP10S Specifications Absolute Maximum Ratings at Ta = 25˚C Parameter Symbol Maximum supply voltage VCC max Allowable power dissipation Conditions Ratings No signal Pd max Unit 6.0 V 300 mW Operating temperature Topr –20 to +75 ˚C Storage temperature Tstg –40 to +125 ˚C Operating Characteristics at Ta = 25˚C Parameter Symbol Conditions Ratings Unit Recommended supply voltage VCC 5.0 Operating supply voltage range VCC op 4.0 to 6.0 V V Recommended load impedance RL 16 to 32 Ω Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN O3098HA (KT)/62598RM (KI) No.4033–1/9 LA4536M Operating Characteristics at Ta = 25˚C, RL=16Ω, Rg=600Ω Parameter Symbol Quiescent current 1.0 20 mA 1.1 4.0 mA 1.0 µA 13 dB 1.0 dB 1.0 dB Output power PO Crosstalk CT SVRR Output noise voltage Unit VCC=6.0V, pin 10, GND VCC=6.0V, pin 1, GND ∆VG2 THD Rpple rejection max VCC=5.0V, no signal ∆VG1 Total harmonic distortion typ ICCO2 VG Voltage gain variations min ICCO1 ICCO3 Voltage gain Ratings Conditions VNO Power off effect VO(off) Mute effect VO(MT) Power on current sensitivity Power off voltage sensitivity I1(on) V1(off) Mute off current sensitivity Mute on voltage sensitivity VCC=5.0V, f=1kHz, VO=–10dBm VCC=5.0V, f=1kHz, VO=–10dBm 9 11 VCC=4.0V, f=1kHz, VO=–20dBm VCC=5.0V, f=1kHz, PO=1mW 0.02 VCC=5.0V, f=1kHz, THD=10% VCC=5.0V, f=1kHz, Rg=1kΩ, VO=–10dBm VCC=4.0V, f=100Hz, Rg=1kΩ, VO=–20dBm, BPF=100Hz VCC=6.0V, Rg=1kΩ, BPF=20Hz to 20Hz VCC=4.0V, f=100Hz, Pin 1 to GND, VIN=–10dBm VCC=4.0V, f=100Hz, Pin 1 to GND, VIN=–10dBm VCC=5.0V, V5≥0.85V 0.24 % 40 100 mW 40 60 dB 45 65 dB 7 0.05 0.5 I10(off) VCC=5.0V, V5≤0.1V VCC=5.0V, V5≥0.85V V10(on) VCC=5.0V, V5≤0.1V 0.5 20 µV –80 dBm –80 dBm 2.0 µA 2.0 µA 0.6 0.2 0.65 Note V V *1 : Quiescent current is the current flowing into pin 6. The current flowing into pin 1 and pin 10 is at the maximum value and calculated from the equation (V pin–0.5V)/16[V/kΩ], increasing total current. Equivalent Circuit Block Diagram P/SW 1 IN 1 2 PRE GND 3 IN 2 4 REF 5 POWER SWITCH MUTE CIRCUIT Amp1 Amp2 BIAS 10 MT/SW 9 OUT 1 8 POWER GND 7 OUT 2 6 VCC A11160 No.4033–2/9 LA4536M Test Circuit I1 I10 1 2 1 P/SW 3 P/SW MT/SW 10 Rg 1kΩ 2 IN 1 3 PRE GND OUT 1 9 LA4536M POWER GND 8 1 4 2 Rg 1kΩ 22µF 2 3 V10 4 2 SG MT/SW 4 V1 1 1 IN 2 OUT 2 7 220µF + 0.1µF 2.2Ω RL 16Ω 2.2Ω 0.1µF RL 16Ω + + + 5 REF VCC 6 MT/SW 10 OUT 1 9 4.7µF VR VCC 220µF DC A RIPPLE A11161 ICC Sample Application Circuit ON P/SW 1 P/SW 2 IN 1 3 PRE GND OFF MT/SW OFF ON VR VR SG 1 SG 2 4 22µF + IN 2 LA4536M POWER GND OUT 2 8 7 + RL 16Ω 2.2Ω 2.2Ω 0.1µF + + 5 REF VCC 6 220µF 0.1µF 4.7µF 220µF RL 16Ω – VCC + A11162 No.4033–3/9 LA4536M Pin Functions (VCC=5.0V) Pin No. Symbol Pin voltage Equivalent circuit Pin function • The system runs on when the VCC is applied to this pin and turns off by connectiong this pin to GND. 1 20kΩ P/SW1 1 A11164 • Input pin connection. Input impedance is 10kΩ. 2 IN1 2.1 500Ω 2 4 IN2 2.1 4 10kΩ A11165 3 PRE GND • 2.1V fixed bias is applied to this pin. 5 REF 2.1 5 23kΩ A11166 6 VCC • Output pin connection. 7 OUT2 2.1 9 OUT1 2.1 7 9 4.7kΩ A11167 8 POWER GND • The muting function turns on when this pin is connected to GND and turns off by applying the VCC to this pin. 10 MT/SW 20kΩ 10 A11168 No.4033–4/9 LA4536M VO – VIN 20 VCC=6.0V 5.0V 4.0V Total harmonic distortion, THD – % 10 Output, VO – dBm 0 THD=10% —10 —20 —30 —40 —50 —60 —70 —70 —60 —50 —40 —30 —20 THD – PO 10 f=1kHz RL=16Ω —10 0 10 7 5 VCC=5.0V RL=16Ω 3 2 1.0 7 5 3 2 0.1 7 5 3 2 0.1 20 2 3 5 100 7 5 3 2 PO 1.0 7 5 3 2 3 2 10 7 5 0.1 7 5 3 2 3 2 THD 1.0 7 5 0.01 7 5 3 20 1 3 2 4 5 6 7 12 5 7 100 2 3 VG 10 8 6 OUT + 220µF 2 10 2 3 2 3 5 7 100 5 7 1k 2 3 5 7 10k 16Ω 2 3 5 7100k Frequency, fIN – Hz ICC – PO 3 VCC=5.0V f=1kHz RL=16Ω 2 output on 2 Current drain, ICC – mA Voltage gain, VG – dB 3 4 3 2 8 f=1kHz RL=16Ω 20dBm V O=– –10dBm 2 14 VG – VCC 140 7 10 VCC=4.0V VO=–10dBm RL=16Ω Power supply voltage, VCC – V 160 5 VG – fIN 16 Voltage gain, VG – dB 3 2 10 7 5 Total harmonic distortion, THD – % Output power, PO – mW f=1kHz RL=16Ω THD=10% PO=1mW 3 Output power, PO – mW PO,THD – VCC 1000 7 5 2 7 1.0 Input voltage, VIN – dBm 120 100 80 100 0% 7 =1 HD 5 T 3 2 10 7 5 60 3 40 0 1 2 3 4 5 6 7 2 8 2 3 5 7 1.0 Power supply voltage, VCC – V Pd – PO 1000 VCC=4.0V RL=16Ω Rg=1kΩ VO=–10dBm 80 7 5 V 3 V 2 5 7 10 2 3 5 7 100 3 2 5 CT – fIN 100 f=1kHz RL=16Ω 2 output on Crosstalk, CT – dB Power dissipation, Pd – mW 2 3 2 Output power, PO – mW .0 =6 CC V 5.0 100 7 5 0µF =10 CREF 60 F 22µ 40 20 3 2 2 3 5 7 1.0 2 3 5 7 10 2 3 Output power, PO – mW 5 7 100 2 3 0 2 3 5 7 100 2 3 5 7 1k 2 3 5 7 10k 2 3 5 7 Frequency, fIN – Hz No.4033–5/9 LA4536M SVRR – VCC —30 —40 —50 —60 CREF=22µF —70 —80 —90 —100 0 1 2 3 4 5 6 7 VNO – VCC 100 7 VR=–20dBm fR=–100Hz Rg=1kΩ Output noise voltage, VNO – ∝V Ripple rejection, SVRR – dBm —20 5 Flat Rg=0 3 2 10 DIN Rg=0 7 5 3 2 0.1 7 5 3 2 8 0 1 Supply voltage, VCC – V Pin off voltage, VPIN(OFF) – V Output noise voltage, VNO – ∝ V 5 3 Flat 2 10 7 3 4 5 6 7 8 VPIN – VCC 1.2 RL=16Ω VCC=5.0V 7 2 Supply voltage, VCC – V VNO – Rg 100 Rg=1kΩ RL=16Ω DIN AUDIO 5 VIN=0 Rg=1kΩ Pin V5≤ 0.1V 1.0 0.8 Pin 10 (MT) MT is OFF ↑ ON↑ON↓ Pin 1 (P/SW)PWR is OFF↓ 0.6 0.4 0.2 3 22 3 5 7 100 2 3 5 7 1k 2 3 5 7 10k 2 3 5 0 7 0 1 Signal source impedance, Rg – Ω VIN=0 Rg=0 Pin V5≥ 0.5V 3 2 T) Pin 10 (M 0.1 7 5 3 2 Pin 1 (P/SW) 0.01 7 5 3 2 0 1 2 3 4 5 6 7 6 7 8 7 8 5 3 2 =0 gnal V IN No si 10 7 5 3 2 I CM on Mute on C 1.0 7 5 3 2 0 8 1 2 3 4 5 6 Supply voltage, VCC – V ICCOP OFF – VCC VDC – VCC 4.0 Rg=1kΩ VIN=0 VIN=0 Rg=1kΩ Mute switch on 1.0 7 5 3 2 3.0 Voltage, VDC – V Quiescent current, ICCOP OFF – mA 5 RL=16Ω(Dual Ope) tput 0% at ou Rg=1kΩ THD=1 100 f=1kHz 7 Supply voltage, VCC – V 7 5 3 2 4 ICC – VCC 3 2 Current drain, ICC – mA Pin on current, IPIN(ON) – µA 7 5 3 Supply voltage, VCC – V IPIN(ON) – VCC 1.0 2 PWR SW OFF 0.1 7 5 3 2 V5,V7,V9 2.0 V5 : VREF V7,V9 : POWER OUT 1.0 0.01 7 5 3 2 0 0 1 2 3 4 5 6 Supply voltage, VCC – V 7 8 0 1 2 3 4 5 6 7 8 Supply voltage, VCC – V No.4033–6/9 LA4536M PO – Ta 200 VG – Ta 16 VCC=5.0V VO=–10dBm RL=16Ω (Dual Ope) f=1kHz V Output power, PO – mW Voltage gain deviation, VG – dB =6.0 VCC 180 5.0V 160 140 120 4.0V 100 80 60 40 f=1kHz THD=10% RL=16Ω (Dual Ope) 20 —40 0 —20 20 40 60 80 14 12 10 8 6 4 —40 100 —20 Ambient temperature, Ta – ˚C VDC – Ta 2.4 Voltage, VDC – V 2.2 2.1 2.0 1.9 1.8 1.7 1.6 —40 —20 0 20 40 60 80 100 Ambient temperature, Ta – ˚C P.SW OFF 20 40 60 80 100 80 100 ICCO – Ta 16 Rg=1kΩ VIN=0 VCC=5.0V Quiescent current, ICCO – mA 2.3 0 Ambient temperature, Ta – ˚C 14 VIN=0 Rg=1kΩ VCC=5.0V 12 10 8 6 4 2 0 —40 —20 0 20 40 60 Ambient temperature, Ta – ˚C VCC=5.0V Output AC waveform, VIN=0 Output AC P.SW DC waveform P.SW OFF P.SW ON waveform P.SW DC waveform P.SW OFF VCC=5.0V Output AC waveform Output AC waveform, VIN=0 P.SW DC waveform P.SW DC waveform P.SW ON P.SW ON No.4033–7/9 LA4536M VCC=5.0V M.SW OFF Output AC waveform Output AC waveform, VIN=0 M.SW DC waveform M.SW DC waveform 1V/div M.SW OFF M.SW OFF VCC=5.0V M.SW ON Output AC waveform Output AC waveform, VIN=0 M.SW DC waveform M.SW DC waveform M.SW ON 1V/div M.SW ON Application Notes Popping noise reduction The switching sequence shown below can minimize the popping noise. PWR.SW VCC t3 PWR, Mute SW t1 t2 A11163 To minimize poping noise, the PWR mute switch should be turned on t1 (about 0.1s) after power-on and turned off t2 (about 0.1s) before power-off. Turn on and off the PWR mute switch by applying VCC with the PWR be in no state. No.4033–8/9 LA4536M Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 2003. Specifications and information herein are subject to change without notice. PS No.4033–9/9