Acapella Optical Modem IC ACS401 Main Features: * Enables up to four full-duplex serial transmission channels through a single fiber optic cable, providing eight virtual fiber paths. * Two additional low speed handshake signals. * Supports Ping Pong LED (PPLED) and LASER Duplex Devices (LDD) for single fiber applications or dual fiber applications using low cost LED/LASER emitters and PIN Diode receiver. * Link lengths up to 95 km with appropriate Laser. * Maximum data rate 128 kbps - optimised for talk-set applications. * Typical 7 mA (average) current consumption, including LASER drive current. * Digital mode, allowing the user to add an external amplifier. Also enables the ACS401 to be used in non-fiber applications. * Bit Error Rate (BER) of 10-9 Equivalent block diagram of ACS401. TRC TxD1 TxD2 TxD3 TxD4 Digital Filter FIFO Compress 3B4B Encoder PPLED LAP LED Driver TxCL RxD1 RxD2 RxD3 LAN Digital Filter FIFO Decompress PINN 3B4B Decoder RxD4 RxCL VA+ Single Fiber PINP PIN Receiver CNT GND Control Data Status XTAL Control Logic VD+ GND 4 XO1 XI1 XO2 XI2 HBT CLK9 ERRC ERRL 3 4 DR(1:3) DM(1:3) DP(1:4) PORB CKC General Description: The ACS401 is a complete optical-modem controller/ driver/receiver IC, supporting various user programmable, fullduplex, synchronous data rates to 128 kbps over a single fiber. Communicating modems automatically maintain synchronisation with each other such that the receive phase of one modem is lined up with the transmit phase of the other, compensating for the propagation delay presented by the link. Link lengths from zero to maximum distance, up to 95 km, are catered for automatically. Acapella Optical Modem IC ACS401 128 kbps Optical Modem for Long Haul Transmission for Single/Dual Fiber applications Inter-IC Encoding Technique VA+ The 3B4B encoding method is used for communication between ACS401s, thus ensuring that there is no DC component in the signal. The encoding and decoding is transparent to the user. 100 nF Laser 470 nF PMOS ZVP4424A VC Transmitter and Receiver Functions Single Fiber Signals TxD and RxD in this specification refer to the set of signals TxD(1:4) and RxD(1:4) respectively. 10 nF PIN Diode The TxD input data of the transmitting modem is time compressed and encoded in 3B4B format. In the receiving modem, 3B4B encoding ensures easy extraction of the bit-clock. The received data is filtered, decoded, then stored in an output memory. The memory provides time expansion, de-jittering and frequency compensation. The data is finally directed to the RxD output pin. VR2 50k PINN IN4001 LAN 4-pin Laser duplex single fiber mode with external Laser drive circuitry Operational Modes The ACS401 has four operational modes controlled by DP(1:4). There are modes of operation to support PPLED and LASER duplex devices on single fiber. In addition, LED/PIN and LASER/PIN are supported on dual fiber. Operational Mode 1. PPLED 2. 4-pin Duplex 3. LED & PIN 4. LASER & PIN No. of Fibers Single Single Dual Dual DP4 DP3 DP2 DP1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 AGND Mode 3 - LED/PIN dual fiber mode This is a dual fiber mode where the LED is used for transmission and a separate PIN diode is used for reception. This allows the use of low cost standard LEDs. LED LAP Fiber N.B. All LASERs must be 4-pin LASERS. DP(1:4) combinations not listed above are factory IC test modes, and should not be selected by the user. Damage to the PPLED/Duplex & LED/PIN components may result if these illegal modes are selected. LAN PIN diode PINP Fiber N.B. for all Operational modes 1, 2, 3, 4 SETB (Pin2) MUST be tied High. PINN LED/PIN dual fiber mode LED LAP Single Fiber LAN LED single fiber mode Mode 1 - LED single fiber mode This is the operational mode for single fiber LED transmission, i.e. the LED is a ‘ping-pong’ type (PPLED) used for both transmit and receive. Connect PINP of ACS401 to GND and leave PINN floating. Mode 2 4-pin Laser duplex single fiber mode This is a single fiber mode where the Laser duplex device is employed. This duplex device comprises a 4-pin Laser for transmission and a PIN diode for reception in a single housing. The Duplex devices are driven by the ACS401 in a half-duplex manner, so potential cross-talk between the transmitter and receiver is of no consequence. Mode 4 4-Pin LASER/PIN dual fiber mode This is a dual fiber mode where the 4-pin laser is used for transmission and a separate PIN diode is used for reception. It is necessary to use a small number of external components (shown in the diagram) to support the power regulation technique. The method for setting the Laser power is described in section headed Control of LASER current . VA+ is the +5V supply used to power the analogue of the ACS401. AGND is analogue ground (pin 49 of the ACS401).The loop is stable when the average current from the monitor pin equals the current through variable resistor VR2. The voltage VC is stable at this point and sets the laser drive current. VA+ 100 nF Fiber VC nF It is necessary to use a small number of external components (shown in the diagram) to support the power regulation technique. The method for setting the Laser power is described in section headed Control of LASER current . PIN Diode VR2 50k AGND IN4001 LAN VA+ is the +5V supply used to power the analogue of the ACS401. AGND is analogue ground (pin 49 of the ACS401).The loop is stable when the average current from the monitor pin equals the current through variable resistor VR2. The voltage VC is stable at this point and sets the laser drive current. Laser 470 nF PMOS ZVP4424A PINN 4-pin Laser dual fiber mode with external Laser drive circuitry Fiber Control of LASER current Example: To generate a 38.4 kbps dual channel. The LASER output current must be set for each individual device in accordance with the manufacturer’s recommendations. The maximum output current to the Laser is controlled by the resistor Rtrc connected between ground and TRC. The minimum value set on Rtrc to avoid damage to the ACS401 is 800Ω. Select a 64 kbps dual channel using the data rate selection pins DR4/3/2/1 = 1/1/0/0, and use a XTAL frequency of: LASER(current max) = 100/Rtrc tolerance +/- 25 %. Whilst TRC sets the maximum current ( to prevent damage to the laser during the adjustment procedure), the actual current to the Laser is determined by the external component VR2. The adjustment procedure is described in the following section. Adjustment Procedure Select the appropriate mode using the pins DP(1:4) (see section headed Operational Modes). Choose a value for the resistor Rtrc that delivers sufficient current to correctly drive the laser at the desired power, with sufficient power margin to compensate for temperature/voltage changes and potential laser degradation. In many applications the value of Rtrc will be set to the maximum current using a resistor value of 800 Ω. XTAL = (38.4 / 64) * 9.216 MHz = 5.5296 MHz. Other ‘non-standard’ transmission frequencies may be generated in the same way as long as the 1 - 12 MHz XTAL oscillator range is observed. A wider range of external clock frequencies may also be permissible - please check with Acapella. Cint Capacitor - CNT For a XTAL frequency range of 5 - 12 MHz the ACS401 requires a ceramic capacitor of value 22 nF - 33 nF +/- 20 % between pin CNT and GND. At frequencies lower than 5 MHz a capacitor of value 68 nF - 100 nF is recommended. It is essential that the CNT capacitor is placed very close to the ACS401. DCDB The Data Carrier Detect (DCDB) signal will go Low when the modems are locked and ready for data transmission. Prior to lock (DCDB = High), the data channels outputs RxD(1:4) are forced Low with the control lines XO(1:2) forced High. Data Rate Selection The output power from the laser may be measured directly using an optical-power meter that is capable of detecting peak opticalpower. If an average optical-power meter is employed then a correction factor of 16 must be used to obtain the peak value . The following data rates apply to TxD1, TxD2, TxD3 and TxD4 and are based on the use of a 9.216 MHz XTALor clock. LASER(peak power) = Laser(average power) * 16. ‘Standard’ mode, DR4 = 1: The external component VR2 should have a range of 0 to 50 KΩ. As VR2 is decreased, output power will first be detected when the laser begins to lase. VR2 should be reduced further until the desired output power is achieved (within the limits of the manufacturer’s specification). LED current control The LED transmit current is less critical though it is important not to exceed the LED manufacturer’s recommendation for maximum current. The current is controlled by a resistor Rtrc connected between TRC and ground. The lower the value Rtrc, the greater the current. The lower limit for Rtrc is 800 Ω while a practical maximum is 40 kΩ. The LED current is inversely proportional to Rtrc while Rtrc > 800Ω: LED(current) = 100/Rtrc tolerance +/- 25 %. PORB The Power-On Reset or PORB pin resets the device if forced Low for 100 ms or more. In normal operation PORB should be held High. Although the PORB pin has been included, e.g. for factory test, the modem has been designed to power up correctly without the aid of PORB. PORB has a special function when used in conjunction with memory lock (see section headed Diagnostic Modes). Crystal Clock Normally, a parallel resonant crystal will be connected between the pins XLI and XLO with the appropriate padding capacitors. Alternatively, it is possible to drive XLI directly by an external clock. The clock frequency for the purpose of this specification will be known as XTAL frequency. The operational range for XTAL frequency is 1 - 12 MHz, though communicating ACS401s must be clocked at the same nominal frequency. The ACS401 has been designed to operate with a XTAL tolerance of 100 ppm giving a relative tolerance of 200 ppm between communicating modems. The recommended frequency of 9.216 MHz, results in the standard range of synchronous communication frequencies tabulated in the section headed Data Rate Selection. N o n standard frequencies may be generated by using the appropriate value XTALor external clock. DR4 1 1 1 1 1 1 1 1 DR3 0 0 0 0 1 1 1 1 DR2 0 0 1 1 0 0 1 1 DR1 0 1 0 1 0 1 0 1 Data Rate 128 kbps 64 kbps 32 kbps 16 kbps 64 kbps 32 kbps 32 kbps 16 kbps No. of Channels Single Single Single Single Dual Dual Four Four Data Rate 64 kbps 32 kbps 16 kbps 32 kbps 16 kbps 16 kbps No. of Channels Single Single Single Dual Dual Four ‘Double’mode, DR4 = 0: DR4 0 0 0 0 0 0 DR3 0 0 0 1 0 1 DR2 0 1 1 0 0 1 DR1 1 0 1 1 0 1 In ‘standard’ mode internal timing accommodates fiber length delays of up to 95 km, link budget permitting. In ‘double’mode the internal timing accommodates fiber length delays of up to 190 km, link budget permitting. ‘Double’ mode essentially halves the frequency of the internal clock and therefore doubles the period of the internal machine cycle, this also has the effect of doubling the duration of LED/LASER transmit pulses, which in turn is likely to lead to improved link budgets, particularly where LEDs or LASERs of higher than recommended capacitance are employed. Bandwidth * Channel Product The ACS401 has a Bandwidth Channel Product (BCP) of 128 kHz in ‘standard’ mode and 64 kHz in ‘double’ mode using the recommended XTAL frequency of 9.216 MHz. The BCP is proportional to the XTAL frequency and is specified as: BCP(kHz) = 128 * XTAL / ( 9.216 *10 6 * n) XTAL = frequency of XTALoscillator. n = 1 for ‘standard’mode; n = 2 for ‘double’ mode. The given maximum bandwidth may be shared by up to 4 channels as shown in the following tables for both ‘standard’ and ‘double’ modes and a XTAL frequency of 9.216 MHz. ‘Standard’ mode - XTAL = 9.216 MHz Bandwidth per channel 32 kHz 64 kHz 128 kHz 16 kHz 32 kHz 64 kHz 32 kHz 16 kHz No of Channels 4 2 1 4 2 1 1 1 BCP 128 128 128 64 64 64 32 16 kHz kHz kHz kHz kHz kHz kHz kHz ‘Double’ mode - XTAL= 9.216 MHz Bandwidth per channel 16 kHz 32 kHz 64 kHz 16 kHz 32 kHz 16 kHz No of Channels 4 2 1 2 1 1 frequency, RxCL is generated from a Digital Phase-Lock Loop (DPLL) system (except where master mode has been selected). The DPLLmakes periodic corrections to the output RxCL clock to compensate for differences in the XTAL frequencies. In the case of an externally supplied transmission clock TxCL, compensation is also made for differences in frequency between the supplied data clock and the selected clock rate defined by DR(1:4). The DPLL is adaptive and will minimise the frequency of correction and jitter, where the XTALfrequency and transmission clocks are tightly toleranced. Diagnostic Modes BCP 64 64 64 32 32 16 kHz kHz kHz kHz kHz kHz The ACS401 has eight diagnostic modes controlled by DM(1:3). These are shown in the following table. Control Signals Diagnostic Mode Full-duplex Full-duplex Remote loopback Full-duplex Local loopback Full-duplex slave Full-duplex master Full-duplex The control signal set XI(1:2) are oversampled at a rate of: Full-duplex XTAL / 18,432 (Hz) in ‘standard’ mode In the full-duplex configuration, the RxCL clock of both devices tracks the average frequency of the TxCL clock of the opposite end of the link. The receiving Digital Phase-Lock Loop (DPLL) system makes periodic adjustments to the RxCL clock to ensure that the average frequency is exactly the same as the far-end TxCL clock. In summary, each TxCL is an independent master clock and each RxCL a slave of the far-end TxCL clock. Power consumption will be minimised by choosing the lowest BCP. XTAL / 36,864 (Hz) in ‘double’ mode The signals are filtered by a 4-bit filter ensuring that the data applied to these inputs is not easily corrupted. These signals may be used for control data regarded as critical. The sampling frequency and filtering dictates a minimum Low or High time for data applied to inputs XI(1:2) of: > (18,432 * 4) / XTAL(s) in ‘standard’ mode > (36,864 * 4) / XTAL (s) in ‘double’mode Therefore, with the recommended XTAL frequency of 9.216 MHz and ‘standard’ mode operation, the minimum High or Low time for data applied to XI(1:2) for successful propagation is 8 ms. The logic status of XI(1:2) is propagated over the link and appears at the far-end at XO(1:2). When the devices are out of lock (DCDB = High), then XO1 = XO2 = High. Transmission Clock TxCL The ACS401 gives a choice between internally and externally generated transmission clocks. When the CKC pin is held Low, TxCL is configured as an output producing a clock at the frequency defined by DR(1:4). When the CKC pin is held High, TxCL is configured as an input, and will accept an externally produced transmission clock with a tolerance of up to 500 ppm with respect to the transmission rate determined by DR(1:4). Data is latched into the device on the rising edge of the TxCL clock independent of internal or external TxCL generation. It is possible to propagate asynchronous data through the link. The TxCL clock will over-sample the data at the rate defined by DR(1-4). The choice of TxCLclock frequency dictates the sample rate of the asynchronous data appearing at the input TxD, and consequently the jitter on the output RxD at the far-end. Example: DR4/3/2/1 CKC Transmission data rate TxD data rate = = = = 1000 0 128 kbps 19.2 kbps With this set-up the over-sample factor is 128 / 19.2 = 6.67, giving an effective jitter of ~15 %. Receive Clock RxCL In synchronous mode, data is valid on the rising edge of RxCL clock (see Figure 2. Timing diagrams). To ensure that the average receive frequency is the same as the transmitted Lock Drift Memory Active Random Drift Active Drift Active DM3 0 0 0 0 1 1 1 1 DM2 0 0 1 1 0 0 1 1 DM1 0 1 0 1 0 1 0 1 Full-duplex slave In slave mode the TxCL and the RxCL clock is derived from the TxCL clock of the far-end of the link, such that the average frequency is exactly the same. Clearly, it is essential that only one modem is configured in slave mode at a time. The CKC pin is overridden such that TxCL is always configured as an output. Since only one device in the modem pair may be configured in slave mode, the mode also selects active lock. Full-duplex master In master mode the RxCL clock is internally generated from the local TxCL clock. The local TxCLclock producing the RxCLclock may be internally or externally generated. Master mode is only valid if the far-end device is configured in slave mode or if the farend TxCLclock is derived from the far-end RxCLclock. Only one modem in the communicating pair may be configured as a master. Local Loopback In local loopback mode, TxD data is looped back inside the nearend modem and is output at its own RxD output. The data is also sent to the far-end modem and synchronisation between the modems is maintained. In local loopback mode data received from the far-end device is ignored, except to maintain lock. If concurrent requests occur for local and remote loopback, local loopback is selected. The local loop diagnostic mode is used to test data flow up to, and back from, the local ACS401 and does not test the integrity of the link itself. Therefore, local loopback operates independently of synchronisation with a second modem (DCDB may be High or Low). Remote Loopback In remote loopback mode, the near-end modem sends a request to the far-end modem to loopback its received data, thus returning the data. The far-end modem also outputs the received data at its RxD. Both modems are exercised completely, as well as the LASERs/LEDs and the fiber optic link. The remote loopback test is normally used to check the integrity of the entire link from the near-end (initiating modem). Whilst a device is responding to a request for remote loopback from the far-end, requests from the near-end to initiate remote loopbacks will be ignored. Drift Lock Communicating modems attain a stable state where the ‘transmit’ window of one modem coincides with the ‘receive’ window of the other, allowing for delay through the optical link. Adjustments to machine cycles are made automatically during operation, to compensate for differences in XTAL frequencies which would otherwise cause loss of synchronisation. Drift lock synchronisation described above, depends on a difference in the XTALfrequencies at each end of the link, and the greater the difference the faster the locking. Therefore, if the difference between XTAL frequencies is very small (a few ppm), automatic locking may take tens of seconds or even minutes. Drift lock will not operate if the two communicating devices are driven by a clock derived from a single source (i.e. tolerance of 0 ppm). Active Lock Active lock mode may be used to accelerate synchronisation of a pair of communicating modems. This mode synchronises the modems with less than 3.0 seconds delay, by adjusting the machine cycles of the modems. Active lock reduces the machine cycle of the device by 0.3 % ensuring rapid lock. After synchronisation the machine cycle reverts automatically to normal. Note that only one device can be configured in active lock mode at any one time, and thus the DM(1:3) pins must not be permanently wired High on both devices in a production system. Active lock mode is usually invoked temporarily on power-up. This can be achieved on the ACS401 by connecting DM1, DM2 and DM3 together, and attaching that node to an RC arrangement with the capacitor to 5 V and the resistor to GND, to create a 5 V ➔ 0 V ramp on power-up. The RC time constant should be > 5 seconds. Device A Mode Drift Drift Drift Drift Active Active Active Random Random Memory Device B Mode Drift Active Random Memory Active Random Memory Random Memory Memory Locking Speed Drift Active Random Random Not allowed Random Random Random Random Active* * Memory lock has random lock speed for the first synchronisation HBT Status pin (‘Heartbeat’ Indicator LED) The ACS401 HBTpin affords a method of driving a display LED in a manner which is sympathetic to low power consumption. The HBT pin is pulsed to indicate ‘locked’status (DCDB = 0) and ‘out of lock’ status (DCDB = 1). The frequency of pulses is 16 times greater for ‘out of lock’ than for ‘lock’. The LED ‘on’ indicates power-up whilst the frequency of pulsing denotes locking status. Since the display LED is on for at most 6.4 % of the total time, the HBT requires little power which may be further reduced by employing high efficiency LEDs. The formulas below presume ‘standard’ mode of operation; for ‘double’ mode the XTAL value should be divided by 2. Powered-up, but not locked Frequency (Hz): XTAL / 1.152 * 10 6 Duration (s): 73,728 / XTAL On time (%): 6.4 % of time. With 9.216 MHz XTAL and ‘standard’ mode Frequency: 8 Hz (approx.) Duration : 8 ms (approx.) Random Lock Powered-up and locked Frequency (Hz): XTAL/ 18,432 Duration (s): 73,728 / XTAL On time (%): 0.4 % of time. With 9.216 MHz XTAL and ‘standard’ mode Frequency: 0.5 Hz (approx.) Duration : 8 ms (approx.) This mode achieves moderate locking times (typically 4 seconds, worst case 12 seconds) with the advantage that the ACS401’s are configured as peers. Communicating modems may be permanently configured in this mode (i.e. with hard-wired DM(1:3) pins). The HBT pin is active High and can supply up to 16 mA at a voltage of > VDD - 0.5 Volts. The display LED should be placed between the HBTpin and GND with a series resistor. The resistor value is a function of the efficiency of the display LED, and the power budget. Random lock operates even when communicating devices are driven from clocks derived from a single source. Random lock mode is compatible with drift lock and active lock. Example: Calculating the HBT resistor value Active lock will succeed even when communicating devices are driven from clocks derived from a single source (i.e. 0 ppm). Memory Lock Following the assertion of a reset (PORB = 0) communicating devices will initiate an arbitration process where within 12 seconds the communicating modems will achieve synchronisation. One establishing itself as an active lock modem and the other establishing itself as a drift lock modem. On subsequent attempts to lock, typically where the fiber has been disconnected and a new fiber inserted, synchronisation will be achieved within 3 seconds. It is only necessary to apply PORB to one device in the communicating pair to initiate an arbitration process. Since memory lock status (active or drift) uses on-chip storage, loss of power to the IC will require a new reset (PORB = 0). Furthermore, should there be a need to synchronise with a third modem, reset will again be required. Mixing Lock modes It is possible to mix all combinations of locking modes once the modems are locked, however, prior to synchronisation two modems configured in active lock will not operate. The effect of mixing locking modes on locking speed is tabulated below: LED on voltage: VDD (ACS401): Resistor voltage: Current to LED: Resistor value: 2.0 V 5.0 V 3.0 V 2 mA (high efficiency LED) 3 / 2 * 10-3 = 1500 Ω Note: The LED referred to in this section is of the inexpensive display type and should not be confused with the LED that interfaces with the fiber optic cable itself. ERC and ERL (Error Detector) These signals can be used to give an indication of the quality of the optical link. Even when a DC signal is applied to the data, handshake and TxCL inputs, the ACS401 modem transmits approximately 40 kbps over the link in each direction. This control data is used to maintain the timing and the relative positioning of ‘transmit’and ‘receive’ windows. The transmit and control data is constantly monitored to make sure it is compatible with the 3B4B format. If a coding error is detected than ERL will go High and will remain High until reset. ERL may be reset by asserting PORB or by removing the fiberoptic cable from one side of the link thereby forcing the device temporarily out of lock. ERC produces a pulse on detection of each coding error. These pulses may be accumulated by means of an external electronic counter. Please note that ERL and ERC detect coding errors and not data errors, nevertheless because of the complexity of the coding rules on the ACS401 the absence of detected errors on these pins will give a good indication of a high quality link. LASER/LED Considerations Since LEDs or LASERs from different suppliers may emit different wavelengths, it is recommended that the LASERs/LEDs in a communicating pair of modems are obtained from the same supplier. Furthermore, the emission spectrum is a function of temperature, so a temperature difference between the ends of a link reduces the responsivity of the receiving LASER/LED, resulting in a reduction in the link budget. Information is given in the suppliers’ data sheets. The following manufacturers have components that will be tested with the ACS401 and Acapella will be glad to assist with contact names and addresses on request: LED Suppliers ABB-Hafo (e.g.1A-212ST, 1A-212SMA) Acapella (e.g.A-ST, A-SMA) GCA (e.g.1A-212-ST-05, 1A-212-SM-02) Honeywell (e.g.HFE4214-013, HFE4404-013) The link budget is the difference between the power coupled to the fiber via the transmit LASER/LED and the power required to realise the minimum input amplifier current via the receive LASER/LED/PIN. The link budget is normally specified in dB or dBm, and represents the maximum attenuation allowed between communicating LASER/LEDs. The budget is utilised in terms of the cable length, cable connectors and splices. It usually includes an operating margin to allow for degradation in LASER/LED performance. The power coupled to the cable, is a function of the efficiency of the LASER/LED, the current applied to the LASER/LED and the type of the fiber optic cable employed. The conversion current produced by the reverse biased LASER/LED or PIN is a function of the LASER/LED/PIN efficiency and the fiber type. The conversion efficiency is measured in terms of its ability to convert the available optical power to current, known as the responsivity, given in (A/W). Some examples of link budgets are given in the tables headed, Link Budget Examples. The ACS401 may be used as a controller and data buffer which allows the device to be used with an external amplifier for nonfiber applications. Check with Acapella for details. Data delay and skew Operating Wavelengths The ACS401 can support any wavelength LED, ELED or LASER, from 660 nm through to 1500 nm. Power Supply Decoupling The ACS401 contains a highly sensitive amplifier, capable of responding to extremely low current levels. To exploit this sensitivity it is important to reduce external noise to a low level compared to the input signal from the LASER/LED. The modem should have an independent power trace to the point where power enters the board. Figure 3. shows the recommended power supply decoupling. The LASER/LED should be sited very close to the PINN, LAN and LAP pins. A generous ground plane should be provided, especially CKC SETB GND XI1 TxD3 XI2 TxD4 HBT DCD GND CLK9 RxD2 RxD1 XTI XTO GND GND NC VD+ VD+ TxCL TxD2 ERRL TxD1 RxCL NC IC DCDB VD+ ERRC RxD4 XO2 XO1 RxD3 Link Budgets Digital Mode Duplex Suppliers GCA 90-0359 Siemens SBM 51214X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 around the sensitive PINN, LAN and LAP pins. The modem should be protected from EMI/RFI sources in the standard ways. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 The Full Duplex Delay (FDD) of TxD and control signals XI(1:2) when using the recommended XTAL frequency of 9.216 MHz (FDD9.216MHz ) are as follows: TxD FDD9.216MHz TxD FDD9.216MHz = = 4 ms (‘standard’mode) 8 ms (‘double’ mode) XI FDD9.216MHz XI FDD9.216MHz = = 10 ms (‘standard’mode) 20 ms (‘double’ mode) For other XTAL frequencies, the delay is inversely proportional to the XTAL frequency using the above delays as the constant of proportionality. FDDXTAL = (9.216 * 10 6 / XTAL) * FDD9.216MHz The synchronous data skew between the main data channels RxD1, RxD2, RxD3 and RxD4 across the link is zero data-bits. ACAPELLA ACS401 1-Fiber Modem Figure 1. Top view of 68 PLCC package NC = Not Connected IC = Internally Connected 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 DM3 VD+ DM2 DM1 DR1 DP2 DP1 NC NC NC TRC IC VA+ LAP LAN PINP PINN CON2 CNT AGND CON1 VG+ NC NC NC GND DP3 GND PORB DP4 DR4 DR3 GND DR2 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 twh twl tf tr 90 % % 90 % 10 % % % 10 % Digital Outputs rise and fall times TxCL and RxCL clock pulse widths TxCL RxCL tsut tht tsur TxD thr RxD Transmit set-up and hold times Receive set-up and hold times Figure 2. Timing diagrams VD+ pins 19, 20, 29 and 67. GND pins 3, 10, 16, 17, 36, 41 and 43 . 1 kΩ CON1 VG+ 10 nF ACS401 V+ +5V GND 47µH µH CON2 Pin 48 and Pin 51 should be connected together TRC VA+ Rtrc > 800 Ω SETB 47µHµH 47 µH µF 100 nF 100 nF ACS401 GND VD+ GND 22- CNT ACS401 GND 100 nF AGND GND All capacitors should be placed very close to the ACS401. ACS401 GND Figure 3. Recommended power supply layout ACS401 ACS401 TxD1 RxD1 TxD2 RxD2 TxD3 RxD3 TxD4 RxD4 RxD1 TxD1 RxD2 TxD2 RxD3 TxD3 RxD4 TxD4 4 **Synchronous Synchronous Channels Channels XO1 XI1 XO2 XI2 4 **Asynchronous Asynchronous Channels Channel Single Fiber Link XI1 XO1 XI2 XO2 Figure 4. 6 Full-duplex channels over a single fiber Single Fiber Duplex LASER link Single Fiber LED link Link Budget Example (Rtrc set so LED launch current = 100 mApeak) Fibertype Fibersize Minimum transmit couple power to fiber (µW) Minimum LED responsivity (AW) Minimum ACS401 sensitivity (nA) Minimum input power to ACS401 amplifier (µW) Link budget (dB) Plastic 1000 micron 1000 0.01 500 50 13 Glass 62.5 micron 100 0.1 500 5 13 Glass 50 micron 50 0.12 500 4.1 11 Link Budget Example (LASER launch power = 1 mW) Fibertype Fibersize Minimum transmit couple power to fiber (µW) Minimum PIN responsivity (AW) Minimum ACS401 sensitivity (nA) Minimum input power to ACS401 amplifier (µW) Link budget (dB) (single mode fiber attenuation = 0.3 dB km) Glass (single mode) 9 micron 1000 0.35 500 1.43 28.4 Absolute Maximum Ratings Parameter Dynamic Characteristics Symbol Min Max Units Parameter Symbol Min Typ Max Units XTAL 1.0 9.216 12 MHz VDD -0.3 6.0 V Crystal frequency (XT1, XTO) Input voltage (non-supply pins) Vin GND - 0.3 VDD + 0.3 V External clock (XTI) High or Low time fclp 40 - 60 % Input current (except LAN,LAP,PINN,PINP,CNT) Iin - 10.0 mA RxD and TxD data rate ‘standard’mode ‘double’mode fclp XTAL/576 XTAL/576 - XTAL/72 XTAL/144 bps Input current (LAN, LAP,PINN,PINP,CNT) Iin - 1.0 mA RxCLand TxCLduty cycle (with TxCL= output) twh twl - 50 - % Tstor -50 160 ˚C Frequency deviation at TxCLfrom selected value (with TxCL= input) Fd 500 - - ppm TxD to TxCLset-up time tsut 300 - - ns TxD to TxCLhold time tht 25 - - ns - 0.5 * (1/RxCL) - ns - ns Power supply VD+ and VA+ (VDD = VD+ or VA+) Storage temperature Operating Conditions Parameter Symbol Power supply (VA+ and DA+) V+ Ambient temperature range TA Min -40 Typ Max Units 5.0 5.25 V - 85 ˚C Static Digital Input Characteristics (for specified operating conditions) Input pins: DR 1/2/3/4, DM 1/2/3, DP1/2/3/4 CKC, TXD1/2/3, PORB, TxCL(input) Parameter Symbol Min Typ Max Units Vin High Vih 2.0 - - V Vin Low Vil - - 0.8 V - - 10 µA RxD to RxCLset-up time tsur RxD to RxCLhold time thr - 0.5 * (1/RxCL) Digital output - fall time tf - - 100 ns Digital output - rise time tr - - 100 ns Power consumption with LASER/LED peak current = 50mA Single channel 64 kbps (Note 2) Pc - 35 - mW Note 2: Power consumption assumes CMOS loads. Check with Acapella for other bandwidth products. Matching Characteristics (for specified operating conditions Parameter Input currentIin Crystal tolerance use parallel resonate crystal and recommended padding capacitors Symbol Min Typ Max Units Ct -100 0 100 ppm - - 500 nA Minimum amplifier sensitivity Static Digital Input Characteristics (for specified operating conditions) Input pins: XI1, XI2, SETB. Parameter Symbol Min Typ Max Units Vin High Vih 2.0 - - V Vin Low Vil - - 0.8 V Pull-up resistor PU 50k 125k 340k Ω Input current (Note 1) Iin - - 100 µA Maximum amplifier input current Imax 1 - - mA Rtre placed between TRC and GND Rtrc 0.8k - 40k Ω Laser current (max limit) Rtrc=0.8 kOhm Rtrc=40 kOhms Ilaser 75 1.8 100 2.5 125 3.2 mA Iled 75 1.8 100 2.5 125 3.2 mA LED capacitance with Vr=0 with Irec=500 nA with Irec=1000 nA CI - - 50 100 pF LED leakage current Vr=1.4 Lleak - - 500 nA LED current Rtrc=0.8 kOhm Rtrc=40 kOhm Single-Fibermode Parameters Note 1: Input current is mainly attributed to pull-up resistor, so it applies when input is Low.The High input current is <10µA. Static Digital Output Characteristics (for specified operating conditions) Output pins: RxD1/2/3, XO1 XO2, DCDB, ERRL, ERRD, RxCL, CLK9, TxCL(output), HBT. Symbol Min Typ Max Units Vout Low (Iin = 4mA) except HBT Parameter Vol 0 - 0.5 V Vout High (Iout = 4mA) except HBT Voh VDD-0.5 - - V Vout Low (Iin - 16mA) HBT Vol 0 - 0.5 V Vout High (Iout = 16mA) HBT Voh VDD-0.5 - - V Max load capcitance CI - - 50 pF LED reverse bias LASER PIN diode leakage current Vrp=4.0V LASER PINdiode reverse bias PINleakage current Epsilon House Chilworth Research Centre Southampton SO16 7NP England UK Tel. UK Fax. PINreverse bias 01703 769 008 01703 768 612 Intn’l. Tel. +44 1703 769 008 Intn’l. Fax. +44 1703 768 612 In the interest of further product development Acapella reserve the right to change this specification without further notice. ©Copyright, Acapella Ltd., 1997 0.65 1.15 1.4 V - - 100 nA Vrp - - 4.0 V CI - - 20 pF Dual-Fibermode Parameters PIN capacitance with Vr=0 Acapella Ltd. Vr Pleak Lleak - - 150 nA Vr 0.95 1.15 1.4 V Email: [email protected] Web: www.acapella.co.uk