® SP9500 12–Bit, Voltage Output D/A Converter ■ ■ ■ ■ Low Power – 1.1mW Voltage Output, 0.5V to 4.5V Range Single +5 Volt Supply 1.4 MHz Multiplying Bandwidth (2-Quadrant) ■ Standard 3-Wire Serial Interface ■ 8–pin (0.15") SOIC and Plastic DIP Packages DESCRIPTION… The SP9500 is a low power 12-Bit Digital-to-Analog Converter. It features 0.5 to 4.5V output swing when using +5volt supply. The converter uses a standard 3–wire serial interface compatible with SPI™, QSPI™ and Microwire™. The output settling-time is specified at 7.5µs. The SP9500 is available in 8–pin 0.15" SOIC and DIP packages, specified over commercial and industrial temperature ranges. VREF DAC REGISTER LATCH DAC + – VOUT AGND SHIFT REGISTER CS DIN SCLK SP9500DS/04 SP9500 12-Bit, Voltage Output D/A Converter 1 © Copyright 2000 Sipex Corporation ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VDD - DGND .................................................................. -0.3V,+6.0V VREF ................................................................................ DGND, VDD AGND .......................................................................... DGND, V REF DIN .................................................................................. DGND, VDD Power Dissipation Plastic DIP .......................................................................... 375mW (derate 7mW/°C above +70°C) Small Outline ...................................................................... 375mW (derate 7mW/˚C above +70˚C) SPECIFICATIONS (Typical at 25˚C; TMIN ≤ TA ≤ TMAX; VDD = +5V, DGND = 0V, VREF = +3.5V; AGND = +1.5V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.) PARAMETER DIGITAL INPUTS Logic Levels VIH VIL 2 Quad, Input Coding REFERENCE INPUTS VREF Voltage Range AGND Voltage Range Input Resistance ANALOG OUTPUT Gain –B, –K –A, –J Initial Offset Bipolar Voltage Range Output Current STATIC PERFORMANCE Resolution Integral Linearity –B, –K –A, –J Differential Linearity –B, –K –A, –J Monotonicity DYNAMIC PERFORMANCE Settling Time Small Signal Full Scale Slew Rate Multiplying Bandwidth STABILITY Gain Scale Zero SP9500DS/04 MIN. TYP. MAX. 2.4 0.8 UNITS CONDITIONS Volts Volts Binary Note 5 0.5 0.5 11 4.5 4.5 13.9 ±0.5 ±1.0 ±1.0 ±0.25 0.5 ±1.0 ±2.0 ±4.0 ±5.0 ±3.0 4.5 12 Volts Volts kΩ LSB LSB LSB LSB Volts mA DIN = 1365; code dependent Note 3 Note 3 VREF = 4.5V; AGND = 0.5V DIN = 0 Bits ±0.25 ±0.5 ±0.5 ±0.5 ±1.0 LSB LSB LSB ±0.25 ±0.75 ±0.25 ±1.0 Guaranteed LSB LSB Note 3 Note 3 VREF = 4.5V; AGND = 0.5V 1 7.5 0.6 1.4 µs µs V/µs MHz to 0.012% to 0.012%, VOUT = 0.5 to 4.5V 15 15 ppm/˚C ppm/˚C tMIN to tMAX tMIN to tMAX SP9500 12-Bit, Voltage Output D/A Converter 2 © Copyright 2000 Sipex Corporation SPECIFICATIONS (continued) (Typical at 25˚C; TMIN ≤ TA ≤ TMAX; VDD = +5V, DGND = 0V, VREF = +3.5V; AGND = +1.5V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.) PARAMETER POWER REQUIREMENTS VDD –J, –K –A, –B Power Dissipation MIN. TYP. MAX. UNITS 0.22 0.22 1.1 0.34 0.50 mA mA mW CONDITIONS Note 5 +5V, ±3%; Note 4, 5 SWITCHING CHARACTERISTICS CS Setup Time (tCSS) 25 ns SCLK Fall to CS Fall Hold Time (tCSH0) 20 ns SCLK Fall to CS Rise Hold Time (tCSH1) 0 ns SCLK High Width (tCH) 40 ns SCLK Low Width (tCL) 40 ns DIN Setup Time (tDS) 50 ns DIN Hold Time (tDH) 0 ns CS High Pulse Width (tCSW) 30 ns ENVIRONMENTAL AND MECHANICAL Operating Temperature –J, –K –A, –B Storage Package –_N –_S 0 –40 –60 +70 +85 +150 °C °C °C 8-pin Plastic DIP 8-pin 0.15" SOIC Notes: 1. Integral Linearity, for the SP9500, is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input condition. 2. Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two adjacent digital input codes. 3. 1 LSB = (VREF-AGND)/4,096. 4. VREF = AGND = 2.5V. 5. The following Power up sequence is recommended: VDD (+5V), VREF. SP9500DS/04 SP9500 12-Bit, Voltage Output D/A Converter 3 © Copyright 2000 Sipex Corporation THEORY OF OPERATION PINOUT – 8-PIN PLASTIC DIP & SOIC VOUT 1 8 VREF VDD 2 7 AGND SCLK 3 6 DGND DIN 4 5 CS SP9500 The SP9500 consists of four main functional blocks – the input shift register, DAC register, 12-Bit D/A converter and a output buffer amplifier, Figure 1. The input shift register is used to convert the serial input data stream to a parallel 12–Bit digital word. The input data is shifted on positive clock (SCLK) edges when the Chip Select (CS) signal is in the “low” state. The MSB is loaded first and LSB last. No shifting of the input data occurs when the Chip Select (CS) signal is in the “high” state. PIN ASSIGNMENTS The DAC register is used to store the digital word which is sent to the R–2R DAC. Its value is updated on the positive transition of the Chip Select (CS) signal. Pin 1- VOUT - Voltage Output. Pin 2- VDD - +5V Power Supply Input. Pin 3- SCLK - Serial Clock Input. The 12–Bit D/A converter is an “inverted” R-2R ladder network. The DAC itself is implemented with precision thin-film resistors and CMOS transmission gate switches. The resistor network is laser-trimmed to achieve better than 12– Bit accuracy. The D/A converter is used to convert the 12-bit input word to a precision voltage. Pin 4- DIN - Serial Data Input. Pin 5- CS - Chip Select Input. Pin 6 - DGND - Digital Ground Pin 7- AGND - Analog Ground. Pin 8- VREF - Reference Input. The operational amplifier is a rail-to-rail input, rail-to-rail output CMOS amplifier. It is capable of supplying 1mA of load current in the 1.5 to 3.5 output voltage range. The initial offset voltage is laser-trimmed to improve accuracy. Settling time is 7.5 µs for a full scale output transition to 0.012% accuracy. FEATURES... The SP9500 is a low power 12–Bit Digital-toAnalog Converter. The converter features 0.5 to 4.5 volt output swings with a single +5V supply. The input coding format used is standard binary, Table 1. This Digital-to Analog Converter uses a standard 3–wire interface compatible with SPI™, QSPI™ and Microwire™. The output settling time is specified at 7.5 µs to full 12-bit accuracy when driving a 10KΩ, 10pF load combination. INPUT MSB The SP9500 Digital-to-Analog Converter is ideally suited for applications such as ATE, process controllers, robotics and instrumentation. The SP9500 is available in an 8-pin 0.15" SOIC and 0.3" PDIP packages, specified over commercial and industrial temperature ranges. SP9500DS/04 OUTPUT LSB 1111 1111 1111 VREF - 1 LSB 1111 1111 1110 VREF - 2 LSB 0000 0000 0001 AGND + 1 LSB 0000 0000 0000 1 LSB = AGND (VREF-AGND) 2 12 Table 1. Binary Coding SP9500 12-Bit, Voltage Output D/A Converter 4 © Copyright 2000 Sipex Corporation +0.5 lsb DNLE -0.5 lsb +0.5 lsb INLE -0.5 lsb 0 CODE 4095 DNLE, INLE Plots USING THE SP9500 External Reference The R-2R DAC input resistance is code dependent and is minimum (11kΩ) at code 1365 and 2731. And, it is nearly infinite at code 0. Because of the code-dependent nature of the reference inputs, a high quality, low output impedance amplifier should be used to drive the VREF and AGND inputs. SCLK periods plus the CS high pulse width tCSW. This is equal to a 1 µs or 1 MHz update rate. However, the DAC settling time to 12–Bits is 7.5 µs, which for full scale output transitions would limit the update rate to 125 kHz. Logic Interface The SP9500 is designed to be compatible with TTL and CMOS logic levels. However, driving the digital inputs with TTL level signals will increase the power consumption of the part by 300 µA. In order to achieve the lowest power consumption use rail-to-rail CMOS levels to drive the digital inputs. Serial Clock and Update Rate The SP9500 maximum serial clock rate (SCLK) is given by 1/(tCH+tCL) which is approximately 12.5 MHz. The digital word update rate is limited by the chip select period, which is 12 X VREF DAC DAC REGISTER REGISTER DIN 1 SHIFT REGISTER 12 LATCH 12 DAC + – VOUT AGND Figure 1. Detailed Block Diagram WHERE… VREF VOUT = VDAC + DIN – AGND Figure 2. Transfer Function SP9500DS/04 VOUT VDAC = ( DIN 4096 ) x (VREF - AGND) + AGND VDAC SP9500 12-Bit, Voltage Output D/A Converter 5 © Copyright 2000 Sipex Corporation CS tCSHO tCSS tCH tCSW tCL tCSH1 SCLK tDH tDS DIN DB11 DB9 DB10 DB8 DB0 Figure 3. Timing Diagram SCLK SK DIN SO I/O CS N/C SI MICROWIRE PORT SP9500 Figure 4. Microwire Connection SK SCLK MOSI DIN I/O CS N/C MISO SPI PORT SP9500 CPOL = 0, CPHA = 0 Figure 5. SPI Connection SP9500DS/04 SP9500 12-Bit, Voltage Output D/A Converter 6 © Copyright 2000 Sipex Corporation PACKAGE: PLASTIC DUAL–IN–LINE (NARROW) E1 E D1 = 0.005" min. (0.127 min.) A1 = 0.015" min. (0.381min.) D A = 0.210" max. (5.334 max). C A2 B1 B e = 0.100 BSC (2.540 BSC) Ø L eA = 0.300 BSC (7.620 BSC) ALTERNATE END PINS (BOTH ENDS) DIMENSIONS (Inches) Minimum/Maximum (mm) 8–PIN 14–PIN 16–PIN 18–PIN 20–PIN 22–PIN A2 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) B 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) B1 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) C 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) D 0.355/0.400 0.735/0.775 0.780/0.800 0.880/0.920 0.980/1.060 1.145/1.155 (9.017/10.160) (18.669/19.685) (19.812/20.320) (22.352/23.368) (24.892/26.924) (29.083/29.337) E 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) E1 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) L 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) Ø 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) SP9500DS/04 SP9500 12-Bit, Voltage Output D/A Converter 7 © Copyright 2000 Sipex Corporation PACKAGE: PLASTIC SMALL OUTLINE (SOIC) (NARROW) E H h x 45° D A Ø e B DIMENSIONS (Inches) Minimum/Maximum (mm) SP9500DS/04 A1 L 8–PIN 14–PIN 16–PIN A 0.053/0.069 (1.346/1.748) 0.053/0.069 (1.346/1.748) 0.053/0.069 (1.346/1.748) A1 0.004/0.010 (0.102/0.249 0.004/0.010 (0.102/0.249) 0.004/0.010 (0.102/0.249) B 0.014/0.019 (0.35/0.49) 0.013/0.020 (0.330/0.508) 0.013/0.020 (0.330/0.508) D 0.189/0.197 (4.80/5.00) 0.337/0.344 0.386/0.394 (8.552/8.748) (9.802/10.000) E 0.150/0.157 (3.802/3.988) 0.150/0.157 (3.802/3.988) 0.150/0.157 (3.802/3.988) e 0.050 BSC (1.270 BSC) 0.050 BSC (1.270 BSC) 0.050 BSC (1.270 BSC) H 0.228/0.244 (5.801/6.198) 0.228/0.244 (5.801/6.198) 0.228/0.244 (5.801/6.198) h 0.010/0.020 (0.254/0.498) 0.010/0.020 (0.254/0.498) 0.010/0.020 (0.254/0.498) L 0.016/0.050 (0.406/1.270) 0.016/0.050 (0.406/1.270) 0.016/0.050 (0.406/1.270) Ø 0°/8° (0°/8°) 0°/8° (0°/8°) 0°/8° (0°/8°) SP9500 12-Bit, Voltage Output D/A Converter 8 © Copyright 2000 Sipex Corporation ORDERING INFORMATION Model .................................................................................. Temperature Range ....................................................................................... Package Monolithic 12-Bit DAC Voltage Output: SP9500JN ................................................................................ 0˚C to +70˚C .......................................................................... 8-pin, 0.3" Plastic DIP SP9500KN ............................................................................... 0˚C to +70˚C .......................................................................... 8-pin, 0.3" Plastic DIP SP9500JS ................................................................................ 0˚C to +70˚C ................................................................................. 8–pin, 0.15" SOIC SP9500KS ............................................................................... 0˚C to +70˚C ................................................................................. 8–pin, 0.15" SOIC SP9500AN ............................................................................... –40˚C to +85˚C ...................................................................... 8-pin, 0.3" Plastic DIP SP9500BN ............................................................................... –40˚C to +85˚C ...................................................................... 8-pin, 0.3" Plastic DIP SP9500AS ............................................................................... –40˚C to +85˚C ............................................................................. 8–pin, 0.15" SOIC SP9500BS ............................................................................... –40˚C to +85˚C ............................................................................. 8–pin, 0.15" SOIC Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: [email protected] Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. SP9500DS/04 SP9500 12-Bit, Voltage Output D/A Converter 9 © Copyright 2000 Sipex Corporation