SL74HCU04 Hex Unbuffered Inverters High-Performance Silicon-Gate CMOS The SL74HCU04 is identical in pinout to the 74LS04. This contain six independent unbuffered inverters. These inverters are well suited for use as oscillators, pulse shapers and in many other applications requiring a high-input impedance amplifier. This device is characterized for over wide temperature ranges to meet industry and ation over military specifications. • Low Power consumption characteristic of CMOS devices • Output drive capability: 10 LS TTL Loads Min. • Operating speed superior to LS TTL • Wide operating voltage range: 2.0 to 6.0 V • Low input current: 1.0 µA Max. • Low quiescent current: 20µA Max. • High noise immunity characteristic of CMOS • Diode protection on all inputs ORDERING INFORMATION SL74HCU04N Plastic SL74HCU04D SOIC TA = -55° to 125° C for all packages igh-Performance??Silicon-Gate LOGIC DIAGRAM FUNCTION TABLE PIN 14 =VCC PIN 7 = GND SLS System Logic Semiconductor Inputs Output A Y L H H L SL74HCU04 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN IOUT Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HCU04 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit V 25 °C to -55°C ≤85 °C ≤125 °C Unit Minimum HighLevel Input Voltage 2.0 4.5 6.0 1.7 3.6 4.8 1.7 3.6 4.8 1.7 3.6 4.8 V VIL Maximum Low Level Input Voltage 2.0 4.5 6.0 0.3 0.8 1.1 0.3 0.8 1.1 0.3 0.8 1.1 V VOH Minimum HighLevel Output Voltage 2.0 4.5 6.0 1.8 4.0 5.5 1.8 4.0 5.5 1.8 4.0 5.5 V 4.5 6.0 3.86 5.36 3.76 5.26 3.7 5.2 2.0 4.5 6.0 0.2 0.5 0.5 0.2 0.5 0.5 0.2 0.5 0.5 VIN=VIH or VIL IOL = 4 mA IOL = 5.2 mA 4.5 6.0 0.32 0.32 0.37 0.37 0.4 0.4 Symbol Parameter VIH Test Conditions VIN=VIH or VIL IOH = -20 µA VIN=VIH or VIL IOH = -4 mA IOH = -5.2 mA VOL Maximum LowLevel Output Voltage VIN=VIH or VIL IOL = 20 µA V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0 µA 6.0 2.0 20 40 µA SLS System Logic Semiconductor SL74HCU04 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol Parameter Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit tPLH, t PHL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tTLH, t THL Maximum Output Transition Time, Any Output (Figures 1 and 2) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns - 10 10 10 pF CIN CPD Maximum Input Capacitance Power Dissipation Capacitance (Per Inverter) Typical @25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 15 pF Figure 1. Switching Waveforms * Includes all probe and jig capacitance Figure 2. Test Circuit SLS System Logic Semiconductor