CXA1898Q Recording/Playback Equalizer Amplifier Description The CXA1898Q is an IC developed for analog signal processing in tape recorders. Processing for both the recording and playback systems is achieved on one chip. Features • Recording equalizer Gp and Fp can be adjusted externally. • Recording mute function • AGC (Automatic Gain Control) • Comparator for AMS (Automatic Music Sensor) • Recording/playback equalizer amplifier with 1.7 times speed switching • 11-bit serial data interface Structure Bipolar silicon monolithic IC Absolute Maximum Ratings • Supply voltage • Operating temperature • Storage temperature • Allowable power dissipation VCC 12 V Topr –20 to +75 °C Tstg –65 to +150 °C PD 735 mW Operating Conditions Supply voltage VCC 6.5 to 10.0 48 pin QFP (Plastic) Applications All analog signal processing in the cassette decks of tape recorders and compact music centers (Applicable to Sankyo Seiki mfg. Co., Ltd. YK47R-KF202 R/P head or equivalent) V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94329B78 CXA1898Q RFC VCC VG GND AGC TC AGC IN2 REC IN2 AGC OUT2 REC OUT2 D GND XRESET DATA Block Diagram and Pin Configuration (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 GND 10k IREF AGC GAIN 19.5dB GND PB OUT2 38 PB FB22 39 D2 GND 70k GND 70k AGC GND PB INA2 42 D3 B EQ A EQ AGC OFF D8 PB INA1 43 GND 70k PB INB1 44 GND PB FB11 45 210k 40k PB OUT1 47 D9 D8 D10 D9 10k AMS AMS GAIN 48 D7 RECEQ PB FB21 46 AGC GAIN 19.5dB MUTE GND D6 SPEED B EQ 210k D4 D5 RECEQ CTL GND LATCHES 70k DECK A/B D10 SPEED D9 SHIFT REGISTERS PBEQ CTL GND 22 M2 D1 GND PB INB2 41 23 LATCH 40k 210k GND 210k PB FB12 40 24 CLK RECEQ IREF 37 D11 D11 GND GND GND GND GND GND GND GND GND AMS OUT AMS GND FP CAL GP CAL AGC IN1 –2– 7 8 9 10 11 12 RMUTE1 I 6 B EQ 5 A EQ 4 REC OUT1 3 AGC OUT1 2 REC IN1 1 AMS FIL GND GND 21 M1 20 PL2 19 PL1 18 BPB 17 BPA 16 PB MUTE 15 SPEED 14 R MUTE2 13 R MUTE1 CXA1898Q Pin Description Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit VCC 6 31 AGC IN1 AGC IN2 VCC 147 4.0V I 50kΩ Description AGC signal input. Input resistance changes between 47kΩ and 3kΩ 3k 6 31 47k ×4 VGS GND VCC VCC 147 7 30 REC IN1 REC IN2 23k 7 4.0V I 50kΩ 30 Recording equalizer input. 50k 1.8k VGS VGS GND GND VCC VCC ×2 8 29 AGC OUT1 AGC OUT2 147 4.0V O 147Ω 18.8k 500 8 500 29 47.8k ×4 VGS AGC output pin. AGC is applied at –11dBm or more. 5.3k GND GND GND VGS VCC VCC ×3 40k 500 9 28 REC OUT1 REC OUT2 4.0V O 147Ω ×2 9 28 147 500 × 10 GND GND –3– 5p Recording equalizer output. CXA1898Q Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit Description VCC VCC A deck equalizer switch. Low: 120µs EQ High: 70µs EQ 147 10 A EQ — I 10 — GND GND VCC VCC 11 B EQ 2.5V (when open) 147 50k I 53kΩ B deck equalizer switch. Low: Normal Tape, 120µs EQ High: CrO2 Tape, 70µs EQ Medium: Metal Tape, 70µs EQ 5k 11 5k GND GND VCC VCC 50µA 20k 20k ×2 12 RMUTE1 I — I — ×2 147 12 2.7V GND GND 13 14 R MUTE1 R MUTE2 VDD 15 SPEED 5.0V (when reset) (when Pin 25 (DATA) is set to high) VCC ×4 O — 5k 13 5k 14 15 ×4 Output for recording mute ON/OFF switch control signal. Outputs D11 from Pin 25 (DATA). Output for recording/ playback equalizer speed switch control signal. Outputs D9 from Pin 25 (DATA). Low: Normal Speed High: High Speed (1.7 times) 16 GND GND 16 20k Recording mute ON/OFF switch. Low: Mute OFF High: Mute ON ∗ Fader function is realized by the external time constant circuit. Connects Pin 13 (RMUTE1). PB MUTE –4– Output pin for playback mute ON/OFF switch control signal. Outputs D7 from Pin 25 (DATA). Connects a resistor to VDD for Pins 13 to 16. CXA1898Q Pin No. Symbol 17 BPA 18 BPB 19 PL1 20 PL2 21 M1 DC voltage I/O I/O resistance Equivalent circuit Description VDD 5.0V (when reset) (when Pin 25 (DATA) is set to high) VCC Outputs D5 from Pin 25 (DATA). ×4 O Outputs D4 from Pin 25 (DATA). 10k — 17 18 Outputs D3 from Pin 25 (DATA). ×4 19 20k Outputs D2 from Pin 25 (DATA). 20 GND 21 22 M2 23 LATCH Outputs D1 from Pin 25 (DATA). GND 22 VCC 25µA 23 26 I — 26 ×4 XRESET 24k 5p 10.5k GND Serial data interface latch input. 100µA 2k — Outputs D6 from Pin 25 (DATA). GND Serial data interface reset input. Low: Reset. At this time serial data outputs (Pins 13 to 22) are all open (high). VCC 24 25µA CLK 100µA 4k Serial data interface clock input. 24 — I — 25 ×4 24k 10.5k GND 25 Serial data interface serial data input. DATA GND VCC VCC ×2 ×2 200 32 AGC TC 0.0V — — 500 32 147 ×2 500 5k 100k GND –5– GND ×4 200 Connects a resistor and capacitor for determining AGC attack/recovery time constants. CXA1898Q Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit Description VCC VCC 30k ×2 ×2 34 VG 4.0V — 60kΩ 500 To each 500 VSG 147 34 ×4 45k Signal reference voltage. Connects a capacitor for ripple rejection. 30k GND 35 VCC 8.0V — — GND 35 VCC VCC VCC ×3 36 RFC 8.0V — Power supply. Connects a resistor and capacitor for obtaining stable voltage with power supply ripple rejected. ×3 — 36 × 250 147 To each RFS GND VCC VCC ×3 5p 500 38 47 PB OUT2 PB OUT1 38 2.8V O 147Ω 47 500 147 ×6 GND GND –6– 5k × 2 ×2 Playback equalizer output. CXA1898Q Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit Description RFS VCC 39 46 PB FB22 PB FB21 2.8V — — 39 2k ×4 ×4 Connects a capacitor for determining playback equalizer time constants, such as 120µs and 70µs. ×3 7k ×3 147 2k 46 GND GND VCC 40 45 PB FB12 PB FB11 1.4V — 105kΩ GND VCC RFS 10k VCC Playback equalizer negative feedback. VCC 10k 1k 41 42 147 PB INB2 PB INA2 PB INA1 PB INB1 44 0.0V I ×2 ×6 43 41 42 43 44 1k ×6 210k 5p 40 147 70k 210k 70kΩ GND GND GND VCC AMS GAIN 3.5V — — Connects a resistor for determining AMS signal detection level and a capacitor for determining HPF cut-off frequency. 100k 48 147 GND Playback equalizer input. VCC 10µ 48 45 GND Note) The resistance of open collector outputs (Pins 2 and 13 to 22) can be also connected to VCC. –7– CXA1898Q Electrical Characteristics (Ta = 25°C, VCC = 8.0V, VDD = 5.0V, refer to Electrical Characteristics Measurement Circuit) Item Measurement conditions Min. Typ. Max. Unit VCC 6.5 8.0 10.0 V Current consumption NORM–NS, VCC = 8V, No signal 13.5 18.0 22.5 mA AGC ON output level Pin 32 external R300kΩ/ /C47µF f = 1kHz, Vin = –25dBm –13.0 –11.0 –9.0 dBm AGC ON channel balance Pin 32 external R300kΩ/ /C47µF f = 1kHz, Vin = –15dBm –2.0 0.0 2.0 dB AGC ON distortion Pin 32 external R300kΩ/ /C47µF f = 1kHz, Vin = 0dBm — 0.3 1.5 % AGC OFF output level Pin 32 external R300kΩ/ /C 47µF f = 1kHz, Vin = –25dBm –7.5 –5.5 –3.5 dBm No signal detection threshold level Pin 48 external R9.1kΩ, C0.015µF Pin 1 external R100kΩ/ /C0.1µF f = 5kHz, 0dB = –21dBm (at PBEQ reference output level) –11.5 –8.2 — dB 120µs–NS frequency response f = 315Hz, Vin = –70dBm Reference for frequency response –23.0 –21.0 –19.0 dBm 120µs–NS frequency response f = 2.7kHz, Vin = –58.5dBm at 120µs–NS, 315Hz –0.1 1.3 2.9 70µs–NS frequency response f = 4.5kHz, Vin = –53.8dBm at 120µs–NS, 315Hz –0.1 1.7 2.9 120µs–HS frequency response f = 5.3kHz, Vin = –52.5dBm at 120µs–NS, 315Hz 1.8 3.0 4.8 70µs–HS frequency response f = 9.1kHz, Vin = –47.8dBm at 120µs–NS, 315Hz 2.1 3.6 5.1 Signal handling 120µs–NS, RL = 2.7kΩ f = 1kHz, THD + N = 1% –10.0 –6.0 — dBm Total harmonic distortion 120µs–NS, RL = 2.7kΩ f = 1kHz, Vin = –56.4dBm — 0.3 0.7 % S/N ratio 120µs–NS, Rg = 2.2kΩ "A" weighting filter 55.0 62.0 — dB Output offset voltage 120µs–NS, Rg = 70kΩ 2.4 2.7 3.2 V Playback equalizer amplifier block AMS AGC Operating voltage –8– dB CXA1898Q Recording equalizer amplifier block Item Measurement conditions Min. Typ. Max. –29.4 –27.9 –26.4 — –10.0 — Reference input level NORM–NS, 315Hz, input level at which reference output can be obtained Reference output level NORM–NS, 315Hz Channel balance NORM-NS, 315Hz, Output difference 1ch–2ch for –27.9dBm input –1.5 0.0 1.5 NORM–NS frequency response f = 3kHz at NORM–NS, 315Hz, reference output –20dB –1.3 –0.2 1.1 NORM–NS frequency response f = 8kHz at NORM–NS, 315Hz, reference output –20dB 3.7 5.7 7.3 NORM–NS frequency response f = 12kHz at NORM–NS, 315Hz, reference output –20dB 10.4 13.4 16.4 CrO2–NS frequency response f = 3kHz at NORM–NS, 315Hz, reference output –20dB 1.8 3.0 4.2 CrO2–NS frequency response f = 8kHz at NORM–NS, 315Hz, reference output –20dB 6.7 8.4 9.7 CrO2–NS frequency response f = 12kHz at NORM–NS, 315Hz, reference output –20dB 13.2 15.8 18.2 METAL–NS frequency response f = 3kHz at NORM–NS, 315Hz, reference output –20dB 3.3 4.5 5.7 METAL–NS frequency response f = 8kHz at NORM–NS, 315Hz, reference output –20dB 5.9 7.4 8.9 METAL–NS frequency response f = 12kHz at NORM–NS, 315Hz, reference output –20dB 11.3 13.7 15.8 NORM–HS frequency response f = 5kHz at NORM–NS, 315Hz, reference output -20dB –0.7 0.2 1.7 NORM–HS frequency response f = 15kHz at NORM–NS, 315Hz, reference output –20dB 8.3 10.5 12.3 NORM–HS frequency response f = 20kHz at NORM–NS, 315Hz, reference output –20dB 13.5 16.7 19.5 CrO2–HS frequency response f = 5kHz at NORM–NS, 315Hz, reference output –20dB 3.6 4.9 6.0 CrO2–HS frequency response f = 15kHz at NORM–NS, 315Hz, reference output –20dB 12.0 14.2 16.0 CrO2–HS frequency response f = 20kHz at NORM–NS, 315Hz, reference output –20dB 17.0 20.0 22.5 METAL–HS frequency response f = 5kHz at NORM–NS, 315Hz, reference output –20dB 4.9 6.1 7.3 METAL–HS frequency response f = 15kHz at NORM–NS, 315Hz, reference output –20dB 10.5 12.4 14.0 METAL–HS frequency response f = 20kHz at NORM–NS, 315Hz, reference output –20dB 14.7 17.4 19.7 –9– Unit dBm dB CXA1898Q Item Measurement conditions Min. Typ. Max. Unit NORM–NS, RL2.7kΩ f = 1kHz, THD = 1% 8.0 8.8 — dB Total harmonic distortion NORM–NS, RL2.7kΩ f = 1kHz, 0dB — 0.2 0.5 % S/N ratio NORM–NS, Rg = 5.1kΩ "A" weighting filter 57.0 60.6 — dB Output offset voltage NORM–NS 3.6 4.0 4.4 V Mute characteristics 1 NORM–NS, f = 1kHz 8dB, Pin 12 = 3.5V — –100 –80 Mute characteristics 2 NORM–NS, f = 1kHz 8dB, Pin 12 = 2.0V –8.3 –7.0 –4.3 Control voltage low level 1 A-EQ (Pin 10) 0.0 — 0.5 Control voltage high level 1 A-EQ (Pin 10) 2.5 — VCC Control voltage low level 2 B-EQ (Pin 11) 0.0 — 0.5 Control voltage medium level 1 B-EQ (Pin 11) 2.2 — 2.8 Control voltage high level 2 B-EQ (Pin 11) 4.2 — VCC Control voltage low level 3 RMUTE1-I (Pin 12) 0.0 — 0.5 Control voltage high level 3 RMUTE1-I (Pin 12) 3.5 — VCC Recording equalizer amplifier block Signal handling Note) NORM–NS : NORMAL TAPE–NORMAL SPEED NORM–HS : NORMAL TAPE–HIGH SPEED CrO2–NS : CrO2 TAPE–NORMAL SPEED CrO2–HS : CrO2 TAPE–HIGH SPEED METAL–NS : METAL TAPE–NORMAL SPEED METAL–HS : METAL TAPE–HIGH SPEED 120µs–NS : EQ = 120µs–NORMAL SPEED 120µs–HS : EQ = 120µs–HIGH SPEED 70µs–NS : EQ = 70µs–NORMAL SPEED 70µs–HS : EQ = 70µs–HIGH SPEED – 10 – dB V CXA1898Q 11-bit serial data interface block Item Measurement conditions Min. Typ. Max. Low level input voltage VIL (LATCH/CLK/DATA/XRESET) (Pins 23, 24, 25, 26) 0.0 — 1.5 High level input voltage VIH (LATCH/CLK/DATA/XRESET) (Pins 23, 24, 25, 26) 3.5 — VDD Low level output voltage VOL, IOL = 2mA (max) (Pins 13, 14, 15, 16, 17, 18, 19, 20, 21, 22) 0.0 — 0.5 High level output offleak current IOZ Leak current which flows to the output pin when Ioz output is open; applied voltage is 10V. — — 1.0 µA 500 — — kHz Maximum clock frequency (1) fCK Minimum clock pulse width (2) tWC — — 1.0 Minimum reset pulse width (3) tWR — — 1.0 Minimum data setup time (4) tSDK (DATA → CLK) — — 1.0 Minimum data hold time (5) tHCD (CLK → DATA) — — 1.0 Minimum data pulse width (6) tWD — — 2.0 Minimum latch setup time (7) tSLD (LATCH → DATA) — — 1.0 Minimum latch hold time (8) tHCL (CLK → LATCH) — — 1.0 Minimum clock hold time (9) tHLC (LATCH → CLK) — — 1.0 Unit V µs Note) • VDD is CPU supply voltage 5.0V. • The maximum value for VDD is Pin 35 (VCC) voltage. • For high level output off leak current, VCC is 10.0V. – 11 – CXA1898Q Timing Chart for 11-bit Serial Data Interface tWC 3.5V CLK 1.5V tSDK tHCD tWD 3.5V DATA D1 D2 1.5V tSLD LATCH 1.5V 3.5V CLK tHLC tHCL DATA D10 D11 3.5V LATCH 1.5V XRESET 1.5V tWR – 12 – tWC AC OUTPUT S505 S504 S503 S502 S501 GND S1B "A" Weighting Filter 30dB AMP BUF –6dB ATT –9dB S3B 1kHz Band Pass Filter (20dB) Audio (22.2Hz-22.2kHz) Filter S1A ATT TL072 100k GND 377k 377k 377k 377k 47µ 47µ 0.015µ S12B 2.7k 0.1µ S7D S7C 0.1µ S7B 0.1µ S7A 0.1µ S12A 2.7k 2.2µ 100 9.1k 2.2µ 100 S11 2.2k S10 2.2k S9 2.2k S8 2.2k 0.47µ 0.47µ 0.47µ 0.47µ 48 PB OUT1 47 AMS GAIN PB FB21 PB FB11 45 46 PB INB1 44 43 PB INA1 42 PB INA2 41 PB INB2 40 PB FB12 CXA1898Q 1 2 4 3 5 6 7 8 9 10 11 0.5V 12 R MUTE1 13 R MUTE2 14 SPEED 15 PB MUTE 16 BPA 17 BPB 18 PL1 19 PL2 20 M1 21 M2 22 39 PB FB22 CLK 24 LATCH 23 IREF 38 PB OUT2 37 25 26 27 28 29 30 31 32 33 34 35 27k 36 100 S3A S13A 100 12k S13B 10k S14A –17dB 0.1µ 10k S6B 100k ATT AMS FIL –29dB AMS OUT S6A 1k 10µ 0.1µ 0.1µ 100k S14B AMS GND 600 S15 10k 10µ FP CAL S4B 0.47µ RFC GP CAL ATT S17A AGC IN1 S18A REC IN1 47k –40dB 10µ 10k S16 S7F 0.47µ 5.1k S20 0.1µ 10k 390k 2.7k S12D 0.018µ 0.018µ 47k VCC 10k S4A 300k 27k 0.1µ VG 100 S18B 70µs S2B S21A GND AGC OUT1 AGC TC A EQ A EQ 10k S23 120µs ATT 47µ 0.47µ S17B 100 4.7µ AGC IN2 B EQ 0.1µ B EQ 10k S39 S27 0.1µ 10k S28A 2k 2k 2k 2k 2k 2k 2k 2k 2k 2k 4.2V 2.0V 2.5V 3.5V 5.0V OFF S24 S25 S26 NORM CrO2 METAL S2A 10k REC IN2 5.1k S19 390k S7E 10k 4.7µ S21B 2.7k S12C AGC OUT2 100 S22A 0.1µ AC INPUT 2.2µ 5.1k 0.47µ 5.1k 100 2.2µ REC OUT2 REC OUT1 D GND XRESET XRESET DATA REC MUTE 8.0V RMUTE1 I DATA S22B S28B – 13 – ON Electrical Characteristics Measurement Circuit GND 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 DC OUTPUT LATCH CLK CXA1898Q CXA1898Q Application Circuit GND GND GND GND 0.1µ REC IN2 AGC IN2 GND AGC TC 31 32 33 30 37 38 2.2µ PB FB22 820p 39 10k 0.018µ GND 47µ 100 12mH 150p 180p PB FB12 40 28 29 25 24 CLK 47k 23 22 D1 LATCH 47k VDD or VCC 47k VDD or VCC 47k VDD or VCC 47k VDD or VCC 47k VDD or VCC 47k VDD or VCC 47k VDD or VCC 47k VDD or VCC 47k VDD or VCC M2 40k 210k GND 210k 26 27 GND AGC GAIN 19.5dB 10k IREF PB OUT2 2.2µ GND GND GND 100k RECEQ IREF 34 4.7µ 10k 12k GND VG VCC RFC 35 36 47µ 2.2µ 10k D GND 100µ 1k 2.7k 0.47µ 2.2meg REC OUT2 47µ AGC OUT2 10µ VDD GND DATA GND XRESET VCC GND D2 GND 21 M1 GND PB GND B EQ A EQ 42 PB INA1 GND 70k GND 70k D3 AGC OFF D8 PB GND PB INB1 44 GND GND 45 46 PB OUT1 AMS GAIN AMS 48 1k D11 D11 GND GND GND GND GND GND GND 1 AMS OUT AMS FIL 2 100k 20 19 18 17 16 15 14 13 PL2 PL1 BPB BPA PB MUTE SPEED R MUTE2 R MUTE1 47k 47k GND 100k 5 4 3 6 27k 27k 8 7 REC IN1 0.1µ AGC IN1 GND D8 D10 D9 10k 47 GND 4.7µ 0.47µ 0.1µ VDD or VCC GND GND GND GND 10k 2.7k 0.1µ 9 10 12 11 0.1µ GND RMUTE1 I GND A EQ 2.2µ AGC OUT1 10k D9 RECEQ GND MUTE 10k 40k 210k AGC GAIN 19.5dB 0.018µ PB FB21 D7 SPEED B EQ 210k 12mH GP CAL 150p 820p PB FB11 FP CAL 180p 47µ 100 D6 REC OUT1 GND GND 70k D4 D5 RECEQ CTL GND AMS GND REC 43 B EQ BIas OSC DECK-A PB-HEAD PB INA2 R/P-HEAD DECK-B 70k AGC REC GND LATCHES 41 SHIFT REGISTERS GND PB INB2 PBEQ CTL GND DECK A/B D10 SPEED D9 2.2µ 10k GND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 14 – VDD or VCC VDD or VCC CXA1898Q 1. System control mode Playback and recording equalizer (1) Playback equalizer (120µs/70µs) A-EQ (Pin 10) L DECK-AB (serial data D10 (Pin 25)) L H 120µs (A DECK) B-EQ (Pin 11) H L 70µs (A DECK) M/H According to A EQ control 120µs (B DECK) According to B EQ control 70µs (B DECK) (2) Recording equalizer (Normal, CrO2, Metal) B-EQ (Pin 11) L M H REC MODE Normal (Type I) CrO2 (Type II) Metal (Type IV) (3) Recording mute (Pin 12) Rec Mute Mute OFF –7dB attenuation Mute ON Control voltage GND ≤ VCL ≤ 0.5V 2.0V 3.5V ≤ VCH ≤ VCC Muting is achieved by varying the recording equalizer amplifier gain just like an electronic volume, according to the DC voltage applied to the REC MUTE pin. (4) FP CAL (Pin 4) The standard resistor setting is 27kΩ, but when resistance value is larger, fo (Hz) is low, and when resistance value is smaller, fo (Hz) is high. (5) Gp Cal (Pin 5) The standard resistor setting is 27kΩ, but when resistance value is larger, gain is larger, and when resistance value is smaller, gain is smaller. – 15 – CXA1898Q 2. 11-bit serial data interface CLk (Pin 24) DATA (Pin 25) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 LATCH (Pin 23) XRESET (Pin 26) • The DATA signal is taken in at the rising edge of the CLK signal. • The DATA signal is taken in to the internal shift register when the LATCH signal is low. (Outputs (Pins 13 to 22) hold the previous value while the LATCH signal is low.) • The internal shift register data is latched and output in parallel at the rising edge of the LATCH signal. (Internal shift register data is loaded while the LATCH signal is high.) • The CLK signal of 11th bit should fall after the LATCH signal rises. • Reset is done when the XRESET pin is low. (asynchronous method) Outputs (Pins 13 to 22) are all high (open) during reset. Output DATA (Pin 25) Control signal Output pin Input set at low Input set at high D1 M2 Pin 22 L H (OPEN) D2 M1 Pin 21 L H (OPEN) D3 PL2 Pin 20 L H (OPEN) D4 PL1 Pin 19 L H (OPEN) D5 BPB Pin 18 L H (OPEN) D6 BPA Pin 17 L H (OPEN) D7 PB-MUTE Pin 16 L H (OPEN) D8 AGC-OFF — AGC function stops AGC function operates D9 SPEED Pin 15 Low, normal speed High (open) 1.7 D10 DECK-AB — A DECK selected B DECK selected D11 REC-MUTE Pin 14/Pin 13 Low mute OFF High (open) mute ON – 16 – CXA1898Q • Make sure that RFC is 5.5V or more and XRESET is 1.5V or less, and 1µs or more when resetting by applying CR time constant to XRESET (Pin 26) and turning power ON. 5.5V or more RFC (Pin 36) 1.5V or less XRESET (Pin 26) 1µs or more • When resetting with CPU or other when power is turned ON 5.5V or more RFC (Pin 36) 5.0V XRESET (Pin 26) 0V 1µs or more • Examples of AGC control during timer recording (1) Resets when power is turned ON (AGC function operates). (2) AGC is turned OFF after AGC inputs (Pins 6 and 31) rise. (External capacitor charge of AGC TC is discharged.) (3) AGC is turned ON and timer recording begins. – 17 – CXA1898Q Circuit Diagram for 11-bit Serial Data Transfer Evaluation Tool CLK1 XPR1 15 100 R16 B3 A3 Y3 B1 Y1 A2 B2 Y2 VSS B4 A4 R10 R11 10k R12 10k 9 100 VDD B4 A4 Y4 B3 A3 Y3 B4 A4 Y4 B3 A3 Y3 C19 0.1µ VDD A4 Y4 C12 0.1µ Y5 Y6 A5 A6 Y1 A2 B2 Y2 VSS B2 B1 A2 A1 Y1 Y2 B1 VSS A1 C9 0.1µ R18 100 R15 220 R14 220 Y2 A3 Y3 VSS C8 0.1µ A2 R9 220 Y1 R4 220 A1 A1 B1 A0 B0 A>BIN A>BOUT A=BOUT A<BOUT VSS A2 A=BIN B2 B3 A3 A<BIN VDD XQ2 XRES2 B2 XA2 C18 0.1µ Q1 C2 R/C2 Q2 VSS XA1 B1 XRES1 Q2 Q3 XQ1 Q4 C1 Q1 Q7 R/C1 CLOCK Q5 Q9 Q10 Q8 C11 0.1µ VDD RESET Q6 Q11 R8 220 R7 220 500kHz 16 250kHz D5 D6 R19 15 100 VSS H SERIAL XQH IN QH G A F D B E CLK2 C S/XL CLK1 VDD C17 0.1µ VSS H SERIAL XQH IN QH G A F B E C D Q10 CLOCK DA D3 D2 D1 D11 D10 D9 D8 L D7 D4 D14 D13 D15 L H L D12 S/XL CLK2 CLK1 VDD VSS C10 0.1µ XLOAD DD ENA 1 ENA P RESET DB Q9 DC Q8 Q11 C 0.1µ VDD XRESET LH 1 2 4 8 8 VSS 7 Q12 L H H Y4 A1 VDD XQ2 C20 0.1µ Q2 D1 VSS XPR2 XR1 XQ1 CLK2 VSS Q1 D2 XQ1 CLK1 XR2 XQ2 Q1 XPR1 VDD Q2 XPR1 1 14 8 16 C15 1000P 11 CLK 100µ/25V LATCH D1 XPR2 CLK1 VDD 6 DATA XR1 CLK2 C13 0.1µ D2 D1 5 XRESET VSS XR2 4 C2 0.1µ 7 3 VDD 6 8 5V XQ2 XQ1 VSS XPR2 Q2 START XQ1 ON XQ2 CLK2 XPR2 XPR1 Q1 Q2 D2 CLK2 CLK1 OFF Q1 XR2 D2 D1 XR1 7 VDD 5 7 VDD XR2 XR1 8 4 6 3 9 C3 0.1µ 7 3 5 2 6 8 C4 0.1µ 6 2 4 1 – 18 – 5 8 1 8 74HC165 (1) 74HC161 L H L 4 74HC165 (2) 9 9 LH 3 9 10 10 L H 2 10 11 14 11 14 H 1 11 14 12 15 13 16 12 15 12 15 LH L L L L H H H H L H H L H L H L 2 3 L H H 1 7 8 6 74HC85 2 R17 C16 4.7µ 9 1 5 10 8 4 11 7 10 8 12 6 11 9 13 5 12 10 14 4 13 11 15 9 14 12 16 10 3 13 16 13 16 19 C7 15P 7 11 2 7 6 12 1 6 5 74HC123 5 4 14 9 4 3 15 10 3 5 2 4 1 3 7 2 6 1 2 74HC08 (2) 74HC08 (1) 74HC04 5 9 8 8 13 8 4 2 3 1 2 7 1 6 7 5 6 4 5 3 4 2 3 1 10 9 9 12 17 74HC00 74HC74 (4) 74HC74 (3) 11 12 10 10 68k DGND 13 3 13 11 11 13 74HC4040 1 EXCLK EXCLK 4 14 12 12 C14 0.1µ VDD C5 0.1µ 8 13 13 8 9 14 14 9 10 2 1 4.4MHz R1 1M C6 15P R2 220 3 6 2 4 10 11 R13 2.2k 16 11 14 12 15 13 16 OFF ON R5 7 11 12 DGND SW GND RESET 10k 6 12 13 14 9 12 10 13 11 14 74HC74 (2) 74HC74 (1) 5 1 4 7 3 6 2 5 1 13 5 14 14 C21 R6 10k GND R3 10k – 19 – (19) LATCH (18) (17) = (8) (16) CLOCK (15) DATA HC165 (14) RESET/CLOCK STOP and COUNT RESET (13) (12) (11) HC123 (10) A = B, H (9) (8) CLK GATE CONT. (7) S/L (6) = (4) (5) (4) (3) START PULSE (2) CLK (1) CLK Dummy Timing Chart for 11-bit Serial Data Transfer Evaluation Tool D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 2µs COUNT RESET CLOCK STOP CXA1898Q CXA1898Q 3. AMS (1) AMS output logic Signal detection No signal detection Detection status AMS OUT (Pin 2) L H AMS OUT (Pin 2) is an open collector output pin. When a 2.2kΩ resistor is connected to VDD: Low : approximately 0.5V (IOL = 2mA (max.)) High : VDD Fig. 1 shows the AMS block diagram. PB OUT1 20k Inside IC SA HPF 20k LPF DET 25kHz AMS GAIN 48 100k 1 AMS OUT 2 AMS FIL 3 AMS GND R3 C2 C1 R2 R1 PB OUT2 VDD VDD GND VDD GND Fig. 1 AMS Block Diagram Fig. 2 shows the frequency response of the signal output from HPF. fC G GAIN (dB) 10 1kHz 25kHz f (Hz) Fig. 2 Frequency Response – 20 – 100kHz CXA1898Q (2) AMS level setting The AMS level is set by adjusting HPF gain and cut-off frequency with the external resistor and capacitor at Pin 48. G and fc in Fig. 2 are obtained from the following formula. G = 20log (1 + 100k/R) [dB] – (1) fc = 1/ (2 • π • C • R) [Hz] Full-wave rectifier is applied for the signal at DET. Signal detection time is set by the time constant of Pin 1 external resistor and capacitor. DET signal detection level: = –7.5dBm (typ.) = playback equalizer reference output level + AMS level + HPF gain – (2) Playback equalizer reference output level of –21dBm is 0dB. Ex.) To set AMS level at –25dB, determine and set the constant for Pin 48 external resistor. (Calculate assuming PBOUT1 = PBOUT2) First, get the required HPF gain from formula (2). –7.5dBm = –21dBm + (–25dB) + HPF gain, so HPF gain = 38.5dB. Next, get Pin 48 external resistance from formula (1). 38.5dB = 20log (1 + 100k/R), so R ≈ 1.2kΩ, and external resistance is 1.2kΩ. – 21 – CXA1898Q Example of Representative Characteristics Quiescent current consumption vs. Supply voltage ICC-Quiescent current consumption (mA) 25 24 23 22 21 20 19 18 17 16 15 6 7 8 9 10 11 VCC-Supply voltage (V) PB OUT PB FB1 PB IN Playback equalizer frequency response PB FB2 VCC = 8V GAIN (dB) 2.2k 55 50 45 40 120µs – NS 35 120µs – HS 70µs – NS 30 70µs – HS 25 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) – 22 – 50k 2.2µ 60 0.018µ 47µ 0.47µ 100 65 M CXA1898Q Output response (dB) Recording equalizer frequency response 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 –2 VCC = 8V 0dB = NORM – NS, 315Hz, –30dBm (Tape) (Speed) NORM– NS CrO2– NS METAL– NS 20 50 100 200 500 1k 2k 5k 10k 20k 50k Frequency (Hz) Output response (dB) Recording equalizer frequency response 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 –2 VCC = 8V 0dB = NORM – NS, 315Hz, –30dBm (Tape) (Speed) NORM– HS CrO2– HS METAL– HS 20 50 100 200 500 1k 2k Frequency (Hz) – 23 – 5k 10k 20k 50k CXA1898Q Output level vs. Mute voltage 10 VCC = 8V (Tape) (Speed) NORM– NS 0dB = reference output level +8dB f = 1kHz 0 –10 –20 Output level (dB) –30 –40 –50 –60 –70 –80 –90 –100 0.0 1.0 2.0 3.0 4.0 5.0 6.0 RMUTE1 (Pin 1) voltage AMS no signal detection level frequency response AMS OUT 48 1 2 B 100k A 100k A : Pin 48 for R9.1k, C0.015µ B : Pin 48 for R1k, C0.1µ AMS FIL A : 0.015µ 9.1k B : 0.1µ 1k 0.1µ 30 25 20 15 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 AMS GAIN AMS input level (playback equalizer output level) (dB) VCC = 8V 120µs – NS AMS OUT 5V 0dB = –21dBm, 315Hz (playback equalizer reference output level) to5V 20 50 100 200 500 1k 2k 5k Frequency (Hz) – 24 – 10k 20k 50k CXA1898Q AGC Output response 10 AGC TC 5 Output level (dBm) VCC = 8V 1kHz AGC OFF 32 0 300k 47µ –5 –10 AGC ON –15 –35 –30 –25 –20 –15 –10 –5 Input level (dBm) Playback equalizer total harmonic distortion Recording equalizer total harmonic distortion VCC = 8V Norm – NS mode RL = 2.7kΩ 1kHz 0dB = –10dBm 2.0 T.H.D. + Noise (%) T.H.D. + Noise (%) 2.0 1.0 0.5 1.0 0.5 0.2 0.2 0.1 0.1 –15 –10 –5 0 VCC = 8V 120µs – NS mode RL = 2.7kΩ 1kHz 5 –30 10 –25 –20 –15 Output level (dB) Output level (dB) – 25 – –10 –5 CXA1898Q Package Outline Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 12.0 – 0.1 36 25 0.15 24 48 13 13.5 37 12 0.8 + 0.15 0.3 – 0.1 ± 0.12 M 0.9 ± 0.2 1 + 0.2 0.1 – 0.1 + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-48P-L04 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE ∗QFP048-P-1212-B LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 0.7g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 26 –