ICX418ALL Diagonal 8mm (Type 1/2) CCD Image Sensor for EIA B/W Video Cameras Description The ICX418ALL is an interline CCD solid-state image sensor suitable for EIA B/W video cameras with a diagonal 8mm (Type 1/2) system. Compared with the current product ICX038DLA, basic characteristics such as sensitivity, smear, dynamic range and S/N are improved drastically. This chip features a field period readout system and an electronic shutter with variable charge-storage time. This chip is compatible with the pins of the ICX038DLA and has the same drive conditions. 20 pin DIP (Cer-DIP) Pin 1 Features V • High sensitivity (+5.0dB compared with the ICX038DLA) • Low smear (–5.0dB compared with the ICX038DLA) • High D range (+2.0dB compared with the ICX038DLA) 3 • High S/N 40 H Pin 11 • High resolution and low dark current Optical black position • Excellent antiblooming characteristics (Top View) • Continuous variable-speed shutter • Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V) • Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V) • Horizontal register: 5V drive 2 12 Device Structure • Interline CCD image sensor • Optical size: Diagonal 8mm (Type 1/2) • Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels • Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels • Chip size: 7.40mm (H) × 5.95mm (V) • Unit cell size: 8.4µm (H) × 9.8µm (V) • Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 12 pixels, rear 2 pixels • Number of dummy bits: Horizontal 22 Vertical 1 (even fields only) • Substrate material: Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01504A29 ICX418ALL VDD GND VL Vφ1 GND φSUB Vφ2 Vφ3 Vφ4 10 9 8 7 6 5 4 3 2 1 Vertical Register VOUT Block Diagram and Pin Configuration (Top View) Note) Horizontal Register 14 15 16 17 18 19 20 GND RD φRG NC Hφ1 Hφ2 VDSUB 13 GND 12 NC 11 NC Note) : Photo sensor Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 Vφ4 Vertical register transfer clock 11 NC 2 Vφ3 Vertical register transfer clock 12 VDSUB 3 Vφ2 Vertical register transfer clock 13 NC 4 φSUB Substrate clock 14 GND GND 5 GND GND 15 GND GND 6 Vφ1 Vertical register transfer clock 16 RD Reset drain bias 7 VL Protective transistor bias 17 φRG Reset gate clock 8 GND GND 18 NC 9 VDD Output circuit supply voltage 19 Hφ1 Horizontal register transfer clock 10 VOUT Signal output 20 Hφ2 Horizontal register transfer clock –2– Substrate bias circuit supply voltage ICX418ALL Absolute Maximum Ratings Item Ratings Unit –0.3 to +50 V VDD, VRD, VDSUB, VOUT – GND –0.3 to +18 V VDD, VRD, VDSUB, VOUT – φSUB –55 to +10 V Vφ1, Vφ2, Vφ3, Vφ4 – GND –15 to +20 V Vφ1, Vφ2, Vφ3, Vφ4 – φSUB to +10 V Voltage difference between vertical clock input pins to +15 V Voltage difference between horizontal clock input pins to +17 V Hφ1, Hφ2 – Vφ4 –17 to +17 V φRG – GND –10 to +15 V φRG – φSUB –55 to +10 V VL – φSUB –65 to +0.3 V Pins other than GND and φSUB – VL –0.3 to +30 V Storage temperature –30 to +80 °C Operating temperature –10 to +60 °C Substrate clock φSUB – GND Supply voltage Clock input voltage ∗1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%. –3– Remarks ∗1 ICX418ALL Bias Conditions 1 [when used in substrate bias internal generation mode] Item Symbol Min. Typ. Max. Unit Output circuit supply voltage VDD 14.55 15.0 15.45 V Reset drain voltage VRD 14.55 15.0 15.45 V Protective transistor bias VL Substrate bias circuit supply voltage VDSUB 15.45 V Substrate clock φSUB Remarks VRD = VDD ∗1 14.55 15.0 ∗2 ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL power supply for the V driver should be used. (When CXD1267AN is used.) ∗2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. Bias Conditions 2 [when used in substrate bias external adjustment mode] Item Symbol Min. Typ. Max. Unit Remarks Output circuit supply voltage VDD 14.55 15.0 15.45 V Reset drain voltage VRD 14.55 15.0 15.45 V VRD = VDD Protective transistor bias VL ∗3 Substrate bias circuit supply voltage VDSUB ∗4 Substrate voltage adjustment range VSUB 6.0 14.0 V ∗5 Substrate voltage adjustment precision ∆VSUB –3 +3 % ∗5 ∗3 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL power supply for the V driver should be used. (When CXD1267AN is used.) ∗4 Connect to GND or leave open. ∗5 The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a special code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated voltage. The adjustment precision is ±3%. However, this setting value has not significance when used in substrate bias internal generation mode. VSUB code — one character indication Code and optimal setting correspond to each other as follows. VSUB code E Optimal setting 6.0 f G h J K L m 6.5 7.0 7.5 8.0 8.5 9.0 N P Q R S T DC Characteristics Output circuit supply current Symbol V W 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 <Example> "L" → VSUB = 9.0V Item U Min. IDD –4– Typ. Max. Unit 5.0 10.0 mA Remarks ICX418ALL Clock Voltage Conditions Item Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Symbol Min. Waveform diagram Remarks VVT 14.55 15.0 15.45 V 1 VVH1, VVH2 –0.05 0 0.05 V 2 VVH3, VVH4 –0.2 0 0.05 V 2 VVL1, VVL2, VVL3, VVL4 –9.6 –9.0 –8.5 V 2 VVL = (VVL3 + VVL4)/2 VφV 8.3 2 VφV = VVHn – VVLn (n = 1 to 4) 9.0 | VVH1 – VVH2 | 9.65 Vp-p 0.1 V 2 VVH = (VVH1 + VVH2)/2 VVH3 – VVH –0.25 0.1 V 2 VVH4 – VVH –0.25 0.1 V 2 VVHH 0.5 V 2 High-level coupling VVHL 0.5 V 2 High-level coupling VVLH 0.5 V 2 Low-level coupling VVLL 0.5 V 2 Low-level coupling VφH 4.75 5.0 VHL –0.05 0 VφRG 0.05 4.5 5.0 VRGLH – VRGLL Substrate clock voltage VφSUB 5.25 Vp-p ∗1 VRGL Reset gate clock voltage∗1 Typ. Max. Unit 3 V 3 V 4 5.5 Vp-p 4 0.8 4 V 23.0 24.0 25.0 Vp-p Low-level coupling 5 ∗1 Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven with the following specifications. Item Reset gate clock voltage Symbol Min. Typ. Max. Unit VRGL –0.2 0 VφRG 8.5 9.0 0.2 V 9.5 Vp-p –5– Waveform diagram 4 4 Remarks ICX418ALL Clock Equivalent Circuit Constant Symbol Item Typ. Min. Max. Unit CφV1, CφV3 2700 pF CφV2, CφV4 2700 pF CφV12, CφV34 820 pF CφV23, CφV41 330 pF Capacitance between horizontal transfer clock CφH1 and GND CφH2 100 pF 91 pF Capacitance between horizontal transfer clocks CφHH 47 pF Capacitance between reset gate clock and GND CφRG 11 pF Capacitance between substrate clock and GND CφSUB 680 pF R1, R3 91 Ω R2, R4 100 Ω RGND 68 Ω Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vertical transfer clock series resistor Vertical transfer clock ground resistor Vφ2 Vφ1 CφV12 R1 R2 Hφ1 CφV1 CφV23 CφV4 Vφ4 Hφ2 CφHH CφV2 CφV41 R4 Remarks RGND CφV34 CφH1 CφH2 CφV3 R3 Vφ3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit –6– ICX418ALL Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% VVT φM φM 2 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform Vφ1 Vφ3 VVH1 VVHH VVH VVHH VVHL VVHL VVHL VVL1 VVHH VVHH VVH3 VVH VVHL VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVHL VVH2 VVHL VVH4 VVLH VVL2VVLH VVLL VVLL VVL4 VVL VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4) VVHL –7– VVL ICX418ALL (3) Horizontal transfer clock waveform tr twh tf 90% VφH twl 10% VHL tr (4) Reset gate clock waveform twh tf VRGH twl VφRG Point A RG waveform VRGL + 0.5V VRGLH VRGL VRGLL VRGLm Hφ1 waveform +2.5V VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the period twh, then: VφRG = VRGH – VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% φM VφSUB φM 2 10% VSUB 0% tr twh –8– tf ICX418ALL Clock Switching Characteristics Item Symbol VT Vertical transfer clock Vφ1, Vφ2, Vφ3, Vφ4 Horizontal transfer clock Readout clock During imaging twh φSUB tf 0.5 2.3 2.5 20 20 15 5.38 19 Unit Remarks µs During readout 0.5 250 ns ∗1 15 During Hφ1 parallel-serial Hφ2 conversion Substrate clock tr Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Hφ Reset gate clock φRG twl 15 0.01 0.01 5.38 0.01 0.01 51 3 3 19 ns ∗2 µs 11 13 1.5 1.8 0.5 ns 0.5 µs ∗1 When vertical transfer clock driver CXD1267AN is used. ∗2 tf ≥ tr – 2ns. Item Symbol Horizontal transfer clock Hφ1, Hφ2 two Min. Typ. 16 20 Max. Unit Remarks ns ∗3 ∗3 The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two. –9– During drain charge ICX418ALL Image Sensor Characteristics (Ta = 25°C) Unit Measurement method mV 1 mV 2 –105 dB 3 20 % 4 Zone 0 and I 25 % 4 Zone 0 to II' Vdt 2 mV 5 Ta = 60°C Dark signal shading ∆Vdt 1 mV 6 Ta = 60°C Flicker F 2 % 7 Lag Lag 0.5 % 8 Item Symbol Min. Typ. Sensitivity S 880 1100 Saturation signal Ysat 1000 Smear Sm Video signal shading SH Dark signal –115 Max. Zone Definition of Video Signal Shading 768 (H) 14 14 12 H 8 V 10 H 8 Zone 0, I 494 (V) 10 Zone II, II' V 10 Ignored region Effective pixel region – 10 – Remarks Ta = 60°C ICX418ALL Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the value indicated on the device.) 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output or chroma signal output of the measurement system. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs × 250 60 [mV] 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with average value of the signal output, 200mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value VSm [mV] of the signal output and substitute the value into the following formula. Sm = 20 × log VSm × 1 × 500 200 1 10 [dB] (1/10V method conversion value) 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax – Vmin)/200 × 100 [%] – 11 – ICX418ALL 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 200mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then substitute the value into the following formula. Fy = (∆Vf/200) × 100 [%] 10. Lag Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/200) × 100 [%] FLD V1 Light Strobe light timing signal output 200mV Ylag (lag) Output – 12 – 13 12 11 7 8 9 10 XSG1 XV3 XSG2 XV4 RG Hφ2 Hφ1 14 6 XV1 22/20V 16 5 XV2 15 17 4 XSUB CXD1267AN 18 22/16V 1/35V 0.01 ICX418 (BOTTOM VIEW) 8 7 6 5 4 2 3 1 Vφ4 Hφ2 3 100k Vφ3 Hφ1 19 Vφ2 NC 9 10 3.9k 100 0.01 20 19 18 17 16 15 14 13 12 11 φRG 20 φSUB RD 2 Vφ1 GND GND 1 VL GND VOUT 15V GND NC VDD VDSUB – 13 – NC Drive Circuit 1 (substrate bias internal generation mode) 3.3/20V 1 0.01 [∗A] CCD OUT 1M 3.3/16V –9V ICX418ALL 14 13 12 11 6 7 8 9 10 XV1 XSG1 XV3 XSG2 XV4 RG Hφ2 Hφ1 16 5 XV2 22/20V 17 4 XSUB 15 18 3 CXD1267AN 19 22/16V 1/35V 1/35V 0.01 1/35V ICX418 (BOTTOM VIEW) 8 7 6 5 4 2 0.1 3 1 100k 27k 56k Vφ4 Hφ2 20 Vφ3 Hφ1 9 10 39k 3.9k 100 0.01 20 19 18 17 16 15 14 13 12 11 φRG 2 Vφ2 NC RD 1 φSUB 270k GND GND VDD 0.1 VL Vφ1 NC 15V GND GND VOUT NC – 14 – VDSUB Drive Circuit 2 (substrate bias external adjustment mode) 3.3/20V 0.1 15k 47k 15k 0.01 [∗A] CCD OUT 1M 3.3/16V –9V ICX418ALL ICX418ALL Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics) 1.0 0.9 0.8 Relative Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 Wave Length [nm] 800 900 1000 Sensor Readout Clock Timing Chart V1 2.5 V2 Odd Field V3 V4 33.5 1.6 2.5 2.5 2.5 0.2 V1 V2 Even Field V3 V4 Unit: µs – 15 – – 16 – CCD OUT V4 V3 V2 V1 HD BLK VD FLD 493 494 525 1 2 3 4 5 520 Drive Timing Chart (Vertical Sync) 10 2 4 6 1 3 5 15 2 4 6 1 3 5 494 493 1 3 5 2 4 6 1 3 5 2 4 6 ICX418ALL 280 275 270 265 260 20 – 17 – SUB V4 V3 V2 V1 RG H2 H1 BLK HD 20 10 768 1 2 3 5 760 Drive Timing Chart (Horizontal Sync) ICX418ALL 20 10 20 22 1 2 3 1 2 3 10 1 2 3 5 40 30 ICX418ALL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) Upper ceramic Lower ceramic 39N 29N 29N 0.9Nm Low melting point glass Compressive strength Shearing strength Tensile strength Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. – 18 – ICX418ALL c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not to perform the following actions as this may cause cracks. • Applying repeated bending stress to the outer leads. • Heating the outer leads for an extended period with a soldering iron. • Rapidly cooling or heating the package. • Applying any load or impact to a limited portion of the low melting point glass using tweezers or other sharp tools. • Prying at the upper or lower ceramic using the low melting point glass as a fulcrum. Note that the same cautions also apply when removing soldered products from boards. e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. – 19 – – 20 – 3 0.55 ~ ~ 3 42 ALLOY 2.6g AS-B14-01(E) LEAD MATERIAL PACKAGE MASS DRAWING NUMBER TIN PLATING LEAD TREATMENT 11.55 Cer-DIP 0.51 PACKAGE MATERIAL PACKAGE STRUCTURE B 0.7 7.55 0.4 0.4 1 20 V 9.0 0.3 M 1.778 14.6 18.0 ± 0.4 H A ~ 3 10 11 B' 0.8 0.46 C 1.4 10 11 (0.7R) (1.0) φ1.4 1 20 (1.7) 9. The notch and the hole on the bottom must not be used for reference of fixing. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 7. The tilt of the effective image area relative to the bottom “C” is less than 60µm. 6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm. 5. The rotation angle of the effective image area relative to H and V is ± 1˚. 4. The center of the effective image area, relative to “B” and “B'” is (H, V) = (9.0, 7.55) ± 0.15mm. 3. The bottom “C” of the package is the height reference. 2. The two points “B” of the package are the horizontal reference. The point “B'” of the package is the vertical reference. 1. “A” is the center of the effective image area. 20pin DIP (600mil) 0˚ to 9˚ 0.25 1.27 Unit: mm 15.1 ± 0.3 0.70 15.24 3.26 ± 0.3 4.0 ± 0.3 (4.0) Package Outline ICX418ALL Sony Corporation