SN74AUP1G17 www.ti.com SCES579I – JUNE 2004 – REVISED MARCH 2010 LOW-POWER SINGLE SCHMITT-TRIGGER BUFFER Check for Samples: SN74AUP1G17 FEATURES 1 • • • • • • • Available in the Texas Instruments NanoStar™ Package Low Static-Power Consumption (ICC = 0.9 mA Max) Low Dynamic-Power Consumption (Cpd = 4.4 pF Typ at 3.3 V) Low Input Capacitance (Ci = 1.5 pF Typ) Low Noise – Overshoot and Undershoot <10% of VCC Ioff Supports Partial-Power-Down Mode Operation Includes Schmitt-Trigger Inputs A 2 GND 3 1 6 2 5 N.C. GND 3 4 Y 1 A 2 GND 3 DSF PACKAGE (TOP VIEW) N.C. VCC A N.C. DRL PACKAGE (TOP VIEW) VCC 5 N.C. 1 A 2 GND 3 5 VCC 4 Y Y 4 Y 4 DRY PACKAGE (TOP VIEW) N.C. • VCC 5 1 • • • Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation tpd = 5.1 ns Max at 3.3 V Suitable for Point-to-Point Applications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) DCK PACKAGE (TOP VIEW) DBV PACKAGE (TOP VIEW) N.C. • • • 1 6 VCC A 2 5 N.C. GND 3 4 Y YFP PACKAGE (TOP VIEW) A GND A1 1 4 A2 B1 2 3 B2 VCC Y YZP PACKAGE (TOP VIEW) DNU A GND A1 1 B1 2 C1 3 5 A2 VCC 4 C2 Y N.C. – No internal connection. DNU – Do not use See mechancial drawings for dimensions. DESCRIPTION/ORDERING INFORMATION The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity (see Figure 1 and Figure 2). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2010, Texas Instruments Incorporated SN74AUP1G17 SCES579I – JUNE 2004 – REVISED MARCH 2010 www.ti.com Static-Power Consumption Dynamic-Power Consumption (µA) (pF) 100% 80% 80% 60% 60% 3.3-V Logic† 40% 40% at 25 MHz† 3.5 3 2.5 Voltage − V 100% Switching Characteristics 3.3-V LVC Logic† AUP 0% † 0% Output 0.5 20% 20% Input 2 1.5 1 0 −0.5 AUP Single, dual, and triple gates Figure 1. AUP – The Lowest-Power Family 20 25 30 Time − ns † AUP1G08 data at C = 15 pF L 0 5 10 15 35 40 45 Figure 2. Excellent Signal Integrity This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION (1) –40°C to 85°C ORDERABLE PART NUMBER PACKAGE (2) TA NanoStar – WCSP (DSBGA) 0.23-mm Large Bump – YFP (Pb-free) Reel of 3000 SN74AUP1G17YFPR _ _ _H7_ NanoStar – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) Reel of 3000 SN74AUP1G17YZPR _ _ _H7_ QFN – DRY Reel of 5000 SN74AUP1G17DRYR H7 uQFN – DSF Reel of 5000 SN74AUP1G17DSFR H7 Reel of 3000 SN74AUP1G17DBVR Reel of 250 SN74AUP1G17DBVT Reel of 3000 SN74AUP1G17DCKR Reel of 250 SN74AUP1G17DCKT Reel of 4000 SN74AUP1G17DRLR SOT (SOT-23) – DBV SOT (SC-70) – DCK SOT (SOT-553) – DRL (1) (2) (3) TOP-SIDE MARKING (3) H17_ H7_ H7_ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE 2 INPUT A OUTPUT Y H H L L Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G17 SN74AUP1G17 www.ti.com SCES579I – JUNE 2004 – REVISED MARCH 2010 LOGIC DIAGRAM (POSITIVE LOGIC) (DBV, DCK, DRL, DRT, DRY, and YZP Packages) 2 4 A Y LOGIC DIAGRAM (POSITIVE LOGIC) (YFP Package) 1 3 A Y Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G17 3 SN74AUP1G17 SCES579I – JUNE 2004 – REVISED MARCH 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 4.6 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 4.6 V –0.5 VCC + 0.5 (2) UNIT VO Output voltage range in the high or low state IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA Continuous current through VCC or GND ±50 mA Package thermal impedance (3) qJA DBV package 206 DCK package 252 DRL package 142 DSF package 300 DRY package 234 YFP/YZP package Tstg Storage temperature range (1) V °C/W 132 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. (2) (3) RECOMMENDED OPERATING CONDITIONS (1) MIN MAX UNIT VCC Supply voltage 0.8 3.6 V VI Input voltage 0 3.6 V VO Output voltage 0 VCC V VCC = 0.8 V –20 mA VCC = 1.1 V –1.1 VCC = 1.4 V –1.7 VCC = 1.65 –1.9 VCC = 2.3 V –3.1 IOH IOL (2) (2) High-level output current Low-level output current VCC = 3 V –4 VCC = 0.8 V 20 VCC = 1.1 V 1.1 VCC = 1.4 V 1.7 VCC = 1.65 V 1.9 VCC = 2.3 V 3.1 VCC = 3 V TA (1) (2) 4 Operating free-air temperature mA mA mA 4 –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Defined by the signal-integrity requirements and design-goal priorities Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G17 SN74AUP1G17 www.ti.com SCES579I – JUNE 2004 – REVISED MARCH 2010 ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going input threshold voltage VT– Negative-going input threshold voltage ΔVT Hysteresis (VT+ – VT–) VOH TYP TA = –40°C to 85°C MAX MIN MAX 0.8 V 0.3 0.6 0.3 0.6 1.1 V 0.53 0.9 0.53 0.9 1.4 V 0.74 1.11 0.74 1.11 1.65 V 0.91 1.29 0.91 1.29 2.3 V 1.37 1.77 1.37 1.77 2.29 3V 1.88 2.29 1.88 0.8 V 0.1 0.6 0.1 0.6 1.1 V 0.26 0.65 0.26 0.65 1.4 V 0.39 0.75 0.39 0.75 1.65 V 0.47 0.84 0.47 0.84 2.3 V 0.69 1.04 0.69 1.04 3V 0.88 1.24 0.88 1.24 0.8 V 0.07 0.5 0.07 0.5 1.1 V 0.08 0.46 0.08 0.46 1.4 V 0.18 0.56 0.18 0.56 1.65 V 0.27 0.66 0.27 0.66 2.3 V 0.53 0.92 0.53 0.92 3V 0.79 1.31 0.79 1.31 0.8 V to 3.6 V VCC – 0.1 VCC – 0.1 IOH = –1.1 mA 1.1 V 0.75 × VCC 0.7 × VCC IOH = –1.7 mA 1.4 V 1.11 1.03 IOH = –1.9 mA 1.65 V 1.32 1.3 2.05 1.97 1.9 1.85 2.72 2.67 IOH = –2.3 mA IOH = –2.7 mA IOH = –4 mA IOL = 20 mA 2.3 V 3V 2.6 0.1 1.1 V 0.3 × VCC IOL = 1.7 mA 1.4 V 0.31 0.37 IOL = 1.9 mA 1.65 V 0.31 0.35 0.31 0.33 0.44 0.45 0.31 0.33 0.44 0.45 IOL = 3.1 mA IOL = 2.7 mA IOL = 4 mA A inputs VI = GND to 3.6 V V V V 2.55 0.3 × VCC IOL = 2.3 mA UNIT V 0.1 IOL = 1.1 mA II TA = 25°C MIN IOH = –20 mA IOH = –3.1 mA VOL VCC 0.8 V to 3.6 V 2.3 V 3V V 0 V to 3.6 V 0.1 0.5 mA Ioff VI or VO = 0 V to 3.6 V 0V 0.2 0.6 mA ΔIoff VI or VO = 0 V to 3.6 V 0 V to 0.2 V 0.2 0.6 mA ICC VI = GND or (VCC to 3.6 V), IO = 0 0.8 V to 3.6 V 0.5 0.9 mA ΔICC VI = VCC 0.6 V, IO = 0 40 50 mA Ci VI = VCC or GND Co VO = GND 3.3 V 0V 1.5 3.6 V 1.5 0V 2.5 pF pF Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G17 5 SN74AUP1G17 SCES579I – JUNE 2004 – REVISED MARCH 2010 www.ti.com SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN 0.8 V tpd A Y TA = –40°C to 85°C TYP MAX M IN MAX 14.6 UNIT 22.7 1.2 V ± 0.1 V 6.3 8 12.8 3.9 1.5 V ± 0.1 V 4.6 5.8 8.4 2.8 10 1.8 V ± 0.15 V 3.9 4.8 7.2 2.4 8.1 2.5 V ± 0.2 V 3.1 3.6 5.1 2 6.1 3.3 V ± 0.3 V 2.7 3 4.4 1.9 5.1 ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN 0.8 V tpd A Y TA = –40°C to 85°C TYP MAX MIN MAX UNIT 25.1 1.2 V ± 0.1 V 7.1 9.1 13.8 4.7 15.6 1.5 V ± 0.1 V 5.2 6.5 9.4 3.4 11 1.8 V ± 0.15 V 4.5 5.4 8 2.9 9 2.5 V ± 0.2 V 3.5 4.2 5.7 2.4 6.8 3.3 V ± 0.3 V 3.1 3.5 4.9 2.2 5.7 ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN 0.8 V tpd A Y TA = –40°C to 85°C TYP MAX MIN MAX UNIT 27.6 1.2 V ± 0.1 V 7.8 10.1 14.8 5.3 16.7 1.5 V ± 0.1 V 5.8 7.4 10.3 3.9 12 1.8 V ± 0.15 V 5 6.1 8.8 3.4 10 2.5 V ± 0.2 V 4 4.7 6.4 2.8 7.5 3.3 V ± 0.3 V 3.5 4.1 5.4 2.6 6.2 ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN 0.8 V tpd 6 A Y TYP TA = –40°C to 85°C MAX MIN MAX UNIT 35.1 1.2 V ± 0.1 V 10 13.1 18.1 7.5 19.8 1.5 V ± 0.1 V 7.4 9.6 12.9 5.6 14.9 1.8 V ± 0.15 V 6.4 7.9 11 4.8 12.4 2.5 V ± 0.2 V 5.2 6.1 7.9 4 9.3 3.3 V ± 0.3 V 4.6 5.3 6.7 3.6 7.7 Submit Documentation Feedback ns Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G17 SN74AUP1G17 www.ti.com SCES579I – JUNE 2004 – REVISED MARCH 2010 OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC TYP 0.8 V 4 1.2 V ± 0.1 V 4 1.5 V ± 0.1 V 4 1.8 V ± 0.15 V 4 2.5 V ± 0.2 V 4.2 3.3 V ± 0.3 V 4.4 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G17 UNIT pF 7 SN74AUP1G17 SCES579I – JUNE 2004 – REVISED MARCH 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (Propagation Delays, Setup and Hold Times, and Pulse Duration) From Output Under Test CL (see Note A) 1 MΩ LOAD CIRCUIT CL VM VI VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC tw VCC Input VCC/2 VCC/2 VI VM Input 0V VM VOLTAGE WAVEFORMS PULSE DURATION 0V tPHL tPLH VOH VM Output VM VOL tPHL VCC Timing Input VCC/2 0V tPLH tsu VOH VM Output VCC VM VOL Data Input VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. B. C. D. E. th VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G17 SN74AUP1G17 www.ti.com SCES579I – JUNE 2004 – REVISED MARCH 2010 PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times) 2 × VCC S1 5 kΩ From Output Under Test GND CL (see Note A) 5 kΩ TEST S1 tPLZ/tPZL tPHZ/tPZH 2 × VCC GND LOAD CIRCUIT CL VM VI V∆ VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.3 V VCC Output Control Output Waveform 1 S1 at 2 × VCC (see Note B) VCC/2 0V tPLZ tPZL VCC VCC/2 VOL + V∆ VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VCC/2 VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G17 9 PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AUP1G17DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM SN74AUP1G17DSFR ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM SN74AUP1G17YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74AUP1G17YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2010 package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74AUP1G17 : • Enhanced Product: SN74AUP1G17-EP NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Mar-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74AUP1G17DBVR SOT-23 DBV 5 3000 180.0 9.2 SN74AUP1G17DBVR SOT-23 DBV 5 3000 178.0 SN74AUP1G17DBVT SOT-23 DBV 5 250 178.0 SN74AUP1G17DBVT SOT-23 DBV 5 250 SN74AUP1G17DCKR SC70 DCK 5 SN74AUP1G17DCKR SC70 DCK SN74AUP1G17DCKT SC70 DCK SN74AUP1G17DCKT SC70 SN74AUP1G17DRLR SN74AUP1G17YFPR SN74AUP1G17YZPR DSBGA 3.23 3.17 1.37 4.0 8.0 Q3 9.0 3.23 3.17 1.37 4.0 8.0 Q3 9.0 3.23 3.17 1.37 4.0 8.0 Q3 180.0 9.2 3.23 3.17 1.37 4.0 8.0 Q3 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 5 3000 180.0 9.2 2.24 2.34 1.22 4.0 8.0 Q3 5 250 180.0 9.2 2.24 2.34 1.22 4.0 8.0 Q3 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SOT DRL 5 4000 180.0 9.2 1.78 1.78 0.69 4.0 8.0 Q3 DSBGA YFP 4 3000 178.0 8.4 0.89 0.89 0.62 4.0 8.0 Q1 YZP 5 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Mar-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUP1G17DBVR SOT-23 DBV 5 3000 205.0 200.0 33.0 SN74AUP1G17DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74AUP1G17DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74AUP1G17DBVT SOT-23 DBV 5 250 205.0 200.0 33.0 SN74AUP1G17DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74AUP1G17DCKR SC70 DCK 5 3000 205.0 200.0 33.0 SN74AUP1G17DCKT SC70 DCK 5 250 205.0 200.0 33.0 SN74AUP1G17DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74AUP1G17DRLR SOT DRL 5 4000 202.0 201.0 28.0 SN74AUP1G17YFPR DSBGA YFP 4 3000 220.0 220.0 35.0 SN74AUP1G17YZPR DSBGA YZP 5 3000 220.0 220.0 34.0 Pack Materials-Page 2 X: Max = 1430 µm, Min = 1370 µm Y: Max = 930 µm, Min = 870 µm X: Max = 1430 µm, Min = 1370 µm Y: Max = 930 µm, Min = 870 µm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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