ZILOG Z89139

PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
1
Z89138/
Z89139 (ROMLESS)
1
VOICE PROCESSING CONTROLLERS
FEATURES
Device
Z89138
Z89139
ROM
(KB)
RAM*
(Bytes)
I/O
Lines
Voltage
Range
24
256
256
47
47
4.5V to 5.5V
4.5V to 5.5V
Note: *General-Purpose
■
Clock Speeds of 20.48 or 29.49 MHz
■
16-Bit Digital Signal Processor (DSP)
■
6K Word DSP Program ROM
■
512 Words On-Chip DSP RAM
■
Watch-Dog Timer and Power-On Reset
■
8-Bit A/D Converter with up to 16 kHz Sample Rate
■
Improved Low-Power STOP Mode
■
10-Bit PWM D/A Converter
■
On-Chip Oscillator that Accepts a Crystal or External
Clock Drive
■
Six Vectored, Prioritized Z8 Interrupts
■
Three Vectored, Prioritized DSP Interrupts
■
Improved Global Power-Down Mode
■
■
Low-Power Consumption - 200 mW (typical)
Two DSP Timers to Support Different A/D and D/A
Sampling Rates
■
Two Comparators
■
IBM® PC-Based Development Tools
■
RAM and ROM Protect
■
Developer’s Toolbox for T.A.M. Applications
■
On-Board Oscillator for 32.768 kHz Real-Time Clock
IBM is a registered trademark of IBM Corporation.
GENERAL DESCRIPTION
The Z89138/Z89139 is a fully integrated, dual processor
controller designed for voice processing applications. The
I/O control processor is a Z8® MCU with 24 KB of program
memory, two 8-bit counter/timers, and up to 47 I/O pins.
The DSP is a 16-bit processor with a 24-bit ALU and accumulator, 512x16 bits of RAM, single cycle instructions, and
6K words of program ROM. The chip also contains a halfflash 8-bit A/D converter with up to a 16 kHz sample rate
and a 10-bit PWM D/A converter. The sampling rates for
the converters are programmable. The precision of the 8bit A/D can be extended by resampling the data at a lower
rate in software. The Z8 and DSP processors are coupled
by mailbox registers and an interrupt system. DSP or Z8
DS97TAD0201
programs can be directed by events in each other’s domain.
The Z89139 is the ROMless version of the Z89138. However, the on-chip DSP is not ROMless.
Notes: All Signals with a preceding front slash, "/", are active Low. For example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only).
PRELIMINARY
1
Z89138/Z89139
Voice Processing Controllers
Zilog
GENERAL DESCRIPTION (Continued)
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
Z8 Core Processor
The on-chip Z8 is Zilog’s 8-bit microcontroller core with an
Expanded Register File to allow access to registermapped peripheral and I/O circuits. The Z8 offers a flexible
I/O scheme, an efficient register and address space structure and a number of ancillary features, which makes it
ideally suited for high-volume processing, peripheral controllers, and consumer applications.
For applications demanding powerful I/O capabilities, the
Z89138 provides 47 pins dedicated to input and output.
These I/O lines are grouped into six ports. Each port is
configurable under software control to provide timing, status signals and parallel I/O with or without handshake.
Four basic memory resources for the Z8 are available to
support a wide range of configurations: Program Memory,
Register File, Data Memory, and Expanded Register File.
The Z8 core processor is supported by an efficient register
file that allows any of 256 on-board data and control registers to be either the source and/or the destination of almost
any instruction. This unique architecture eliminates traditional microprocessor Accumulator bottlenecks and permits rapid content switching.
The Register File is composed of 236 bytes of general-purpose registers, four I/O port registers, and 15 control and
status registers. The Expanded Register File consists of
mailbox registers, WDT mode register, DSP Control register, Stop-Mode Recovery register, Port Configuration register, and the control and data registers for Port 4 and Port
5. Some of these registers are shared with the DSP.
DSP Coprocessor
The DSP coprocessor is a second generation, 16-bit
two’s- complement CMOS Digital Signal Processor (DSP).
Most instructions, including multiply and accumulate, are
accomplished in a single clock cycle. The processor contains two on-chip data RAM blocks of 256 words, a 6K
word program ROM, 24-bit ALU, 16x16 multiplier, 24-bit
Accumulator, shifter, six-level stack, three vectored interrupts and two inputs for conditional program jumps. Each
RAM block contains a set of four pointers which can be incremented or decremented automatically to affect hardware looping without software overhead. The data RAMs
can be simultaneously addressed and loaded to the multiplier for a true single-cycle scalar multiply.
Four external DSP registers are mapped into the expanded register file of the Z8. Communication between the Z8
and the DSP occurs through those common registers that
form the mailbox registers.
The analog output is generated by a 10-bit resolution
Pulse Width Modulator (PWM). The PWM output is a digital signal with CMOS output levels. The output signal has
a resolution of 1 in 1024 with a sampling rate of 16 kHz
(XTAL = 20.48 MHz). The sampling rate can be changed
under software control and can be set at 10 and 16 kHz.
The dynamic range of the PWM is from 0 to 4V.
An 8-bit resolution half-flash A/D converter is provided.
The conversion is conducted with a sampling frequency of
16 kHz. (XTAL = 20.48 MHz) in order to provide oversampling. The input signal is 4V peak to peak.
Two additional timers (Timer2 and Timer3) have been
added to support different sampling rates for the A/D and
D/A converters. These timers are free-running counters
that divide the crystal frequency to the appropriate sampling of frequency. Two DSP I/O pins: DSP0, DSP1 are
provided for application.
To unburden the software from supporting real-time problems such as counting/timing and data communication, the
Z8 offers two on-chip counter/timers with a large number
of user-selectable modes.
Watch-Dog Timer and Stop-Mode Recovery features are
software driven by setting specific bits in control registers.
STOP and HALT instructions support reduced power operation. The low-power Stop Mode allows parameter information to be stored in the register file if power fails. An external capacitor or battery will retain device memory and
power the 32 kHz timer.
2
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
PIN DESCRIPTION
P00
P01
P02
P03
Address
or I/O
(Nibble
P04
Programmable)
P05
P06
P07
P10
P11
P12
Address/Data
P13
or I/O
P14
(Byte
Programmable) P15
P16
P17
P20
P21
P22
I/O
P23
(Bit
Programmable) P24
P25
P26
P27
Timer 0
Capture Reg.
Register File
256 x 8 Bit
Timer 1
Port 0
Port 3
Register Bus
24 Kbytes
Program
ROM
(Z89138)
Port 1
P31
P32
P33
Internal Address Bus
Z8 Core
1
Input
P34
P35 Output
P36
P37
Internal Data Bus
Port 4
P40
P41
P42
I/O
P43
(Bit
P44 Programmable)
P45
P46
P47
Port 5
P50
P51
P52
P53
P54
P55
P56
P57
Expanded
Register Bus
Expanded Register
File
(Z8)
Extended Bus of the DSP
Peripheral
Register
(DSP)
256 Word
RAM 0
mailbox
256 Word
RAM 1
Port 2
Internal Address Bus
6K Words
Program
ROM
DSP Core
I/O
(Bit
Programmable)
Internal Data Bus
INT 1
INT 2
RMLS
/AS
/DS
R/W
Ext.
Memory
Control
XTAL1
XTAL2
OSC
VDD
GND
/RESET
OSC1
OSC2
DSP Port
DSP0
DSP1
PWM
(10-Bit)
PWM
Extended Bus of the DSP
Timer 2
Timer 3
ADC
(8-Bit)
Power
AN IN
AN VDD
AN GND
VREF+
VREF-
32 kHz
OSC
Figure 1. Z89138/139 Functional Block Diagram
DS97TAD0201
PRELIMINARY
3
Z89138/Z89139
Voice Processing Controllers
Zilog
P07
NC
NC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OSC02
OSC01
GND
NC
NC
PIN DESCRIPTION (Continued)
80
P06
P05
P04
P03
P02
P01
P00
GND
P17
P16
P15
P14
P13
P12
P11
P10
GND
AGND
VREFANIN
75
70
65
60
55
81
51
50
85
45
100-Pin QFP
90
40
95
35
100
5
10
15
20
25
30
VREF+
ANVDD
GND
PWM
RMLS
DSP1
DSP0
/AS
/DS
R//W
NC
P57
P56
P55
P54
VCC
XTAL2
XTAL1
P53
P52
P37
P36
P35
P34
P33
P32
P31
/RESET
P20
P21
1
31
NC
NC
NC
VCC
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P27
P26
P25
P24
P23
P22
Figure 2. Z89138 100-Pin QFP Pin Configuration
4
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Table 1. Z89138 100-Pin QFP Pin Identification
I/O Port
Symbol
Pin
Number
GND
VCC
3, 53, 88, 97
16, 47, 77
VREF+
ANVDD
1
2
Input/Output
PWM
RMLS
DSP1-0
/AS
/DS
R//W
NC
P57-P54
XTAL2
XTAL1
P53-P52
P37-P34
P33-P31
/RESET
P20-P27
P40-P47
P50-P51
NC
OSC1
OSC2
NC
NC
P07-P00
P17-P10
ANGND
VREFANIN
4
5
6, 7
8
9
10
11
12-15
17
18
19, 20
21-24
25-27
28
29-36
37-44
45, 46
48-52
54
55
56-76
78, 79
80-87
89-96
98
99
100
Output
Input
Output
Output
Output
Output
DS97TAD0201
Direction
1
Function
Digital Ground
Digital VCC = +5V
Input/Output
Output
Input
Input/Output
Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input
Output
Input/Output
Input/Output
Input
Input
Analog Voltage Ref+
Analog VDD
PWM Output
Control Input
DSP User Output 1, 0
Address Strobe
Data Strobe
Read/Write
No Connection
Port 5 Bit 7-4
Crystal Output (20.48 or 29.49 MHz)
Crystal Input (20.48 or 29.49 MHz)
Port 5 Bit 3-2
Port 3 Bit 7-4
Port 3 Bit 3-1
Reset
Port 2, Bit 0-7
Port 4, Bit 0-7
Port 5, Bit 0-1
No Connection
Crystal Input (32.768 kHz)
Crystal Output (32.768 kHz)
No Connection
No Connection
Port 0, Bit 7-0
Port 1, Bit 7-0
Analog GND
Analog Voltage RefAnalog Input
PRELIMINARY
5
Z89138/Z89139
Voice Processing Controllers
Zilog
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OSC2
OSC1
GND
PIN DESCRIPTION (Continued)
70
65
60
55
51
50
80
45
85
40
100-Pin VQFP
35
90
30
95
100
1
5
10
15
20
26
25
NC
NC
NC
NC
NC
VCC
P51
P50
P47
P46
P45
P44
P43
P44
P45
P46
P47
P50
P51
VCC
NC
NC
NC
NC
NC
GND
PWM
RMLS
DSP1
DSP0
/AS
/DS
R//W
NC
P57
P56
P55
P54
VCC
XTAL2
XTAL1
P53
P52
P37
P36
P35
P34
P33
P32
P31
NC
NC
P07
P06
P05
P04
P03
P02
P01
P00
GND
P17
P16
P15
P14
P13
P12
P11
P10
GND
AGND
VREFANIN
VREF+
ANVDD
75
76
Figure 3. Z89138 100-Pin VQFP Pin Configuration
6
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Table 2. Z89138 100-Pin VQFP Pin Identification
I/O Port
Symbol
Pin
Number
GND
VCC
1, 51, 86, 95
14, 45, 75
VREF+
ANVDD
99
100
Input/Output
PWM
RMLS
DSP1-0
/AS
/DS
R//W
NC
P57-P54
XTAL2
2
3
4, 5
6
7
8
9
10-13
15
Output
Input
Output
Output
Output
Output
Input/Output
Output
XTAL1
16
Input
P53-P52
P37-P34
P33-P31
/RESET
P20-P27
P40-P47
P50-P51
NC
OSC1
OSC2
NC
NC
P07-P00
P17-P10
ANGND
VREFANIN
17, 18
19-22
23-25
26
27-34
35-42
43, 44
46-50
52
53
54-74
76, 77
78-85
87-94
96
97
98
Input/Output
Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
DS97TAD0201
Direction
1
Symbol
Digital Ground
Digital VCC = +5V
Input
Output
Input/Output
Input/Output
Input
Input
PRELIMINARY
Analog Voltage Ref+
Analog VDD
PWM Output
Control Input
DSP User Output 1, 0
Address Strobe
Data Strobe
Read/Write
No Connection
Port 5 Bit 7-4
Crystal Output (20.48 or
29.49 MHz)
Crystal Input (20.48 or 29.49
MHz)
Port 5 Bit 3-2
Port 3 Bit 7-4
Port 3 Bit 3-1
Reset
Port 2, Bit 0-7
Port 4, Bit 0-7
Port 5, Bit 0-1
No Connection
Crystal Input (32.768 kHz)
Crystal Output (32.768 kHz)
No Connection
No Connection
Port 0, Bit 7-0
Port 1, Bit 7-0
Analog GND
Analog Voltage RefAnalog Input
7
Z89138/Z89139
Voice Processing Controllers
Zilog
P07
NC
NC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OSC02
OSC01
GND
NC
NC
PIN DESCRIPTION (Continued)
80
P06
P05
P04
P03
P02
P01
P00
GND
P17
P16
P15
P14
P13
P12
P11
P10
GND
AGND
VREFANIN
75
70
65
60
55
51
81
50
85
45
100-Pin QFP
90
40
95
35
100
5
10
15
20
25
30
VREF+
ANVDD
GND
PWM
VCC
DSP1
DSP0
/AS
/DS
R//W
NC
P57
P56
P55
P54
VCC
XTAL2
XTAL1
P53
P52
P37
P36
P35
P34
P33
P32
P31
/RESET
P20
P21
1
31
NC
NC
NC
VCC
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P27
P26
P25
P24
P23
P22
Figure 4. Z89139 100-Pin QFP Pin Configuration
8
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Table 3. Z89139 100-Pin QFP Pin Identification
I/O Port
Symbol
Pin Number
GND
VCC
3, 53, 88, 97
5, 16, 47, 77
VREF+
ANVDD
1
2
Input/Output
PWM
DSP1-0
/AS
/DS
R//W
NC
P57-P54
XTAL2
XTAL1
P53-P52
P37-P34
P33-P31
/RESET
P20-P27
P40-P47
P50-P51
NC
OSC1
OSC2
NC
NC
P07-P00
P17-P10
ANGND
VREFANIN
4
6, 7
8
9
10
11
12-15
17
18
19, 20
21-24
25-27
28
29-36
37-44
45, 46
48-52
54
55
56-76
78-79
80-87
89-96
98
99
100
Output
Output
Output
Output
Output
DS97TAD0201
Direction
1
Function
Digital Ground
Digital VCC = +5V
Input/Output
Output
Input
Input/Output
Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input
Output
Input/Output
Input/Output
Input
Input
Analog Voltage Ref+
Analog VDD
PWM Output
DSP User Output 1, 0
Address Strobe
Data Strobe
Read/Write
No Connection
Port 5 Bit 7-4
Crystal Output (20.48 or 29.49 MHz)
Crystal Input (20.48 or 29.49 MHz)
Port 5 Bit 3-2
Port 3 Bit 7-4
Port 3 Bit 3-1
Reset
Port 2, Bit 0-7
Port 4, Bit 0-7
Port 5, Bit 0-1
No Connection
Crystal Input (32.768 kHz)
Crystal Output (32.768 kHz)
No Connection
No Connection
Port 0, Bit 7-0
Port 1, Bit 7-0
Analog GND
Analog Voltage RefAnalog Input
PRELIMINARY
9
Z89138/Z89139
Voice Processing Controllers
Zilog
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OSC2
OSC1
GND
PIN DESCRIPTION (Continued)
70
65
60
55
51
50
80
45
85
40
100-Pin VQFP
35
90
30
95
100
1
5
10
15
20
26
25
NC
NC
NC
NC
NC
VCC
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P27
P26
P25
P24
P23
P22
P21
P20
/RESET
GND
PWM
VCC
DSP1
DSP0
/AS
/DS
R//W
NC
P57
P56
P55
P54
VCC
XTAL2
XTAL1
P53
P52
P37
P36
P35
P34
P33
P32
P31
NC
NC
P07
P06
P05
P04
P03
P02
P01
P00
GND
P17
P16
P15
P14
P13
P12
P11
P10
GND
AGND
VREFANIN
VREF+
ANVDD
75
76
Figure 5. Z89139 100-Pin VQFP Pin Configuration
10
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Table 4. Z89139 100-Pin VQFP Pin Identification
I/O Port
Symbol
Pin Number
GND
VCC
1, 51, 86, 95
3, 14, 45, 75
VREF+
ANVDD
99
100
Input/Output
PWM
DSP1-0
/AS
/DS
R//W
NC
P57-P54
XTAL2
XTAL1
P53-P52
P37-P34
P33-P31
/RESET
P20-P27
P40-P47
P50-P51
NC
OSC1
OSC2
NC
NC
P07-P00
P17-P10
ANGND
VREFANIN
2
4, 5
6
7
8
9
10-13
15
16
17, 18
19-22
23-25
26
27-34
35-42
43, 44
46-50
52
53
54-74
76, 77
78-85
87-94
96
97
98
Output
Output
Output
Output
Output
DS97TAD0201
Direction
1
Function
Digital Ground
Digital VCC = +5V
Input/Output
Output
Input
Input/Output
Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input
Output
Input/Output
Input/Output
Input
Input
PRELIMINARY
Analog Voltage Ref+
Analog VDD
PWM Output
DSP User Output 1, 0
Address Strobe
Data Strobe
Read/Write
No Connection
Port 5 Bit 7-4
Crystal Output (20.48 or 29.49 MHz)
Crystal Input (20.48 or 29.49 MHz)
Port 5 Bit 3-2
Port 3 Bit 7-4
Port 3 Bit 3-1
Reset
Port 2, Bit 0-7
Port 4, Bit 0-7
Port 5, Bit 0-1
No Connection
Crystal Input (32.768 kHz)
Crystal Output (32.768 kHz)
No Connection
No Connection
Port 0, Bit 7-0
Port 1, Bit 7-0
Analog GND
Analog Voltage RefAnalog Input
11
Z89138/Z89139
Voice Processing Controllers
Zilog
ABSOLUTE MAXIMUM RATINGS
Sym
Description
Min
Max
Units
VCC
Supply
Voltage (*)
Storage Temp
–0.3
+7.0
V
–65°
+150°
C
†
C
TSTG
TA
Oper.
Ambient
Temp.
Stresses greater than those listed under Absolute Maximum Ratings can cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for an extended period can affect device reliability.
Notes:
*Voltage on all pins with respect to GND.
†See Ordering Information.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Figure 6).
+5V
2.1 kΩ
From Output
Under Test
150 pF
9.1 kΩ
Figure 6. Test Load Diagram
CAPACITANCE
TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured
pins returned to GND.
Parameter
Input capacitance
Output capacitance
I/O capacitance
12
Min
Max
0
0
0
12 pF
12 pF
12 pF
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
DC ELECTRICAL CHARACTERISTICS
Sym
Parameter
VCC
Note 1
TA = 0°C to +55°C
Min
Max
Typical
@ 25°C
Units
1
Conditions
ICC
Supply Current
5.0V
65
40
mA
ICC1
Halt Mode Current
5.0V
20
6
mA
ICC2
Stop Mode Current
5.0V
20
6
µA
See Note 2
VMAX
Max Input Voltage
5.0V
7
VCH
5.0V
0.9 VCC
VCC +0.3
2.5
V
5.0V
GND –0.3
0.1 VCC
1.5
V
Driven by External
Clock Generator
Driven by External
Clock Generator
VIH
Clock Input High
Voltage
Clock Input Low
Voltage
Input High Voltage
5.0V
0.7 VCC
VCC +0.3
2.5
V
VIL
Input Low Voltage
5.0V
GND –0.3
0.2 VCC
1.5
V
VOH
Output High Voltage
5.0V
VCC–0.4
4.8
V
IOH = –2.0 mA
VOL1
Output Low Voltage
5.0V
0.4
0.1
V
IOL = +4.0 mA
VOL2
Output Low Voltage
5.0V
1.2
0.3
V
IOL = +12 mA, 3 Pin
Max
VRH
5.0V
.8 VCC
VCC
2.1
V
5.0V
GND –0.3
0.2 VCC
1.7
25
10
mV
IIL
Reset Input High
Voltage
Reset Input Low
Voltage
Comparator Input
Offset
Voltage
Input Leakage
5.0V
–10
10
10
µA
IOL
Output Leakage
5.0V
–10
10
10
µA
IIR
Reset Input Current
5.0V
–55
–30
µA
VCL
VRl
VOFFSET
5.0V
Notes:
1. 5.0V ±0.5V
2. When a 32 kHz crystal is used, additional value must be added to the STOP Mode current ICC2.
The sum will be 200 µA/max, 150 µA/typical.
DS97TAD0201
PRELIMINARY
13
Z89138/Z89139
Voice Processing Controllers
Zilog
DC ELECTRICAL CHARACTERISTICS
Z89138 A/D Converter
TA = 0° C to +55°C
Sym
IIL
IIH
IVREFH
IVREFL
IVEFL
IVREFL
14
Parameter
Input Leakage
Analog Input
Input Leakage
Analog Input
Input Current
Input Current
Input Current
Input Current
VDD
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
Min
Max
Units
1.00
µA
2.00
1.00
2
–2.00
2
µA
mA
µA
mA
µA
PRELIMINARY
Conditions
ANVDD
=
5.50
V
VIN
=
0.00
V
VREFH
=
5.50
V
VREFL
=
0.00
V
ANVDD
=
5.50
V
VIN
=
5.50
V
VREFH
=
5.50
V
VREFL
=
0.00
V
VIN
=
5.50
V
VREFL
=
0.00
V
ANVDD
=
5.50
V
VIN
=
5.50
V
VREFL
=
5.50
V
ANVDD
=
5.50
V
VIN
=
0.00
V
VREFH
=
5.50
V
ANVDD
=
0.00
V
VIN
=
0.00
V
VREFH
=
5.50
V
ANVDD
=
5.50
V
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
DC ELECTRICAL CHARACTERISTICS
21 Other Non-Regular I/O
1
TA = 0° C to +55°C
Sym
Parameter
VDD
Min
Max
Units
Conditions
IIRH
Input Current ROMless Pin
5.5V
6.00
µA
VIN = 5.50 V
IIR1
Input Current ROMless Pin
5.5V
6.00
µA
VIN = 0.00 V
IIR
Input Current ROMless Pin
During Reset Active
Input Current
XTAL2 pin in STOP Mode
Input Current
XTAL2 Pin in STOP Mode
Input current
XTAL1 Pin
Input Current
XTAL1 Pin
Output Low
Voltage XTAL2 Reset Inactive
Output Low
Voltage XTAL2 Reset Inactive
Output High
Voltage XTAL2 Reset Inactive
Output High
Voltage XTAL2 Reset Inactive
Input Current
P31, P32, P33
Input Current
P31, P32, P33
5.5V
1.00
mA
VIN = 5.50 V
5.5V
1.00
µA
VIN = 0.00 V
5.5V
1.00
µA
VIN = 5.50 V
5.5V
30
µA
VIN = 0.00 V
5.5V
30
µA
VIN = 5.50 V
5.5V
1.20
V
IOL = 4.00 mA
5.5V
0.60
V
IOL =1.00 mA
IIHX2
IILX2
IIHX1
IILX1
VOLXR
VOLX
VOHXR
IVOHX
IIH
IIL
DS97TAD0201
5.5V
4.00
V
IOH = 4.00 mA
5.5V
4.00
V
IOH =1.00 mA
5.5V
1.00
µA
VIN = 5.50 V
5.5V
1.00
µA
VIN = 0.00 V
PRELIMINARY
15
Z89138/Z89139
Voice Processing Controllers
Zilog
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Diagram
R//W
13
12
Port 0, /DM
16
19
Port 1
3
A7 - A0
1
D7 - D0 IN
2
9
/AS
18
8
11
4
5
/DS
(Read)
6
17
10
Port1
A7 - A0
D7 - D0 OUT
14
15
7
/DS
(Write)
Figure 7. External I/O or Memory Read/Write Timing
16
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Table
VCC
No
Symbol
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TdAZ(DS)
TwDSR
TwDSW
TdDSR(DR)
ThDR(DS)
TdDS(A)
TdDS(AS)
TdR/W(AS)
TdDS(R/W)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)
TdDI(DS)
TdDM(AS)
Address Valid to /AS Rise Delay
/AS Rise to Address Float Delay
/AS Rise to Read Data Req’d Valid
/AS Low Width
Address Float to /DS Fall
/DS (Read) Low Width
/DS (Write) Low Width
/DS Fall to Read Data Req’d Valid
Read Data to /DS Rise Hold Time
/DS Rise to Address Active Delay
/DS Rise to /AS Fall Delay
R//W Valid to /AS Rise Delay
/DS Rise to R//W Not Valid
Write Data Valid to /DS Fall (Write) Delay
/DS Rise to Write Data Not Valid Delay
Address Valid to Read Data Req’d Valid
/AS Rise to /DS Fall Delay
Data Input Setup to /DS Rise
/DM Valid to /AS Fall Delay
1
TA= 0°C to +55°C
Note [4]
Min
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
25
35
Max
150
35
0
125
75
90
0
40
35
25
35
40
25
180
48
50
20
Units
Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2,3
2,3
1,2,3
2,3
1,2,3
1,2,3
1,2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
1,2,3
2,3
1,2,3
2,3
Notes:
1. When using extended memory timing add 2 TpC.
2. Timing numbers given are for minimum TpC.
3. See clock cycle dependent characteristics table.
4. 5.0V ±0.5 V.
Standard Test Load
All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
DS97TAD0201
PRELIMINARY
17
Z89138/Z89139
Voice Processing Controllers
Zilog
AC ELECTRICAL CHARACTERISTICS
Additional Timing Diagram
3
1
Clock
2
7
2
3
7
TIN
4
5
6
IRQN
8
9
Clock
Setup
11
Stop
Mode
Recovery
Source
10
Figure 8. Additional Timing
18
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
AC ELECTRICAL CHARACTERISTICS
Additional Timing Table
VCC
No
Sym
Parameter
1
2
3
4
5
6
7
8a
8b
9
10
11
12
TpC
TrC,TfC
TwC
TwTinL
TwTinH
TpTin
TrTin, TfTin
TwIL
TwIL
TwIH
Twsm
Tost
Twdt
Input Clock Period
Clock Input Rise & Fall Times
Input Clock Width
Timer Input Low Width
Timer Input High Width
Timer Input Period
Timer Input Rise & Fall Timer
Int. Request Low Time
Int. Request Low Time
Int. Request Input High Time
Stop-Mode Recovery Width Spec
Oscillator Start-up Time
Watch-Dog Timer
1
TA= 0°C to +55°C
Note 5
Min
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
48.83
Max
6
17
70
3TpC
8TpC
100
70
3TpC
3TpC
12
5TpC
5
15
25
100
Units
Notes
ns
ns
ns
ns
1, 6
1
1,7
ns
ns
ns
ms
ms
ms
ms
1
1
1
1,2
1
1
1
3
D1 = 0, D0 = 0 [4]
D1 = 0, D0 = 1 [4]
D1 = 1, D0 = 0 [4]
D1 = 1, D0 = 1 [4]
Notes:
1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2. Interrupt request via Port 3 (P31-P33).
3. SMR-D5 = 0
4. Reg. WDT
5. 5.0V ±0.5 V
6. For 29.49 MHz, it will be 30.53 ns.
7. For 29.49 MHz, it will be 9 ns.
DS97TAD0201
PRELIMINARY
19
Z89138/Z89139
Voice Processing Controllers
Zilog
AC ELECTRICAL CHARACTERISTICS
Handshake Timing Diagrams
Data In Valid
Data In
Next Data In Valid
2
1
3
Delayed DAV
/DAV
(Input)
4
5
RDY
(Output)
6
Delayed RDY
Figure 9. Input Handshake Timing
Data Out Valid
Data Out
Next Data Out Valid
7
/DAV
(Output)
Delayed DAV
8
9
11
10
RDY
(Input)
Delayed
RDY
Figure 10. Output Handshake Timing
20
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
AC ELECTRICAL CHARACTERISTICS
Handshake Timing Table
VCC
TA= 0°C to +55°C
No
Symbol
Parameter
Note
Min
1
2
3
4
5
6
7
8
9
10
11
TsDI(DAV)
ThDI(RDY)
TwDAV
TdDAVI(RDY)
TdDAVId(RDY)
TdDO(DAV)
TcLDAV0(RDY)
TcLDAV0(RDY)
TdRDY0(DAV)
TwRDY
TdRDY0d(DAV)
Data In Setup Time
RDY to Data Hold Time
Data Available Width
DAV Fall to RDY Fall Delay
DAV Rise to RDY Rise Delay
RDY Rise to DAV Fall Delay
Data Out to DAV Fall Delay
DAV Fall to RDY Fall Delay
RDY Fall to DAV Rise Delay
RDY Width
RDY Rise to DAV Fall Delay
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
0
0
40
Max
70
40
0
TpC
0
70
40
40
Units
Data
Direction
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
1
Note: 5.0V ±0.5V
DS97TAD0201
PRELIMINARY
21
Z89138/Z89139
Voice Processing Controllers
Zilog
PIN FUNCTIONS
/RESET (input, active Low). This pin initializes the MCU.
Reset is accomplished either through Power-On Reset
(POR), Watch-Dog Timer (WDT) reset, Stop-Mode Recovery, or external reset. During POR and WDT Reset, the internally generated reset signal is driving the reset pin Low
for the POR time. Any devices driving the reset line must
be open-drain to avoid damage from a possible conflict
during reset conditions. A /RESET will reset both the Z8
and the DSP.
For the Z8: After the POR time, /RESET is a Schmitt-triggered input. To avoid asynchronous and noisy reset problems, the Z8 is equipped with a reset filter of four external
clocks (4TpC). If the external reset signal is less than 4TpC
in duration, no reset occurs. On the fifth clock after the
/RESET is detected, an internal RST signal is latched and
held for an internal register count of 18 external clocks, or
for the duration of the external reset, whichever is longer.
Program execution begins at location 000CH (hexadecimal), 5-10 TpC cycles after /RESET is released. The Z8
does not reset WDT, SMR, P2M, and P3M registers on a
Stop-Mode Recovery operation.
For the DSP: After POR, the DSP is in RUN mode. The Z8
controls the DSP commands to HALT, RUN or RESET.
When the DSP is in HALT mode, it cannot be woke up with
WDT or SMR.
RMLS ROMless (input, active High). This pin, when connected to VDD, disables the internal Z8 ROM. (Note that,
when pulled Low to GND, the device functions normally as
the ROM version.) The DSP cannot be configured as
ROMless. This pin is only available on the Z89138.
R//W Read/Write (output, write Low). The R//W signal defines the signal flow when the Z8 is reading or writing to an
external program or data memory. The Z8 is reading when
this pin is High and writing when this pin is Low.
XTAL2 Crystal 2 (time-based output). This pin connects a
parallel-resonant, crystal, ceramic resonant, or LC network
to the on-chip oscillator output.
DSP0 (output). DSP0 is a general-purpose output pin connected to bit 6 of the Analog Control Register (DSP EXT4).
This bit has no special significance and can be used to output data by writing to bit 6 of the ACR.
DSP1 (output). DSP1 is a general-purpose output pin connected to bit 7 of the Analog Control Register (DSP EXT4).
This bit has no special significance and can be used to output data by writing to bit 7 of the ACR.
PWM Pulse Width Modulator (Output). The PWM is a 10bit resolution D/A converter. This output is a digital signal
with CMOS output levels.
ANIN (input). Analog input for the A/D converter.
ANVDD. Analog power supply for the A/D converter.
VREF+ (input). Reference voltage (High) for the A/D converter.
VDD. Digital power supply for the Z89138.
GND. Digital ground for the Z89138.
OSC1 Oscillator 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, RC network to the on-chip oscillator input.
OSC2 Oscillator 2 (time-based output). This pin connects
a parallel-resonant crystal, ceramic resonator, LC, RC network to the on-chip oscillator output.
NC No Connect. For the 100-pin QFP package, pins 63
through 76, and pins 78 and 79 should be tied to Ground.
Other NC pins must float.
/AS Address Strobe (output, active Low). Address Strobe
is pulsed once at the beginning of each machine cycle. Address output is through Port 0/Port 1 for all external programs. Memory address transfers are valid at the trailing
edge of /AS. Under program control, /AS is placed in the
high-impedance state along with Ports 0 and 1, Data
Strobe, and Read/Write.
/DS Data Strobe (output, active Low). Data Strobe is activated once for each external memory transfer. For read
operations, data must be available prior to the trailing edge
of /DS. For write operations, the falling edge of /DS indicates that output data is valid.
XTAL1 Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, RC network, or an external single-phase clock to the on-chip oscillator input.
22
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS
compatible port. These eight I/O lines are configured under software control as a nibble I/O port, or as an address
port for interfacing external memory. The input buffers are
Schmitt-triggered and the output drivers are push-pull.
Port 0 is placed under handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control /DAV0 and RDY0. Handshake signal direction is dictated by the I/O direction to Port 0 of the upper
nibble P07-P04. The lower nibble must have the same direction as the upper nibble.
The Auto Latch on Port 0 puts valid CMOS levels on all
CMOS inputs which are not externally driven. Whether this
level is 0 or 1 cannot be determined. A valid CMOS level,
rather than a floating node, reduces excessive supply current flow in the input buffer.
For external memory references, Port 0 provides address
bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of
Port 0 can be programmed independently as I/O while the
lower nibble is used for addressing. If one or both nibbles
are needed for I/O operation, they are configured by writing to the Port 0 mode register.
In ROMless mode, after a hardware reset, Port 0 is configured as address lines A15-A8, and extended timing is set
to accommodate slow memory access. The initialization
routine can include reconfiguration to eliminate this extended timing mode. (In ROM mode, Port 0 is defined as
input after reset.)
Port 0 is set in the high-impedance mode if selected as an
address output state along with Port 1 and the control signals /AS, /DS, and R//W (Figure 11).
4
Z89138/139
MCU
Port 0
(I/O or A15 - A8)
4
Handshake Controls
/DAV0 and RDY0
(P32 and P35)
OEN
Pad
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 11. Port 0 Configuration
DS97TAD0201
PRELIMINARY
23
1
Z89138/Z89139
Voice Processing Controllers
Zilog
PIN FUNCTIONS (Continued)
Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOS
compatible port (Figure 12). It has multiplexed Address
(A7-A0) and Data (D7-D0) ports. These eight I/O lines are
programmed as inputs or outputs, or can be configured under software control as an Address/Data port for interfacing external memory. The input buffers are Schmitt-triggered and the output drivers are push-pull.
Port 1 can be placed under handshake control. In this configuration, Port 3, lines P33 and P34 are used as the handshake controls RDY1 and /DAV1 (Ready and Data Avail-
able). Memory locations greater than 24575 (Z89138) (in
ROM mode) are referenced through Port 1. To interface
external memory, Port 1 must be programmed for the multiplexed Address/Data mode. If more than 256 external locations are required, Port 0 outputs the additional lines.
Port 1 can be placed in the high-impedance state along
with Port 0, /AS, /DS, and R//W, allowing the Z89138/139
to share common resources in multiprocessor and DMA
applications.
8
Z89138/139
MCU
Port 1
(I/O or AD7 - AD0)
Handshake Controls
/DAV2 and RDY2
(P31 and P36)
OEN
Pad
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 kΩ
Figure 12. Port 1 Configuration
24
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS
compatible I/O port. These eight I/O lines are configured
under software control independently as inputs or outputs.
Port 2 is always available for I/O operation. The input buffers are Schmitt-triggered. Bits programmed as outputs can
be globally programmed as either push-pull or open-drain.
Port 2 can be placed under handshake control. In this configuration, Port 3 lines P31 and P36 are used as the handshake controls lines /DAV2 and RDY2. The handshake
signal assignment for Port 3 lines P31 and P36 is dictated
by the direction (input or output) assigned to bit 7, Port 2
(Figure 13).
The Auto Latch on Port 2 puts valid CMOS levels on all
CMOS inputs which are not externally driven. Whether this
level is 0 or 1, cannot be determined. A valid CMOS level,
rather than a floating node, reduces excessive supply current flow in the input buffer.
Port 2
(I/O)
Z89138/139
MCU
Handshake Controls
/DAV2 and RDY2
(P31 and P36)
Open-Drain
OEN
Pad
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 13. Port 2 Configuration
DS97TAD0201
PRELIMINARY
25
1
Z89138/Z89139
Voice Processing Controllers
Zilog
PIN FUNCTIONS (Continued)
Port 3 (P37-P31). Port 3 is a 7-bit, CMOS compatible port
with three fixed inputs (P33-P31) and four fixed outputs
(P37-P34). It is configured under software control for input/output, counter/timers, interrupt, and port handshakes.
Pins P31, P32, and P33 are standard CMOS inputs; outputs are push-pull.
Two on-board comparators can process analog signals on
P31 and P32 with reference to the voltage on P33. The analog function is enabled by programming bit 1 of the Port 3
Mode Register. Port 3, pin 3 is a falling edge interrupt input. P31 and P32 are programmable as rising, falling or
both edge-triggered interrupts (IRQ register bits 6 and 7).
P33 is the comparator reference voltage input. Access to
counter/timer1 is made through P31 (TIN) and P36 (TOUT).
Handshake lines for ports 0, 1, and 2 are available on P31
through P36.
Port 3 also provides the following control functions: handshake for Ports 0, 1, and 2 (/DAV and RDY); three external
interrupt request signals (IRQ3-IRQ1); timer input and output signals (TIN and TOUT) (Figure 14).
Comparator Inputs. Port 3, pins P31 and P32 all have a
comparator front end. The comparator reference voltage,
pin P33, is common to both comparators. In analog mode,
P31 and P32 are the positive inputs to the comparators
and P33 is the reference voltage supplied to both comparators. In digital mode, pin P33 can be used as a P33 register input or IRQ1 source.
Table 5. Port 3 Pin Assignments
Pin
I/O
CTC1
AN IN
Int.
P31
IN
TIN
AN1
IRQ2
P32
P33
P34
P35
P36
IN
IN
OUT
OUT
OUT
AN2
REF
IRQ0
IRQ1
P37
OUT
P0 HS
P1 HS
P2 HS
EXT
D/R
D/R
D/R
R/D
DM
R/D
TOUT
R/D
Notes:
HS = Handshake Signals
D = DAV
R = RDY
26
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
1
1
2
Port 3
(I/O or Control)
Z89138/139 3
MCU
4
5
6
7
R247 = P3M
D1
1 = Analog
0 = Digital
DIG.
IRQ2, TIN, P31 Data
Latch
P31 (AN1)
+
AN.
-
IRQ0, P32 Data Latch
P32 (AN2)
+
P33 (REF)
-
IRQ1, P33 Data Latch
From Stop Mode
Recovery Source
Figure 14. Port 3 Configuration
DS97TAD0201
PRELIMINARY
27
Z89138/Z89139
Voice Processing Controllers
Zilog
PIN FUNCTIONS (Continued)
Port 4 (P47-P40). Port 4 is an 8-bit, bidirectional, CMOS
compatible I/O port (Figure 15). These eight I/O lines are
configured under software control independently as inputs
or outputs. Port 4 is always available for I/O operation. The
input buffers are Schmitt-triggered. Bits programmed as
outputs can be globally programmed as either push-pull or
open-drain.
Z89138/139
MCU
Port 4 is a bit programmable general-purpose I/O port. The
control registers for Port 4 are mapped into the expanded
register file (Bank F) of the Z8.
Auto Latch. The Auto Latch on Port 4 puts valid CMOS
levels on all CMOS inputs which are not externally driven.
Whether this level is 0 or 1 cannot be determined. A valid
CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer.
Port 4
(I/O)
Open-Drain
OEN
Pad
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 15. Port 4 Configuration
28
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Port 5 (P53-P50). Port 5 is a 4-bit, bidirectional, CMOS
compatible I/O port (Figure 16). These four I/O lines are
configured under software control independently as inputs
or outputs. Port 5 is always available for I/O operation. The
input buffers are Schmitt-triggered. Bits programmed as
outputs can be globally programmed as either push-pull or
open-drain.
Z89138/139
MCU
Port 5 is a bit programmable general-purpose I/O port. The
control registers for Port 5 are mapped into the expanded
register file (Bank F) of the Z8.
Auto Latch. The Auto Latch on Port 5 puts valid CMOS
levels on all CMOS inputs which are not externally driven.
Whether this level is 0 or 1 cannot be determined. A valid
CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer.
Port 5
(I/O)
Open-Drain
OEN
Pad
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 16. Port 5 Configuration
DS97TAD0201
PRELIMINARY
29
1
Z89138/Z89139
Voice Processing Controllers
Zilog
Z8 FUNCTIONAL DESCRIPTION
The Z8 core of the Z89138/139 incorporates special functions to enhance the Z8’s application in a variety of voiceprocessing applications.
Reset. The device is reset in one of the following conditions:
■
Power-On Reset
■
Watch-Dog Timer
■
Stop-Mode Recovery Source
■
External Reset
Program Memory. The Z8 addresses up to 24 KB of internal program memory and 40 KB external memory (Figure
17). The first 12 bytes of program memory are reserved for
the interrupt vectors. These locations contain six 16-bit
vectors which correspond to the five user interrupts and
one DSP interrupt. Byte 12 to byte 24575 consist of onchip mask-programmed ROM. At addresses 24576 and
greater the Z8 executes external program memory. In
ROMless mode, the Z8 will execute external program
memory beginning at byte 12 and continuing through byte
65535.
65535
ROM Protect. The 24 KB of internal program memory for
the Z8 is mask programmable. A ROM protect feature prevents “dumping” of the ROM contents of Program Memory
by inhibiting execution of LDC, LDCI, LDE, and LDEI instructions. The ROM Protect option is mask-programmable, to be selected by the customer at the time the ROM
code is submitted.
Data Memory (/DM). In ROM Mode, the Z8 can address
up to 40 KB of external data memory beginning at location
24576 (Figure 18). In ROMless mode, the Z8 can address
the full 64 KB of external data memory beginning at location 12. External data memory can be included with, or
separated from, the external program memory space.
/DM, an optional I/O function that can be programmed to
appear on Port 34, is used to distinguish between data and
program memory space. The state of the /DM signal is
controlled by the type of instruction being executed. An
LDC opcode references PROGRAM (/DM inactive) memory, and an LDE instruction references data (/DM active
Low) memory (Figure 18).
65535
External
ROM and RAM
24575
Location of
First Byte of
Instruction
Executed
After RESET 12
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
External
Data
Memory
On-Chip
ROM
In ROM Mode
11
IRQ5
10
IRQ5
9
IRQ4
8
IRQ4
7
IRQ3
6
IRQ3
5
IRQ2
4
IRQ2
3
IRQ1
2
IRQ1
1
IRQ0
0
IRQ0
24575
Not Addressable
(In ROM Mode)
0
Figure 18. Data Memory Map
Figure 17. Program Memory
30
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Register File. The standard Z8 register file consists of four
I/O port registers, 236 general-purpose registers, and 15
control and status registers (R0-R3, R4-R239, and R241R255, respectively). The instructions access registers directly or indirectly through an 8-bit address field. This allows a short, 4-bit register address using the Register
Pointer (Figure 19). In the 4-bit mode, the register file is
divided into 16 working register groups, each occupying 16
continuous locations. The Register Pointer addresses the
starting location of the active working register group (Figure 20).
The SMR register, WDT Register, control and data registers for Port 4 and Port 5, and the DSP control register are
located in Bank F of the Expanded Register File. Bank B
of the Expanded Register File consists of the Mailbox Interface through which the Z8 and the DSP communicate.
The rest of the Expanded Register is not physically implemented and is open for future expansion.
R253 RP
D7 D6 D5 D4
D3 D2 D1 D0
Note: Register Group E (Registers EF-E0) is only accessed through a working register and indirect addressing
modes.
RAM Protect. The upper portion of the Z8’s RAM address
spaces 80H to EFH (excluding the control registers) is protected from reading and writing. The RAM Protect bit option is mask-programmable and is selected by the customer when the ROM code is submitted. After the mask option
is selected, the user activates the RAM Protect from the internal ROM code by loading a bit D6 in the IMR register to
either a 0 (OFF) or a 1 (ON). A 1 in D6 indicates RAM Protect enabled.
Stack. The Z8’s external data memory or the internal register file is used for the stack. The 16-bit Stack Pointer
(R255-R254) is used for the external stack which can reside only from 24576 to 65535 in ROM mode or 0 to 65535
in ROMless mode. An 8-bit Stack Pointer (R255) is used
for the internal stack residing within the 236 general-purpose registers (R239-R4). SPH can be used as a generalpurpose register when using internal stack only.
Expanded Register File. The register file on the Z8 has
been expanded to allow for additional system control registers and for mapping of additional peripheral devices
along with I/O ports into the register address area. The Z8
register address space has been implemented as 16
banks of 16 register groups per bank (Figure 20). These
register banks are known as the ERF (Expanded Register
File). Bits 7-4 of register RP (Register Pointer) select the
working register group. Bits 3-0 of register RP select the
Expanded Register bank (Figure 21).
Expanded Register File Bank
Working Register Group
Figure 19. Register Pointer Register
R255
r7 r6
r5 r4
r3 r2
r1 r0
Group 15 (F) Control Registers
R253
R240
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group
R239
Group 14 (E)
R223
Group 13 (D)
R79
Group 4 (4)
Group 3 (3)
Specified Working
Register Group
R63
R47
Group 2 (2)
The upper nibble
of the register
file address
provided by the
instruction points
to the specified
working-register
group
R31
Group 1 (1)
R15
Group 0 (0)
I/O Ports
R3
R0
Figure 20. Register Pointer
DS97TAD0201
PRELIMINARY
31
1
Z89138/Z89139
Voice Processing Controllers
Zilog
Z8 FUNCTIONAL DESCRIPTION (Continued)
Z8 STANDARD CONTROL REGISTERS
REGISTER POINTER
7
6
5
4
3
2
1
REGISTER BANK (0)
RESET CONDITION
REGISTER GROUP 15(F)
D7 D6 D5 D4 D3 D2 D1 D0
FFH
SPL
FEH
SPH
0
FDH
Working Register
Group Pointer
FCH
Expanded Register
Bank Pointer
FBH
FAH
F9H
Z8 Reg. File
†
F8H
*
*
F7H
FFH
FOH
F6H
F5H
% F4
F3H
F2H
F1H
F0H
RP
FLAGS
IMR
IRQ
IPR
P01M
P3M
P2M
PRE0
T0
PRE1
T1
TMR
Reserved
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
0
0
0
0
0
0
0
0
U
U
U
U
U
U
U
U
0
U
U
U
U
U
U
U
0
0
0
0
0
0
0
0
U
U
U
U
U
U
U
U
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
U
U
U
U
U
U
U
0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
0
0
U
U
U
U
U
U
U
U
0
0
0
0
0
0
0
0
Z8 EXPANDED REGISTER BANK (F)
REGISTER GROUP 0 (0)
F
7FH
*
C
B
Re
A
se
9
rve
8
*
5
4
3
rve
se
1
Re
2
0
(F) 0FH
WDTMR
(F) 0EH
HSEC
(F) 0DH
Reserved
U
U
U
0
1
1
0
1
(F) 0CH
DSP CON
U
U
U
1
U
U
U
U
(F) 0BH
SMR
0
0
1
0
0
0
0
0
(F) 0AH
Reserved
(F) 09H
Reserved
(F) 08H
Reserved
(F) 07H
Reserved
(F) 06H
P45CON
U
U
U
0
U
U
U
0
(F) 05H
P5M
1
1
1
1
1
1
1
1
(F) 04H
P5
U
U
U
U
U
U
U
U
(F) 03H
P4M
1
1
1
1
1
1
1
1
(F) 02H
P4
U
U
U
U
U
U
U
U
(F) 01H
Reserved
(F) 00H
PCON
1
1
1
1
1
1
1
0
d
7
6
d
0FH
00H
RESET CONDITION
E
D
Notes:
U = Unknown
Z8 EXPANDED REGISTER BANK (B)
† = For ROMless mode, RESET Condition 10110110
* Will not be Reset with a Stop-Mode Recovery
Z8-DSP
Mailbox Interface
(R0...R15)
Z8 STANDARD REGISTER BANK (0)
REGISTER GROUP 0
*
*
*
*
RESET CONDITION
(0) 03H
P3
1
1
1
1
U
U
U
U
(0) 02H
P2
U
U
U
U
U
U
U
U
(0) 01H
P1
U
U
U
U
U
U
U
U
(0) 00H
P0
U
U
U
U
U
U
U
U
Figure 21. Expanded Register File Architecture
32
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Interrupts. The Z8 has six different interrupts from six different sources. The interrupts are maskable and prioritized
(Figure 22). The six sources are divided as follows; three
sources are claimed by Port 3 lines P33-P31, two by
counter/timers, and one by the DSP (Table 6). The Interrupt Mask Register globally or individually enables or disables the six interrupt requests.
IRQ0 IRQ2
IRQ1, 3, 4, 5
Interrupt
Edge
Select
IRQ Register
(D6, D7)
IRQ
IMR
6
IPR
Global
Interrupt
Enable
Interrupt
Request
Priority
Logic
Vector Select
Figure 22. Interrupt Block Diagram
Table 6. Interrupt Types, Sources, and Vectors
Name
Source
Vector Location
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
/DAV0, P32, AN2
/DAV1, P33
/DAV2, P31, TIN, AN2
IRQ3
T0
TI
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
DS97TAD0201
Comments
External (P32), Programmable Rise or Fall Edge Triggered
External (P33), Fall Edge Triggered
External (P31), Programmable Rise or Fall Edge Triggered
Internal (DSP activated), Fall Edge Triggered
Internal
Internal
PRELIMINARY
33
1
Z89138/Z89139
Voice Processing Controllers
Zilog
Z8 FUNCTIONAL DESCRIPTION (Continued)
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by
the Interrupt Priority Register. An interrupt machine cycle
is activated when an interrupt request is granted. This disables all subsequent interrupts, pushes the Program
Counter and Status Flags to the stack, and then branches
to the program memory vector location reserved for that interrupt.
All Z8 interrupts are vectored through locations in the program memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request Register can be polled to determine
which of the interrupt requests needs service.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 can be rising, falling or both edge triggered, and are programmable by the user. The software
can poll to identify the state of the pin.
Programming bits for the Interrupt Edge Select are located
in the IRQ Register (R250), bits D7 and D6 . The configuration is shown in Table 7.
Table 7. IRQ Register
IRQ
D7
0
0
1
1
Interrupt Edge
D6
0
1
0
1
P31
F
F
R
R/F
P32
F
R
F
R/F
Notes:
F = Falling Edge
R = Rising Edge
Clock. The Z89138/139 on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a crystal, LC,
ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 20.48 MHz maximum, with a series resistance
(RS) less than or equal to 100 Ohms. The system clock
(SCLK) is one half the crystal frequency.
The crystal is connected across XTAL1 and XTAL2 using
capacitors from each pin to Ground (Figure 23).
XTAL1
C1
XTAL1
XTAL1
XTAL2
XTAL2
C1
L
XTAL2
C2
C2
Ceramic Resonator or
Crystal
LC
External Clock
Figure 23. Oscillator Configuration
34
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Counter/Timers. There are two 8-bit programmable
counter/timers (T1,T0), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources. However, the T0 prescaler is
driven by the internal clock only (Figure 24).
The counters can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters can
also be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(0 to 256) that has been loaded into the counter. When the
counter reaches the end of the count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated.
The counters, but not the prescalers, are read at any time
without disturbing their value or count mode. The clock
source for T1 is user-definable and is either the internal microprocessor clock divided by four, or an external signal input via Port 31. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input
that can be retriggerable or non-retriggerable, or as a gate
input for the internal clock. The counter/timers can be cascaded by connecting the T0 output to the input of T1.
DSP Clock
÷2
÷2
OSC
D7, D6
(F) OC
Internal Data Bus
(DSP CON)
T0, T2, T3
÷2
Write
D0,D1
(SMR)
Write
Read
PRE0
Initial Value
Register
T0
Initial Value
Register
6-Bit
Down
Counter
8-bit
Down
Counter
T0
Current Value
Register
÷ 16
÷4
Internal
Clock
IRQ4
TOUT
P36
÷2
External Clock
Clock
Logic
÷4
Internal Clock
Gated Clock
Triggered Clock
TIN P31
Write
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
Write
IRQ5
T1
Current Value
Register
Read
Internal Data Bus
Figure 24. Counter/Timer Block Diagram
DS97TAD0201
PRELIMINARY
35
1
Z89138/Z89139
Voice Processing Controllers
Zilog
Z8 FUNCTIONAL DESCRIPTION (Continued)
Port Configuration Register (PCON). The PCON register configures the comparator output on Port 3. The PCON
register (Figure 25) is located in the Expanded Register
File at Bank F, location 00H.
Comparator Output Port 3 (D0). Bit 0 controls the comparator use in Port 3. A 1 in this location brings the comparator outputs to P34 and P35, and a 0 releases the Port
to its standard I/O configuration.
Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VCC and
the oscillator circuit to stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one
of three conditions:
1. Power fail to Power OK status;
2. Stop-Mode Recovery (if D5 of SMR=1);
PCON (F) %00
D7 D6 D5 D4 D3 D2
3. WDT time-out.
D1 D0
R Always "1"
W 0 P34,P37 Standard output
1 P34,P37 Comparator output
R Always "1"
W No effect
The POR time is a nominal 5 ms. Bit 5 of the STOP Mode
register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock, RC/LC
oscillators).
Note: Reset condition is 11111110
Figure 25. Port Configuration Register (PCON)
Port 4 and 5 Configuration Register (P45CON). The
P45CON register configures Port 4 and Port 5, individually, to open-drain or push-pull active. This register is located
in the Expanded Register File at Bank F, location 06H.
Port 4 Open-Drain (D0). Port 4 can be configured as an
open-drain by resetting this bit (D0 = 0) or configured as
push-pull active by setting this bit (D0 = 1). The default value is 1.
Port 5 Open-Drain (D4). Port 5 can be configured as an
open-drain by resetting this bit (D4 = 0) or configured as
push-pull active by setting this bit (D4 = 1). The default value is 1.
36
HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The devices are recovered by interrupts, either externally or internally generated.
STOP. This instruction turns off the internal clock and external crystal oscillation. It reduces the standby current to
20 µA or less. The STOP Mode is terminated by a reset
only, either by WDT time-out, POR, SMR, or external reset. This causes the processor to restart the application
program at address 000CH. In order to enter STOP (or
HALT) Mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction.
To do this, the user must execute a NOP (opcode=FFH)
immediately before the appropriate Sleep instruction. For
example:,
FF
6F
NOP
STOP
FF
7F
NOP
HALT
PRELIMINARY
; clear the pipeline
; enter STOP Mode
or
; clear the pipeline
; enter HALT Mode
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Stop-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 26). All bits are Write-Only
except bit 7, which is Read-Only. Bit 7 is a flag bit that is
hardware set on the condition of STOP recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or
a high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4, or the
SMR register, specify the source of the Stop-Mode Recovery signal. Bits 0 and 1 determine the time-out period of the
WDT. The SMR is located in Bank F of the Expanded Register group at address 0BH.
SMR (FH) 0BH
D7 D6 D5 D4 D3 D2 D1 D0
W 0 SCLK/TCLK not divided by 16†
1 SCLK/TCLK divided by 16
R Always "1"
Reserved
W 000
001
010
011
100
101
R
POR only*
No effect
P31
P32
P33
Half second timeout from
33 kHz ext. osc.
110 P2 NOR 0-3
111 P2 NOR 0-7
Always "1"
W
0
1
R
Stop Delay
OFF
ON*
Always "1"
W 0 Low Stop Recovery Level*
1 High Stop Recovery Level
R Always "1"
* Default Setting After Reset
† Reset After Stop-Mode Recovery
W No effect
R 0 POR*
1 Stop-Mode Recovery
Figure 26. Stop-Mode Recovery Register (SMR)
DS97TAD0201
PRELIMINARY
37
1
Z89138/Z89139
Voice Processing Controllers
Zilog
Z8 FUNCTIONAL DESCRIPTION (Continued)
SCLK/TCLK divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
control) and/or HALT Mode (where TCLK sources
counter/timers and interrupt logic).
Stop-Mode Recovery Source (D4-D2). These three bits
of the SMR specify the wake-up source of the Stop-Mode
Recovery (Figure 27 and Table 8).
SMR D4 D3 D2
0 0 0
SMR D4 D3 D2 SMR D4 D3 D2
0 1 0
1 0 0
0 1 1
VDD
P31
P32
P33
SMR D4 D3 D2
1 0 1
SMR D4 D3 D2
1 1 0
P20
P20
P23
P27
SMR D4 D3 D2
1 1 1
HSEC
To POR
RESET
Stop Mode Recovery Edge
Select (SMR)
To P33 Data
Latch and IRQ1
MUX
P33 From Pads
Digital/Analog Mode
Select (P3M)
Figure 27. Stop-Mode Recovery Source
Table 8. Stop-Mode Recovery Source
SMR:432
D4
D3
D2
Operation
Description of Action
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
POR and/or external reset recovery
No effect
P31 transition
P32 transition
P33 transition
HSEC
Logical NOR of P20 through P23
Logical NOR of P20 through P27
38
Stop-Mode Recovery Delay Select (D5). When Low, this
bit disables the 5 ms /RESET delay after Stop-Mode Recovery. The default configuration of this bit is 1. If the “fast”
wake up is selected, the Stop-Mode Recovery source is
kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6). A 1 in this bit position indicates that a high level on any one of the recovery
sources wakes the Z89138/139 from STOP Mode. A 0 indicates low level recovery. The default is 0 on POR (Table
8).
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP Mode. It is active High, and is 0 (cold)
on POR/WDT /RESET. This bit is Read-Only. It is used to
distinguish between a cold or warm start.
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
DSP Control Register (DSPCON). The DSPCON register
controls various aspects of the Z8 and the DSP. It can configure the internal system clock (SCLK) or the Z8, /RE-
SET, and HALT of the DSP, and control the interrupt interface between the Z8 and the DSP (Table 9).
1
Table 9. DSP Control Register (F) OCH [Read/Write]
Field
DSPCON (F)0CH
Position
Attrib
Value
Z8_SCLK
76------
R/W
00
01
1x
DSP_Reset
--5-----
R
W
DSP_Run
---4----
R/W
Reserved
----32--
W
R
DSP_INT2
------1-
R
W
Z8_IRQ3
0
1
0
1
1
0
R
W
-------0
Z8 IRQ3 (D0). When read, this bit indicates the status of
the Z8 IRQ3. The Z8 IRQ3 is set by the DSP by writing to
D9 of DSP External Register 4 (ICR). By writing a 1 to this
bit, Z8 IRQ3 is Reset.
DSP INT2 (D1). This bit is linked to DSP INT2. Writing a 1
to this bit sets the DSP INT2. Reading this bit indicates the
status of the DSP INT2.
1
0
Label
(OSC/8)
(OSC/4)
(OSC/2)
Return “0”
No effect
Reset DSP
Halt_DSP
Run_DSP
No effect
Return “0”
No effect
FB_DSP_INT2
Set DSP_INT2
No effect
FB_Z8_IRQ3
Clear IRQ3
No effect
DSP RESET (D5). Setting this bit to 1 will reset the DSP.
If the DSP was in HALT Mode, this bit is automatically preset to 1. Writing a 0 has no effect.
Z8 SCLK (D7-D6). These bits define the SCLK frequency
of the Z8. The oscillator can be divided by 8, 4, or 2. After
a reset, both bits default to 00.
DSP RUN (D4). This bit defines the HALT Mode of the
DSP. If this bit is set to 0, then the DSP clock is turned off
to minimize power consumption. After this bit is set to 1,
then the DSP will continue code execution from where it
was halted. After a hardware reset, this bit is reset to 1.
DS97TAD0201
PRELIMINARY
39
Z89138/Z89139
Voice Processing Controllers
Zilog
Z8 FUNCTIONAL DESCRIPTION (Continued)
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is initially enabled by
executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT circuit
is driven by an on-board RC oscillator or external oscillator
from the XTAL1 pin. The POR clock source is selected
with bit 4 of the WDT register (Figure 28). The WDTMR
register is accessible only within 64 Z8 clock cycles after
POR.
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP
00
01*
10
11
INT RC OSC
5 ms
15 ms
25 ms
100 ms
EXTERNAL CLOCK
256 Tpc
512 Tpc
1024 Tpc
4096 Tpc
WDT During HALT
0 OFF
1 ON*
WDT During STOP
0 OFF
1 ON*
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
* Default setting after RESET
W No effect
R Always "1"
Figure 28. Watch-Dog Timer Mode Register
Half-Second Timer Status Register (HSEC). The halfsecond timer status register (Figure 29) is a free-running
timer clocked by the external 32.768 kHz crystal. In normal
operation mode, every half-second, the timer will time-out
and set bit 0 (D0) of the HSEC register to 1. The user can
reset this bit for real timing. In Stop mode, this timer can be
used as a Stop-Mode Recovery source. Every half-second, the timer will recover the Stop mode and bit 0 of the
HSEC register will be set to 1. Therefore, in STOP Mode,
the user can keep real time.
HSEC (F) 0E
D7 D6 D5 D4 D3 D2 D1 D0
R
1 Half second time-out
0 No time-out
W 1 No effect
0 RESET the half second timer bit
Reserved R "0"
W No effect
Figure 29. Half-Second Timer Status Register
40
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
WDT Time Select (D0, D1). These bits selects the WDT
time period. The configuration is shown in Table 10.
WDT During HALT (D2). This bit determines whether or
not the WDT is active during HALT Mode. A 1 indicates active during HALT. The default is 1.
Table 10. WDT Time Select
D1
D0‘
Time-out of
Internal RC OSC
0
0
1
1
0
1
0
1
5 ms min
15 ms min
25 ms min
100 ms min
Time-out of
XTAL Clock
256 TpC
512 TpC
1024 TpC
4096 TpC
Notes:
TpC = XTAL clock cycle.
Tolerance = ±10%
/RESET
4 Clock
Filter
Clear
CLK
WDT During STOP (D3). This bit determines whether or
not the WDT is active during STOP Mode. Since XTAL
clock is stopped during STOP Mode, the on-board RC
must be selected as the clock source to the POR counter.
A 1 indicates active during STOP. The default is 1.
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configuration of this bit is 0 which selects the RC oscillator.
18 Clock RESET
Generator
RESET
Internal
RESET
WDT Select
(WDTMR)
WDT TAP SELECT
CK Source
Select
(WDTMR)
XTAL
RC
OSC.
VDD
2V REF.
From Stop
Mode
Recovery
Source
+
-
M
U
X
5 ms POR 5 ms 15 ms 25 ms 100 ms
CK
WDT/POR Counter Chain
CLR
2V Operating
Voltage Det.
12 ns Glitch Filter
WDT
Stop Delay
Select (SMR)
Figure 30. Resets and WDT
DS97TAD0201
PRELIMINARY
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Voice Processing Controllers
Zilog
DSP REGISTERS DESCRIPTION
General. The DSP is a high-performance second generation CMOS Digital Signal Processor with a modified Harvard-type architecture with separate program and data
ports. The design has been optimized for processing power and saving silicon space.
Registers. The DSP has eight internal registers and seven external registers. The external registers are for the A/D
and D/A converters, and the mailbox and interrupt interfacing between DSP to the Z8. External registers are accessed in one machine cycle, the same as internal registers.
DSP Registers
There are 15 internal and extended 16-bit registers which
are defined in Table 11.
Table 11. DSP Registers
Register
Attribute
Register Definition
BUS
X
Y
A
SR
SP
PC
P
EXT0
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
Read
Write
Read
Write
Read
Write
Read
Write
Read/Write
Read
Write
Read/Write
Data-Bus
X Multiplier Input, 16-Bit
Y Multiplier Input, 16-Bit
Accumulator, 24-Bit
Status Register
Stack Pointer
Program Counter
Output of MAC, 24-Bit
Z8 ERF Bank B, Register 00-01 (from Z8)
Z8 ERF Bank B, Register 08-09 (to Z8)
Z8 ERF Bank B, Register 02-03 (from Z8)
Z8 ERF Bank B, Register 0A-0B (to Z8)
Z8 ERF Bank B, Register 04-05 (from Z8)
Z8 ERF Bank B, Register 0C-0D (to Z8)
Z8 ERF Bank B, Register 06-07 (from Z8)
Z8 ERF Bank B, Register 0E-0F (to Z8)
DSP Interrupt Control Register
A/D Converter
D/A Converter
Analog Control Register
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT3-EXT0 (External Registers 3-0). These are the Mailbox Registers used by the DSP and Z8 to communicate.
These four 16-bit registers correspond to the eight outgoing and eight incoming 8-bit registers in Bank B of the Z8’s
Expanded Register File.
EXT5 (D/A and A/D Data Register). This register is used
by both D/A and A/D converters. The D/A converter is
loaded by writing to this register, while the A/D converter is
addressed by reading from this register. The Register
EXT5 is accessible only by the DSP.
EXT4 (DSP Interrupt Control Register (ICR)). This register
controls the interrupts in the DSP as well as the interrupts
in common between the DSP and the Z8. It is accessible
by the DSP only, except for bit F and bit 9.
EXT6 (Analog Control Register). This register controls the
D/A and A/D converters. It is a read/write register accessible only by the DSP.
42
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
DSP Z8 Mail Box
To receive information from the DSP, the Z8 uses eight incoming registers which are mapped in the Z8 extended
Register File (Bank B, 08 to 0F). The DSP treats these as
four 16-bit registers that correspond to the eight incoming
Z8 registers (Figure 31).
The Z8 can supply the DSP with data through eight outgoing registers mapped into both the Z8 Expanded Register
File (Bank B, Registers 00 to 07) and the external register
interface of the DSP. These registers are Read/Write and
can be used as general-purpose registers of the Z8. The
DSP can only read information from these registers. Since
the DSP uses a 16-bit data format and the Z8 an 8-bit data
format, eight outgoing registers of the Z8 correspond to
four DSP registers. The DSP can only read information
from the outgoing registers.
Both the outgoing registers and the incoming registers
share the same DSP address (EXT3-EXT0).
Note: The Z8 can read and write to ERF Bank B R00-R07,
Registers 08-0F are Read-Only from the Z8.
Outgoing Registers
(B)00, (B)01
(B)02, (B)03
EXT0
(B)04, (B)05
(B)06, (B)07
EXT2
EXT1
EXT3
Incoming Registers
Z8 Data Bus
EXT1
EXT2
(B)0C, (B)0D
(B)0E, (B)0F
(F)0C
EXT3
DSP Interrupt Control Register
EXT4
D/A and A/D Data Registers
EXT5
DSP Data Bus
EXT0
(B)08, (B)09
(B)0A, (B)0B
D7, D1
D9
D2
Analog Control Register
EXT6
Figure 31. Z8-DSP Interface
Table 12. Z8 Outgoing Registers (Read-Only from DSP)
Field
Outgoing [0]
Outgoing [1]
Outgoing [2]
Outgoing [3]
Outgoing [4]
Outgoing [5]
Outgoing [6]
Outgoing [7]
(B)00
(B)01
(B)02
(B)03
(B)04
(B)05
(B)06
(B)07
DS97TAD0201
Position
Attrib
Value
76543210
76543210
76543210
76543210
76543210
76543210
76543210
76543210
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
%NN
%NN
%NN
%NN
%NN
%NN
%NN
%NN
PRELIMINARY
Label
(B)00/DSP_ext0_hi
(B)01/DSP_ext0_lo
(B)02/DSP_ext1_hi
(B)03/DSP_ext1_lo
(B)04/DSP_ext2_hi
(B)05/DSP_ext2_lo
(B)06/DSP_ext3_hi
(B)07/DSP_ext3_lo
43
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Z89138/Z89139
Voice Processing Controllers
Zilog
DSP REGISTERS DESCRIPTION (Continued)
Table 13. Z8 Incoming Registers (Write-Only from DSP)
Field
Position
Attrib
Value
Incoming [8] (B)08
76543210
%NN
Incoming [9] (B)09
76543210
Incoming [a] (B)0A
76543210
Incoming [b] (B)0B
76543210
Incoming [c] (B)0C
76543210
Incoming [d] (B)0D
76543210
Incoming [e] (B)0E
76543210
Incoming [f] (B)0F
76543210
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
%NN
%NN
%NN
%NN
%NN
%NN
%NN
Label
DSP_ext0_hi
No Effect
DSP_ext0_lo
No Effect
DSP_ext1_hi
No Effect
DSP_ext1_lo
No Effect
DSP_ext2_hi
No Effect
DSP_ext2_lo
No Effect
DSP_ext3_hi
No Effect
DSP_ext3_lo
No Effect
Table 14. DSP Incoming Registers
Field
DSP_ext0
Mail Box
DSP_ext1
Mail Box
DSP_ext2
Mail Box
DSP_ext3
Mail Box
44
Position
Attrib
Value
fedcba9876543210
R
W
R
W
R
W
R
W
%NNNN
fedcba9876543210
fedcba9876543210
fedcba9876543210
PRELIMINARY
%NNNN
%NNNN
%NNNN
Label
(B)00, (B)01
(B)08, (B)09
(B)02, (B)03
(B)0A, (B)0B
(B)04, (B)05
(B)0C, (B)0D
(B)06, (B)07
(B)0E, (B)0F
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
DSP Interrupts
and INT0, respectively (Figure 34). The DSP does not allow interrupt nesting (interrupting service routines that are
currently being executed). When two interrupt requests occur simultaneously the DSP starts servicing the interrupt
with the highest priority level.
The DSP processor has three interrupt sources (INT2,
INT1, INT0) (Figure 32). These sources have different priority levels (Figure 33). The highest priority, the next lower
and the lowest priority level are assigned to INT2, INT1
INT2
INT2
Z8_INT
A/D INT
Interrupt Priority Logic
INT1
Interrupt Request Logic
Interrupt Mask Logic
INT0
D/A INT
IPR2
INT1
INT0
CLEAR_INT0
IPR1
CLEAR_INT1
IPR0
CLEAR_INT2
FB DSP
FeedBack Z8_INT MPX
ENABLE_INT
Figure 32. DSP Interrupts
INT0
INT1
INT2
DSP Execution
INT2
INT0
INT1
INT2
Figure 33. DSP Interrupt Priority Structure
Z8 Side
DSP Side
On the Z8, set D1 to
interrupt DSP via DSP INT2.
DSP INT2
DSP CON
1
After serving IRQ3,
set D0 to clear the
interrupt request.
0
9
After serving INT2,
set D4 to clear the
interrupt request.
ICR
(EXT4)
4
The DSP sets D9 to
interrupt Z8 via Z8 IRQ3.
IRQ3 of the Z8
Figure 34. Interprocessor Interrupts Structure
DS97TAD0201
PRELIMINARY
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Z89138/Z89139
Voice Processing Controllers
Zilog
DSP REGISTERS DESCRIPTION (Continued)
Table 15. EXT4 DSP Interrupt Control Register (ICR) Definition
Field
Position
Attrib
Value
1
0
DSP_IRQ2
f---------------
R
DSP_IRQ1
f---------------e--------------
W
R
DSP_IRQ0
-e---------------d-------------
W
R
DSP_MaskINT2
--d---------------c------------
W
R/W
DSP_MaskINT1
----b-----------
R/W
DSP_MaskINT0
-----a----------
R/W
Z8_IRQ3
------9--------------9---------
R
W
DSPintEnable
-------8--------
R/W
DSP_IPR2
DSP_IPR1
DSP_IPR0
Clear_IRQ2
--------7---------------6---------------5---------------4--------------4----
R/W
R/W
R/W
R
W
------------3--------------3---
R
W
-------------2--------------2--
R
W
--------------10
W
R
Clear_IRQ1
Clear_IRQ0
Reserved
46
PRELIMINARY
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Binary
Binary
Binary
1
0
1
0
1
0
Label
Set_IRQ2
Reset_IRQ2
No effect
Set_IRQ1
Reset_IRQ1
No effect
Set_IRQ0
Reset_IRQ0
No effect
Enable_INT2
Disable_INT2
Enable_INT1
Disable_INT1
Enable_INT0
Disable_INT0
Return "0"
Set_Z8_IRQ3
Reset_Z8_IRQ3
Enable
Disable
IPR2
IPR1
IPR0
Return "0"
Clear_IRQ2
Has_no_effect
Return "0"
Clear_IRQ1
No effect
Return "0"
Clear_IRQ0
No effect
No effect "0"
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Interrupt Control Register (ICR). The ICR is mapped into
EXT4 of the DSP (Table 15). The bits are defined as follows:
DSP_IRQ2 (Z8 Interrupt). This bit is read by both Z8 and
DSP and is set only by writing to the Z8 expanded Register
File (Bank F, ROC, bit 0). This bit asserts IRQ2 of the DSP
and is cleared by writing to the Clear_IRQ2 bit.
DSP_IRQ1 (A/D Interrupt). This bit is read by the DSP only
and is set when valid data is present at the A/D output register (conversion done). This bit asserts IRQ1 of the DSP
and is cleared by writing to the Clear_IRQ1bit.
DSP_IRQ0 (D/A Interrupt). This bit is read by DSP only
and is set by Timer3. This bit assists IRQ0 of the DSP and
is cleared by writing to the Clear_IRQ0 bit.
DSP_MaskIntX. These bits are accessed by the DSP
only. Writing a 1 to these locations allows the INT to be
serviced, while writing a 0 masks off the corresponding
INT.
Z8_IRQ3. This bit can be read by both the Z8 and the DSP
but can only be set by the DSP. Addressing this location
accesses bit D3 of the Z8 IRQ register, hence, this bit is
not implemented in the ICR. During the interrupt service
routine executed on the Z8 side, the User must reset the
Z8_IRQ3 bit by writing a 1 to bit D0 of the DSPCON.
The hardware of the Z89138/139 automatically resets
Z8_IRQ3 bit three instructions of the Z8 after 1 is written to
its location in register bank 0F. This delay provides the timing synchronization between the Z8 and the DSP sides
during interrupts. In summary, the interrupt service routine
of the Z8 for IRQ3 should be finished by:
LD
OR
POP
IRET
;
;
;
;
RP,#%0F
r12,#%01
RP
DSP Enable_INT. Writing a 1 to this location enables global interrupts of the DSP while writing 0 disables them. A
system Reset globally disables all interrupts.
DSP_IPRX. This three-bit group defines the Interrupt Selection logic as shown in Table 16.
Clear_IRQX. These bits are accessed by the DSP only.
Writing a 1 to these locations resets the corresponding
DSP_IRQX bits to 0. Clear_IRQX are virtual bits and are
not implemented.
Table 16. DSP Interrupt Selection
DSP_IPR[2-0]
2 1 0
Z8_INT is
switched to
A/D_INT is
switched to
D/A_INT is
switched to
000
001
010
011
100
101
110
111
INT2
INT1
INT2
INT1
INT0
INT0
Reserved
Reserved
INT1
INT2
INT0
INT0
INT2
INT1
Reserved
Reserved
INT0
INT0
INT1
INT2
INT1
INT2
Reserved
Reserved
DS97TAD0201
PRELIMINARY
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Z89138/Z89139
Voice Processing Controllers
Zilog
DSP Analog Data Registers
A/D supplies 8-bit data to the DSP through the register
EXT5 of the DSP. From the 16 bits of EXT5, only bits 2
through 9 are used by the A/D (Figure 36). Bits 0 and 1 are
padded with zeroes.
The D/A conversion is DSP driven by sending 10-bit data
to the EXT5 of the DSP. The six remaining bits of EXT5 are
not used (Figure 35).
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Reserved
10-Bit Data for D/A
(Write Only)
Reserved
Figure 35. EXT5 Register D/A Mode Definition
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Reserved
8-Bit Data From A/D Converter
(Read Only)
Reserved
Figure 36. EXT5 Register A/D Mode Definition
48
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
ANALOG CONTROL REGISTER (ACR)
The Analog Control register is mapped to register EXT6 of
the DSP (Table 17). This read/write register is accessible
by the DSP only.
The 16-bit field of EXT6 defines modes of both the A/D and
the D/A. The High Byte configures the D/A while the Low
Byte controls the A/D mode.
Table 17. EXT6 Analog Control Register (ACR)
Field
Position
Attrib
Value
MPX_DSP_INT0
f---------------
R/W
1
0
Reserved
-edcba----------
R
W
Return “0”
No effect
Reserved
------9---------
R
W
Return “1”
No effect
D/A_SamplingRate-------8--------
R/W
DSP_port (DSP1, --------76-----DSP0)
R/W
Enable A/D
----------5-----
R/W
ConversionDone
-----------4----
W
R
StartConversion
------------3---
R/W
Reserved
-------------2--
R
W
Label
20.48
MHz
29.49
MHz*
16 kHz
10 kHz
8.04 kHz
9.6 kHz
16 kHz
8 kHz
16 kHz
9.6 kHz
P26
Timer3
0
1
User-defined DSP
outputs
1
0
A/D Enabled
A/D Disabled
1
0
No effect
Done
Not Done
1
0
Start
Wait Timer
Return “0”
No effect
20/29 MHz Select --------------1-
R/W
1
0
A/D_SamplingRate---------------0
R/W
1
0
29.49 MHz*
20.48 MHz†
Notes:
* Default value
† Optional feature
DS97TAD0201
PRELIMINARY
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Z89138/Z89139
Voice Processing Controllers
Zilog
DSP IRQ0. This bit defines the source of the DSP IRQ0 interrupt.
D/A_Sampling Rate. This field defines the sampling rate
of the D/A output. It changes the period to Timer3 interrupt
and the maximum possible accuracy of the D/A Sampling
Rate (Table 18).
Table 18. D/A Data Accuracy
D/A_Sampling Rate
Bit 8
0
1
Conversion Done. This Read-Only flag indicates that the
A/D conversion is complete. Upon reading EXT5 (A/D data), the Conversion Done flag is cleared.
Start A/D Conversion. Writing a 1 to this location immediately starts one conversion cycle. If this bit is reset to 0 the
input data is converted upon successive Timer2 time-outs.
A hardware reset forces this bit to 1.
Sampling Rate
20.48 MHz
29.49 MHz
16 kHz
10 kHz
Enable A/D. Writing a 0 to this location disables the A/D
converter, a 1 will enable it. A hardware reset forces this
bit to 0.
8.04 kHz
9.6 kHz
DSP0. DSP0 is a general-purpose output pin connected to
Bit 6. This bit has no special significance and can be used
to output data by writing to bit 6.
DSP1. DSP1 is a general-purpose output pin connected to
Bit 7. This bit has no special significance and can be used
to output data by writing to bit 7.
A/D_Sampling Rate. This field defines the sampling rate
of the A/D. It changes the period of Timer2 interrupt (Table
19).
Table 19. A/D Sampling Rate
A/D_Sampling Rate
Bit 0
1
0
Sampling Rate
20.48 MHz
29.49 MHz
16 kHz
8 kHz
16 kHz
9.6 kHz
DSP TIMERS
Timer2 is a free running counter that divides the XTAL frequency (20.48 MHz) to support different sampling rates for
the A/D converter. The sampling rate is defined by the Analog Control Register. Upon reaching the end of a count,
the timer generates an interrupt request to the DSP.
Analogous to Timer2, Timer3 generates the different sampling rates for the D/A converter. Timer3 also generates an
interrupt request to the DSP upon reaching its final count
value (Figure 37).
Timer2
8, 16 kHz
A/D
Timer3
16, 10 kHz
D/A
Timer2
16, 9.6 kHz
A/D
Timer3
8.04, 9.6 kHz
D/A
OSC
20.48 MHz
USC
29.49 MHz
Figure 37. Timer2 and Timer3
50
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Pulse Width Modulator (PWM)
The PWM supports two different sampling rates (10 and 16
kHz), according to the settings of bit 8 of the ACR. The output of the PWM can be assigned to logic 1 only during the
active region (which is 4/5 of the output signal period). The
output will be at logic 0 for the rest of the time. An exception occurs in 10 kHz PWM, where the active region covers
the whole output signal period (Figure 39). The active region is divided into 1024 time slots. In each of these time
slots, the output can be set to logic 1 or logic 0.
slot of each of the 32 groups represents Low_Val, while
High_Val is represented by the remaining 31 time slots in
each group.
For example, a value of %13a is loaded into PWM data
register EXT 5:
%13a = 01 0011 1010B = 314
High_Val = 01001B = 9
Low_Val = 11010B = 26
In order to increase the effective sampling rate, the PWM
employs a special technique of distributing the “logic 1” period over the active region.
The 10-bit PWM data is divided into two parts: the upper
five bits (High_Val) and the lower five bits (Low_Val). The
1024 time slots in the active region are divided into 32
equal groups, with 32 time slots in each group. The first
26 out of 32 groups will then have their first slots set to logic 1. The remaining one slot in each group has nine time
slots set to logic 1.
For 10 kHz PWM, the effective output frequency is 10K x
32 = 320 kHz. Figure 40 illustrates the waveform by using
a 6-bit PWM data (3-bit High_Val and 3-bit Low_Val).
250 µs
10 kHz
100 µs
16 kHz
Figure 38. PWM Waveform (shaded area shows the active region)
DS97TAD0201
PRELIMINARY
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Z89138/Z89139
Voice Processing Controllers
Zilog
Figure 39. PWM Waveform of the Active Region
(for a 6-bit PWM data)
52
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DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
A/D CONVERTER (ADC)
Analog to Digital Converter
The A/D converter is an 8-bit half flash converter which
uses two reference resistor ladders for its upper four bits
(MSBs) and lower four bits (LSBs) conversion (Figure 40).
Two reference voltage pins, VREF+ (High) and VREF(Low), are provided for external reference voltage supplies. During the sampling period, the converter is auto-ze-
roed before starting the conversion time depending on the
external clock frequency and the selection of the A/D sampling rate (Figure 40). The sampling rates are 10 or 16 kHz
(XTAL = 20.48 MHz) in order to provide oversampling. The
rates are software controlled by the ACR (DSP External
Register 6). Timer2 supports the ADC. The maximum conversion time is 2 µs.
AN IN
4-Bit
Flash
Sample
4-Bit
DAC
Auto Zero m
4 MSB
–
4-Bit
Flash
+
4 LSB
Auto Zero
Latch 4 MSB
Latch 4 LSB
Bits 9-2 Register 12 of DSP
Figure 40. A/D Converter
Conversion begins by writing to the appropriate bit in the
Analog Control Register (ACR). The start commands are
implemented in such a way as to begin a conversion at any
time. If a conversion is in progress and a new start command is received, then the conversion in progress is aborted and a new conversion initiated. This allows the programmed values to be changed without affecting a
conversion in progress. The new values take effect only after a new start command is received.
DS97TAD0201
The ADC can be disabled (for low power) or enabled by an
analog Control Register bit.
Though the ADC functions for a smaller input voltage and
voltage reference, the noise and offsets remain constant
over the specified electrical range. The errors of the converter will increase and the conversion time can also take
slightly longer due to smaller input signals.
PRELIMINARY
53
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Z89138/Z89139
Voice Processing Controllers
1
1
2
3
Zilog
4
5
6
7
8
9
10
11
26
27
28
29
30
31
32
SCLK
P32
Input Sample
A/D Result
DSP INT
DSP Write
Notes:
1. SCLK = 10 MHz (XTAL =
20.48 MHz)
Figure 41. ADC Timing Diagram
Figure 42 shows the input circuit of the ADC. When conversion starts, the analog input voltage from the input is
connected to the MSB and LSB flash converter inputs as
shown in the Input Impedance CKT diagram. Shunting 31
parallel internal resistances of the analog switches and simultaneously charging 31 parallel 1 pF capacitors is equivalent to a 400 Ohms input impedance in parallel with a 31
pF capacitor. Other input stray capacitance adds about 10
pF to the input load. Input source resistances up to 2 kOhms can be used under normal operating conditions without any degradation of the input settling time. For larger input source resistance, longer conversion cycle times can
be required to compensate the input settling time problem.
VREF is set using the VREF + pin.
CMOS Switch
on Resistance
2-5kΩ
V Ref
R Source
C .5 pF
V Ref
C .5 pF
C Parasitic
V Ref
31 CMOS Digital
Comparators
C .5 pF
Figure 42. Input Impedance of ADC
54
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Z8 EXPANDED REGISTER FILE REGISTERS
Expanded Register Bank B
1
(B) 04
D7 D6 D5 D4 D3 D2 D1 D0
(B) 00
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT2,
Bits D15-D8
DSP EXT0,
Bits D15-D8
Figure 43. Outgoing Register to DSP EXT0
(High Byte) (B) 00H [Read/Write]
Figure 47. Outgoing Register to DSP EXT2
(High Byte)
(B) 04H [Read/Write]
(B) 05
(B) 01
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT2,
Bits D7-D0
DSP EXT0,
Bits D7-D0
Figure 44. Outgoing Register to DSP EXT0
(Low Byte)
(B) 01H [Read/Write]
Figure 48. Outgoing Register to DSP EXT2
(Low Byte)
(B) 05H [Read/Write]
(B) 06
(B) 02
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT3,
Bits D15-D8
DSP EXT1,
Bits D15-D8
Figure 45. Outgoing Register to DSP EXT1
(High Byte)
(B) 02H [Read/Write]
Figure 49. Outgoing Register to DSP EXT3
(High Byte)
(B) 06H [Read/Write]
(B) 03
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT1,
Bits D7-D0
Figure 46. Outgoing Register to DSP EXT1
(Low Byte)
(B) 03H [Read/Write]
DS97TAD0201
PRELIMINARY
55
Z89138/Z89139
Voice Processing Controllers
Zilog
(B) 07
(B) 0B
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT3,
Bits D7-D0
DSP EXT1,
Bits D7-D0
Figure 50. Outgoing Register to DSP EXT3
(Low Byte)
(B) 07H [Read/Write]
(B) 08
Figure 54. Incoming Register from DSP EXT1
(Low Byte)
(B) 0BH [Read-Only]
(B) 0C
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT0,
Bits D15-D8
DSP EXT2,
Bits D15-D8
Figure 51. Incoming Register from DSP EXT0
(High Byte)
(B) 08H [Read-Only]
(B) 09
Figure 55. Incoming Register from DSP EXT2
(High Byte)
(B) 0CH [Read-Only]
(B) 0D
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT0,
Bits D7-D0
DSP EXT2,
Bits D7-D0
Figure 52. Incoming Register from DSP EXT0
(Low Byte)
(B) 09H [Read-Only]
(B) 0A
Figure 56. Incoming Register from DSP EXT2
(Low Byte)
(B) 0DH [Read-Only]
(B) 0E
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT1,
Bits D15-D8
DSP EXT3,
Bits D15-D8
Figure 53. Incoming Register from DSP EXT1
(High Byte)
(B) 0AH [Read-Only]
56
Figure 57. Incoming Register from DSP EXT3
(High Byte)
(B) 0EH [Read-Only]
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
(B) 0F
P5D (FH) 04H
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT3,
Bits D7-D0
1
Data
Figure 58. Incoming Register from DSP EXT3
(Low Byte)
(B) 0FH [Read-Only]
Expanded Register Bank F
Figure 62. Port 5 Data Register
(F) 04H [Read/Write]
P5M (FH) 05H
D7 D6 D5 D4 D3 D2 D1 D0
PCON (F) %00
D7 D6 D5 D4 D3 D2
P50-P57 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input*
Returns "FF" Upon Read
D1 D0
R Always "1"
W 0 P34,P37 Standard output
1 P34,P37 Comparator output
* Default setting after Reset
R Always "1"
W No effect
Figure 63. Port 5 Mode Register
(F) 05H [Write-Only]
Note: Reset condition is 11111110
Figure 59. Port Configuration Register (PCON)
(F) 00H [Write-Only]
P45M (FH) 06H
(Write only)
D7 D6 D5 D4 D3
P4D (FH) 02H
D2 D1 D0
Port 4 Configuration Bit
0 Open-Drain
1 Push-pull
D7 D6 D5 D4 D3 D2 D1 D0
No effect
Data
Port 5 Configuration Bit
0 Open-Drain
1 Push-pull
No effect
Figure 60. Port 4 Data Register
(F) 02H [Read/Write]
Figure 64. Port 4 and 5 Configuration Register
(F) 06H [Write-Only]
P4M (FH) 03H
D7 D6 D5 D4 D3 D2 D1 D0
P40-P47 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input
Returns "FF" Upon Read
Figure 61. Port 4 Mode Register
(F) 03H [Write-Only]
DS97TAD0201
PRELIMINARY
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Z89138/Z89139
Voice Processing Controllers
Zilog
SMR (FH) 0BH
D7 D6 D5 D4 D3 D2 D1 D0
W 0 SCLK/TCLK not divided by 16†
1 SCLK/TCLK divided by 16
R Always "1"
Reserved
W 000
001
010
011
100
101
R
POR only*
No effect
P31
P32
P33
Half second timeout from
33 kHz ext. osc.
110 P2 NOR 0-3
111 P2 NOR 0-7
Always "1"
W
0
1
R
Stop Delay
OFF
ON*
Always "1"
W 0 Low Stop Recovery Level*
1 High Stop Recovery Level
R Always "1"
* Default Setting After Reset
† Reset After Stop-Mode Recovery
W No effect
R 0 POR*
1 Stop-Mode Recovery
Figure 65. Stop-Mode Recovery Register (SMR)
(F) 0BH [Read/Write]
58
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
Table 20. DSP Control Register (F) 0CH [Read/Write]
Field
DSPCON (F) 0CH
Position
Attributes
Value
00
01
1x
Z8_SCLK
76------
R/W
DSP_Reset
--5-----
R
W
DSP_Run
---4----
Reserved
----32--
IntFeedback
R
W
------1-
Return “0”
No effect
FB_DSP_INT2
Set DSP_INT2
No effect
FB_Z8_IRQ3
Clear IRQ3
No effect
1
0
R
W
-------0
OSC/8
OSC/4
OSC/2
Return “0”
No effect
Reset DSP
Halt_DSP
Run_DSP
0
1
0
1
xx
R/W
1
Label
1
0
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP
00
01*
10
11
INT RC OSC
5 ms
15 ms
25 ms
100 ms
EXTERNAL CLOCK
256 Tpc
512 Tpc
1024 Tpc
4096 Tpc
WDT During HALT
0 OFF
1 ON*
WDT During STOP
0 OFF
1 ON*
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
* Default setting after RESET
W No effect
R Always "1"
Figure 66. Watch-Dog Timer Mode Register
(F) 0FH [Read/Write]
DS97TAD0201
PRELIMINARY
59
Z89138/Z89139
Voice Processing Controllers
Zilog
Z8 CONTROL REGISTERS
R243 PRE1
R240
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0 T1 Single Pass
1 T1 Modulo N
RESERVED
Clock Source
1 T1Internal
0 T1External Timing Input
(TIN) Mode
Figure 67. Reserved (F0H)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R241 TMR
D7 D6 D5 D4
D3 D2 D1 D0
Figure 70. Prescaler 1 Register
(F3H: Write-Only)
0 No Function
1 Load T0
0 Disable T0 Count
1 Enable T0 Count
R244 T0
0 No Function
1 Load T1
D7 D6 D5 D4 D3 D2
D1
D0
0 Disable T1 Count
1 Enable T1 Count
T0 Low Byte Initial Value
(When Written)
TIN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
T0 Low Byte Current Value
(When Read)
TOUT Modes
00 Not Used
01 T0 Out
10 T1 Out
11 Internal Clock Out (P36)
Figure 71. Counter/Timer 0 Register
(F4H: Read/Write)
R243 PRE1
Figure 68. Timer Mode Register
(F1H: Read/Write)
D7 D6 D5
D0
Count Mode
0 T1 Single Pass
1 T1 Modulo N
R242 T1
D7 D6 D5 D4
Clock Source
1 T1Internal
0 T1External Timing Input
(TIN) Mode
D3 D2 D1 D0
T1 Low Byte Initial Value
(When Written)
T1 Low Byte Current Value
(When Read)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
Figure 72. Prescaler 0 Register
(F5H: Write-Only)
Figure 69. Counter/Timer 1 Register
(F2H: Read/Write)
60
D4 D3 D2 D1
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
R248 P01M
R246 P2M
D7 D6 D5 D4
1
D7 D6 D5 D4 D3 D2 D1 D0
D3 D2 D1 D0
P00 - P03 Mode
00 Output
01 Input *
1X A11 - A8
P20 - P27 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input *
* Default Setting After Reset
Stack Selection
0 External
1 Internal *
P10 - P17 Mode
00 Byte Output
01 Byte Input *
10 AD7 - AD0
11 High-Impedance AD7 - AD0,
/AS, /DS, /R//W, A11 - A8,
A15 - A12, If Selected
Figure 73. Port 2 Mode Register
(F6H: Write-Only)
R247 P3M
D7 D6 D5 D4 D3 D2 D1
External Memory Timing
0 Normal *
1 Extended
D0
0 Port 2 Pull-Ups Open Drain *
1 Port 2 Pull-Ups Active
* Default Setting After Reset
0 P31, P32 Digital Mode *
1 P31, P32 Analog Mode
0 P32 = Input *
P35 = Output *
1 P32 = /DAV0/RDY0
P35 = RDY0//DAV0
P04 - P07 Mode
00 Output
01 Input *
1X A15 - A12
Figure 75. Port 0 Mode Register
(F8H: Write-Only)
00 P33 = Input *
P34 = Output *
01 P33 = Input
P34 = /DM
10 P33 = Input
P34 = /DM
11 P33 = /DAV1/RDY1
P34 = RDY1//DAV1
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
0 P31 = Input (TIN) *
P36 = Output (TOUT) *
1 P31 = /DAV2/RDY2
P36 = RDY2//DAV2
0 P30 = Input
P37 = Output
Reserved
* Default Setting After Reset
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
Figure 74. Port 3 Mode Register
(F7H: Write-Only)
Reserved
Figure 76. Interrupt Priority Register
(F9H: Write-Only)
DS97TAD0201
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61
Z89138/Z89139
Voice Processing Controllers
Zilog
Z8 CONTROL REGISTERS (Continued)
R250 IRQ
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4
Expanded Register File Bank
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = DSP
IRQ4 = T0
IRQ5 = T1
Inter Edge
P31 ↓ P32 ↓ = 00
P31 ↓ P32 ↑ = 01
P31 ↑ P32 ↓ = 10
P31 ↑↓ P32 ↑↓ = 11
D3 D2 D1 D0
Working Register Group
Figure 80. Register Pointer
(FDH: Read/Write)
R254 SPH
D7 D6 D5 D4 D3 D2 D1 D0
Figure 77. Interrupt Request Register
(FAH: Read/Write)
Stack Pointer Upper
Byte (SP8 - SP15)
R251 IMR
Figure 81. Stack Pointer High
(FEH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ0-IRQ5
(D0 = IRQ0)
1 Enables RAM Protect
1 Enables Interrupts
R255 SPL
D7 D6 D5
D4 D3 D2 D1
D0
Stack Pointer Lower
Byte (SP0 - SP7)
Figure 78. Interrupt Mask Register
(FBH: Read/Write)
Figure 82. Stack Pointer Low
(FFH: Read/Write)
R252 FLAGS
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
Figure 79. Flag Register
(FCH: Read/Write)
62
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DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
PACKAGE INFORMATION
1
Figure 83. 100-Pin QFP Package Diagram
Figure 84. 100-Pin VQFP Package Diagram
DS97TAD0201
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Z89138/Z89139
Voice Processing Controllers
Zilog
ORDERING INFORMATION
Z89138 (20 MHz)
100-Pin QFP
100-Pin VQFP
Z8913820FSC
Z8913820ASC
Z89139 (20 MHz)
100-Pin QFP
100-Pin VQFP
Z8913920FSC
Z8913920ASC
Z89138 (29 MHz)
100-Pin QFP
100-Pin VQFP
Z8913829FSC
Z8913829ASC
Z89139 (29 MHz)
100-Pin QFP
100-Pin VQFP
Z8913929FSC
Z8913929ASC
For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.
CODES
Packages
F = Quad Flatpack (QFP)
A = Very Small Quad Flatpack (VQFP)
Speeds
20 = 20.48 MHz
29 = 29.49 MHz
Temperature
S = 0°C to + 55°C
Environmental
C = Plastic Standard
Example:
Z 89138 20 F S C
is a Z89138, 20.48 MHz, QFP, 0°C to +55°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
64
PRELIMINARY
DS97TAD0201
Z89138/Z89139
Voice Processing Controllers
Zilog
1
© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc.
makes no warranty, express, statutory, implied or by
description, regarding the information set forth herein or
regarding the freedom of the described devices from
intellectual property infringement. Zilog, Inc. makes no
warranty of merchantability or fitness for any purpose.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
DS97TAD0201
Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
PRELIMINARY
65
Z89138/Z89139
Voice Processing Controllers
66
Zilog
PRELIMINARY
DS97TAD0201