CUB DL82 R Austria Mikro Systeme International 0.6 µm CMOS DL82 is a transparent D-latch with 2x drive strength. The Q output follows the D input when GN is low. The Q output is independent of D when GN is high and retains the value of D just prior to the rising edge on GN. Truth Table D GN L H X L L H Q Capacitance QN L H Ci (pF) D H L Q D GN DL82 0.013 0.023 no change GN QN Area Power 0.95 mils2 4.61 µW / MHz Delay [ns] = tpd.. = f(SL, L) Output Slope [ns] = op_sl.. = f(L) AC Characteristics : Tj = 25°C with SL = Input Slope [ns] ; L = Output Load [pF] with L = Output Load [pF] VDD = 3.3V Typical Process AC Characteristics SL = 0.1 Characteristics Symbol Delay D to Q SL = 2.0 L = 0.2 L = 1.4 L = 2.0 L = 0.2 L = 1.4 L = 2.0 tpddqr tpddqf 1.02 1.27 2.48 2.59 3.19 3.16 1.11 1.45 2.57 2.76 3.26 3.33 Delay D to QN tpddqnr tpddqnf 1.72 1.47 3.10 2.62 3.75 3.17 1.89 1.57 3.27 2.71 3.91 3.26 Delay GN to Q tpdgnqr tpdgnqf 1.25 1.57 2.71 2.89 3.41 3.46 1.55 1.86 3.01 3.19 3.71 3.76 Delay GN to QN tpdgnqnr tpdgnqnf 2.04 1.71 3.43 2.86 4.13 3.45 2.34 2.02 3.72 3.17 4.44 3.73 Output Slope D to Q op_sldqr op_sldqf 1.07 1.01 5.30 4.05 7.32 5.30 1.08 1.00 5.27 4.02 7.28 5.32 Output Slope D to QN op_sldqnr op_sldqnf 1.01 0.78 5.13 3.78 7.25 5.45 0.96 0.78 5.18 3.77 7.20 5.41 Output Slope GN to Q op_slgnqr op_slgnqf 1.03 0.98 5.13 4.01 7.50 5.32 1.05 1.00 5.28 3.98 7.33 5.73 Output Slope GN to QN op_slgnqnr op_slgnqnf 1.00 0.76 5.15 3.81 7.25 5.42 1.00 0.75 5.11 3.80 7.38 5.50 Sept. 1996 - 140 - Rev. N/C DL82 R Austria Mikro Systeme International Characteristics Min D Setup Time to GN Min GN Width Sept. 1996 CUB Symbol [ns] Low tsudgnh tsudgnl 0.74 0.92 Low twgn 0.96 High - 141 - 0.6 µm CMOS Characteristics Min D Hold Time to GN Rev. N/C High Low Symbol [ns] thdgnh thdgnl 0.00 0.00