bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 1K-BIT SERIAL EPROM WITH SDQ INTERFACE FEATURES • • • • • • • The bq2022A SDQ™ interface requires only a single connection and a ground return. The DATA pin is also the sole power source for the bq2022A. The bus architecture allows multiple SDQ devices to be connected to a single host. 1024 bits of One-Time Programmable (OTP) EPROM For Storage Of User-Programmable Configuration Data Factory-Programmed Unique 64-Bit Identification Number Bus-Interface Architecture Allowing Multiple bq2022As Attached to a Single Host Single-Wire Interface to Reduce Circuit Board Routing Synchronous Communication Reduces Host Interrupt Overhead No Standby Power Required Available in a 3-Pin SOT23 Package and TO-92 Package The small surface-mount package options saves printed-circuit-board space, while the low cost makes it ideal for applications such as battery pack configuration parameters, record maintenance, asset tracking, product-revision status, and access-code security. ORDERING INFORMATION(1) PACKAGED DEVICES(3) (2) TA –20°C to 70°C APPLICATIONS • • • • PART NUMBER PACKAGE bq2022ADBZR SOT23-3 bq2022ALPR TO-92 STATUS PREVIEW (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com Security Encoding Inventory Tracking Product-Revision Maintenance Battery-Pack Identification (2) Device specified to communicate at –40°C to 85°C (3) The device is available only in tape and reel with a base quantity of 3000 units for the bq2022ADBZR and 2000 units for the bq2022ALPR. DESCRIPTION The bq2022A is a 1K-bit serial EPROM containing a factory-programmed, unique 48-bit identification number, 8-bit CRC generation, and the 8-bit family code (09h). A 64-bit status register controls write protection and page redirection. BLOCK DIAGRAM DBZ PACKAGE (TOP VIEW) SDQ SDQ VSS 1 SDQ Communications Controller and 8-Bit CRC Generation Circuit Internal Bus bq2022A RAM Buffer (8 bytes) EPROM STATUS (64 bits) VSS 3 ID ROM (64 bits) VSS EPROM MEMORY (1024 bits) 2 1 2 LP PACKAGE (BOTTOM VIEW) 3 VSS 1 VSS 2 SDQ 3 NC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SDQ is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT VPU DC voltage applied to data IOL Low-level output current –0.3 V to 7 V 40 mA ESD IEC 61000-4-2 Air discharge Data to VSS, VSS to data TA Operating free-air temperature range TA(Comm) Communication free-air temperature range Tstg Storage temperature range 15 kV –20°C to 70°C Communication is specified by design –40°C to 85°C –55°C to 125°C Lead temperature (soldering, 10 s) (1) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS TA = –20°C to 70°C; VPU(min) = 2.65 VDC to 5.5 VDC, all voltages relative to VSS PARAMETER IDATA Supply current TEST CONDITION MIN TYP MAX VPU = 5.5 V 20 Logic 0, VPU = 5.5 V, IOL = 4 mA, SDQ pin 0.4 Logic 0, VPU = 2.65 V, IOL = 2 mA 0.4 VOL Low-level output voltage VOH High-level output voltage Logic 1 IOL Low-level output current (sink) VOL = 0.4 V, SDQ pin VIL Low-level input voltage Logic 0 VIH High-level input voltage Logic 1 VPP Programming voltage VPU UNIT µA V 5.5 4 0.8 2.2 mA V V 11.5 12 V AC SWITCHING CHARACTERISTCS TA = –20°C to 70°C; VPU(min) = 2.65 VDC to 5.5 VDC, all voltages relative to VSS PARAMETER MIN MAX UNIT 60 120 µs 1 15 µs tWSTRB 15 µs tc µs Bit cycle time (1) tWSTRB Write start cycle tWDSU Write data setup (1) tWDH Write data hold (1) (2) 60 trec Recovery time (1) tRSTRB Read start cycle (1) tODD Output data delay (1) tODHO Output data hold tRST Reset time (1) tPPD Presence pulse delay (1) tPP Presence pulse tEPROG EPROM programming time tPSU tPREC (1) (2) 2 TEST CONDITION tc (1) TYP 1 For memory command only (1) µs 5 1 13 µs tRSTRB 13 µs 17 60 µs µs 480 (1) 15 60 µs 60 240 µs 2500 µs Program setup time 5 µs Program recovery time 5 µs 5-kΩ series resistor between SDQ pin and VPU. (See Figure 1) tWDH must be less than tc to account for recovery. Submit Documentation Feedback bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 AC SWITCHING CHARACTERISTCS (continued) TA = –20°C to 70°C; VPU(min) = 2.65 VDC to 5.5 VDC, all voltages relative to VSS PARAMETER TEST CONDITION MIN TYP MAX UNIT tPRE Program rising-edge time 5 µs tPFE Program falling-edge time 5 µs tRSTREC 480 µs Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION bq2022ADBZR SDQ 1 I Data VSS 2, 3 - Ground bq2022ALPR VSS 1 - GND SDQ 2 I Data NC 3 - No connection FUNCTIONAL DESCRIPTION GENERAL OPERATION The block diagram on page 1 shows the relationships among the major control and memory sections of the bq2022A. The bq2022A has three main data components: a 64-bit factory-programmed ROM, including 8-bit family code, 48-bit identification number and 8-bit CRC value, 1024-bit EPROM, and EPROM STATUS bytes. Power for read and write operations is derived from the DATA pin. An internal capacitor stores energy while the signal line is high and releases energy during the low times of the DATA pin, until the pin returns high to replenish the charge on the capacitor. A special manufacturer's PROGRAM PROFILE BYTE can be read to determine the programming profile required to program the part. 1024-BIT EPROM Table 1 is a memory map of the 1024-bit EPROM section of the bq2022A, configured as four pages of 32 bytes each. The 8-byte RAM buffers are additional registers used when programming the memory. Data are first written to the RAM buffer and then verified by reading an 8-bit CRC from the bq2022A that confirms proper receipt of the data. If the buffer contents are correct, a programming command is issued and an 8-byte segment of data is written into the selected address in memory. This process ensures data integrity when programming the memory. The details for reading and programming the 1024-bit EPROM portion of the bq2022A are in the Memory Function Commands section of this data sheet. Table 1. 1024-Bit EPROM Data Memory Map ADDRESS(HEX) PAGE 0060-007F Page 3 0040-005F Page 2 0020-003F Page 1 0000-001F Page 0 Submit Documentation Feedback 3 bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 EPROM STATUS MEMORY In addition to the programmable 1024-bits of memory are 64 bits of status information contained in the EPROM STATUS memory. The STATUS memory is accessible with separate commands. The STATUS bits are EPROM and are read or programmed to indicate various conditions to the software interrogating the bq2022A. The first byte of the STATUS memory contains the write protect page bits, that inhibit programming of the corresponding page in the 1024-bit main memory area if the appropriate write-protection bit is programmed. Once a bit has been programmed in the write protect page byte, the entire 32-byte page that corresponds to that bit can no longer be altered but may still be read. The write protect bits may be cleared by using the WRITE STATUS command. The next four bytes of the EPROM STATUS memory contain the page address redirection bytes. Bits in the EPROM status bytes can indicate to the host what page is substituted for the page by the appropriate redirection byte. The hardware of the bq2022A makes no decisions based on the contents of the page address redirection bytes. This feature allows the user's software to make a data patch to the EPROM by indicating that a particular page or pages should be replaced with those indicated in the page address redirection bytes. The ones complement of the new page address is written into the page address redirection byte that corresponds to the original (replaced) page. If a page address redirection byte has an FFh value, the data in the main memory that corresponds to that page are valid. If a page address redirection byte has some other hex value, the data in the page corresponding to that redirection byte are invalid, and the valid data can now be found at the ones complement of the page address indicated by the hexadecimal value stored in the associated page address redirection byte. A value of FDh in the redirection byte for page 1, for example, indicates that the updated data are now in page 2. The details for reading and programming the EPROM status memory portion of the bq2022A are given in the Memory Function Commands section. Table 2. EPROM Status Bytes ADDRESS (HEX) PAGE 00h Write protection bits BIT0 - write protect page 0 BIT1 - write protect page 1 BIT2 - write protect page 2 BIT3 - write protect page 3 BIT4 to 7 - bitmap of used pages 01h Redirection byte for page 0 02h Redirection byte for page 1 03h Redirection byte for page 2 04h Redirection byte for page 3 05h Reserved 06h Reserved 07h Factory programmed 00h Error Checking To validate the data transmitted from the bq2022A, the host generates a CRC value from the data as they are received. This generated value is compared to the CRC value transmitted by the bq2022A. If the two CRC values match, the transmission is error-free. The equivalent polynomial function of this CRC is X8 + X5 + X4 + 1. Details are found in the CRC Generation Section of this data sheet. Customizing the bq2022A The 64-bit ID identifies each bq2022A. The 48-bit serial number is unique and programmed by Texas Instruments. The default 8-bit family code is 09h; however, a different value can be reserved on an individual customer basis. Contact your Texas Instruments sales representative for more information. Bus Termination Because the drive output of the bq2022A is an open-drain, N-channel MOSFET, the host must provide a source current or a 5-kΩ external pullup, as shown in the typical application circuit in Figure 1. 4 Submit Documentation Feedback bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 VPU SDQ 1 Communications Controller 3 VSS VSS CPU 2 bq2022A HOST Figure 1. Typical Applications Circuit Serial Communication A host reads, programs, or checks the status of the bq2022A through the hierarchical command structure of the SDQ interface. Figure 2 shows that the host must first issue a ROM command before the EPROM memory or status can be read or modified. The ROM command either selects a specific device when multiple devices are on the SDQ bus, or skips the selection process in single SDQ device applications. Initialization ROM Command Sequence Memory/Status Command Sequence Figure 2. General Command Sequence Initialization Initialization consists of two pulses, the RESET and the PRESENCE pulses. The host generates the RESET pulse, while the bq2022A responds with the PRESENCE pulse. The host resets the bq2022A by driving the DATA bus low for at least 480 µs. For more details, see the RESET section under SDQ Signaling. ROM COMMANDS READ ROM The READ ROM command sequence is the fastest sequence that allows the host to read the 8-bit family code and 48-bit identification number. It is used if only one SDQ slave device is attached to the bus. The READ ROM sequence starts with the host generating the RESET pulse of at least 480 µs. The bq2022A responds with a PRESENCE pulse. Next, the host continues by issuing the READ ROM command, 33h, and then reads the ROM and CRC byte using the READ signaling (see the READ and WRITE signals section) during the data frame. Reset and Presence Signals 1 1 Read ROM (33h) 0 0 1 1 0 0 Family Code and Identification Number (7 BYTES) CRC (1 BYTE) Figure 3. READ ROM Sequence Submit Documentation Feedback 5 bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 MATCH ROM The MATCH ROM command, 55h, is used by the host to select a specific SDQ device when the family code and identification number is known. The host issues the MATCH ROM command followed by the family code, ROM number, and the CRC byte. Only the device that matches the 64-bit ROM sequence is selected and available to perform subsequent Memory/Status Function commands. Reset and Presence Signals 1 0 Match ROM (55h) 1 0 1 0 1 Family Code and Identification Number (7 BYTES) 0 CRC (1 BYTE) Figure 4. MATCH ROM Sequence SEARCH ROM The SEARCH ROM command, F0h, is used to obtain the 8-bit family code and the 48-bit identification number and 8-bit CRC of any SDQ device when it is unknown. All devices on the bus are read under the SEARCH ROM command with the use of a collision-detect and device-decode method. Figure 5 shows the SEARCH ROM sequence started by the host, generating the RESET pulse of at least 480 µs. The bq2022A responds with a PRESENCE pulse. The host then issues the command in the command frame by writing an F0h. During the DATA READ of the SEARCH ROM sequence, each bit is transmitted three times. The bq2022A transmits the bit followed by the complement of the bit. The host in turn retransmits the bit just read. Collision detection is performed by comparing the bit and bit complement time-slots. If they are both zero, this indicates that a collision has occurred, indicating multiple devices on the bus. The device decode is achieved in the third transmission of the bit from the host back to the bq2022A. If the bit transmitted by the host does not match the bit transmitted by the bq2022A, then the device with mismatch stops transmitting. Devices that did match, continue transmitting. This process is continued until all bits of a single device are read. The SEARCH ROM command is reissued and the process is repeated to read additional devices. NOTE: NOTE: If the number of devices on the bus is unknown, the SEARCH ROM command should be used. Reset and Presence Signals Data Read Search ROM (F0h) 0 0 0 0 1 1 1 1 A. B = bit(n): nth bit transmitted by bq2022A B. C = bit(n): complement of nth bit transmitted by bq2022A C. H = bit(n): nth bit transmitted by host BIT0 Figure 5. SEARCH ROM Sequence 6 Submit Documentation Feedback BITn BIT63 bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 SKIP ROM This SKIP ROM command, CCh, allows the host to access the memory/status functions without issuing the 64-bit ROM code sequence. The SKIP ROM command is directly followed by a memory/status functions command. Because this command can cause bus collisions when multiple SDQ devices are on the same bus, this command should be issued in single device applications. Reset and Presence Signals Skip ROM (CCh) 0 1 0 1 0 1 0 1 Figure 6. SKIP ROM Sequence MEMORY/STATUS FUNCTION COMMANDS Six memory/status function commands allow read and modification of the 1024-bit EPROM data memory or the 64-bit EPROM status memory. There are two types of READ MEMORY command, plus the WRITE MEMORY, READ STATUS, and WRITE STATUS commands. Additionally, the part responds to a PROGRAM PROFILE byte command. The bq2022A responds to memory/status function commands only after a part is selected by a ROM command. READ DATA MEMORY COMMANDS Two READ MEMORY commands are available on the bq2022A. Both commands are used to read data from the 1024-bit EPROM data field. They are the READ MEMORY/Page CRC and the READ MEMORY/Field CRC commands. The READ MEMORY/Page CRC generates CRC at the end any 32-byte page boundary whereas the READ MEMORY/Field CRC generates CRC when the end of the 1024-bit data memory is reached. READ MEMORY/Page CRC To read memory and generate the CRC at the 32-byte page boundaries of the bq2022A, the ROM command is followed by the READ MEMORY/Generate CRC command, C3h, followed by the address low byte and then the address high byte. An 8-bit CRC of the command byte and address bytes is computed by the bq2022A and read back by the host to confirm that the correct command word and starting address were received. If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the host issues read time slots and receives data from the bq2022A starting at the initial address and continuing until the end of a 32-byte page is reached. At that point, the host sends eight additional read time slots and receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte to the last byte of the current page. Once the 8-bit CRC has been received, data is again read from the 1024-bit EPROM data field starting at the next page. This sequence continues until the final page and its accompanying CRC are read by the host. Thus each page of data can be considered to be 33 bytes long, the 32 bytes of user-programmed EPROM data and an 8-bit CRC that gets generated automatically at the end of each page. Initialization and ROM Command Sequence READ MEMORY/Generate CRC Command C3h Address Low Byte Address High Byte A0 A7 A8 A15 Read and Verify CRC EPROM Memory and CRC Byte Generated at 32-Byte Page Boundaries NOTE: Individual bytes of address and data are transmitted LSB first. Figure 7. READ MEMORY/Page CRC Submit Documentation Feedback 7 bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 READ MEMORY/Field CRC To read memory without CRC generation on 32-byte page boundaries, the ROM command is followed by the READ MEMORY command, F0h, followed by the address low byte and then the address high byte. NOTE: As shown in Figure 8, individual bytes of address and data are transmitted LSB first. An 8-bit CRC of the command byte and address bytes is computed by the bq2022A and read back by the host to confirm that the correct command word and starting address were received. If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the host issues read time slots and receives data from the bq2022A starting at the initial address and continuing until the end of the 1024-bit data field is reached or until a reset pulse is issued. If reading occurs through the end of memory space, the host may issue eight additional read time slots and the bq2022A responds with an 8-bit CRC of all data bytes read from the initial starting byte through the last byte of memory. After the CRC is received by the host, any subsequent read time slots appear as logical 1s until a reset pulse is issued. Any reads ended by a reset pulse prior to reaching the end of memory does not have the 8-bit CRC available. Initialization and ROM Command Sequence READ MEMORY Command F0h Read EPROM Address High Read and Memory Until End Byte Verify CRC of EPROM Memory A7 A8 A15 Address Low Byte A0 Read and Verify CRC Figure 8. READ MEMORY/Field CRC WRITE MEMORY The WRITE MEMORY command is used to program the 1024-bit EPROM memory field. The 1024-bit memory field is programmed in 8-byte segments. Data is first written into an 8-byte RAM buffer one byte at a time. The contents of the RAM buffer is then ANDed with the contents of the EPROM memory field when the programming command is issued. Figure 9 illustrates the sequence of events for programming the EPROM memory field. After issuing a ROM command, the host issues the WRITE MEMORY command, 0Fh, followed by the low byte and then the high byte of the starting address. The bq2022A calculates and transmits an 8-bit CRC based on the WRITE command and address. If at any time during the WRITE MEMORY process, the CRC read by the host is incorrect, a reset pulse must be issued, and the entire sequence must be repeated. After the bq2022A transmits the CRC, the host then transmits 8 bytes of data to the bq2022A. Another 8-bit CRC is calculated and transmitted based on the 8 bytes of data. If this CRC agrees with the CRC calculated by the host, the host transmits the program command 5Ah and then applies the programming voltage for at least 2500 µs or tEPROG. The contents of the RAM buffer is then logically ANDed with the contents of the 8-byte EPROM offset by the starting address. The starting address can be any integer multiple of eight between 0000 and 007F (hex) such as 0000, 0008, and 0010 (hex). The WRITE DATA MEMORY command sequence can be terminated at any point by issuing a reset pulse except during the program pulse period tPROG. NOTE: The bq2022A responds with the data from the selected EPROM address sent least significant-bit first. This response should be checked to verify the programmed byte. If the programmed byte is incorrect, then the host must reset the part and begin the write sequence again. 8 Submit Documentation Feedback bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 For both of these cases, the decision to continue programming is made entirely by the host, because the bq2022A is not able to determine if the 8-bit CRC calculated by the host agrees with the 8-bit CRC calculated by the bq2022A. Prior to programming, bits in the 1024-bit EPROM data field appear as logical 1s. Write Memory Command? (0Fh) Selected State N Selected State Y Bus Master Transmits Low Byte Address (LSB First) AD0 to AD7 Bus Master Transmits High Byte Address (LSB First) AD8 to AD15 bq2022A Loads Address Into Address Counter bq2022A Transmits CRC of Write Command and Address, then Clears CRC Register bq2022A Receives 8 Bytes of Data and Stores in RAM Buffer bq2022A Transmits CRC of Previous Received 8 Bytes of Data N Code 5Ah Received Y Voltage on Data Pin = VPP N Y Contents of RAM buffer AND’ed with contents of data memory offset by address counter and stored in data memory offset by address counter . programming time required to be at least t EPROG when VPP Vdc on data pin bq2022A Increments Address Counter and Transmits 1 Byte of Data Memory Indexed by Address Counter bq2022A 8th Byte Transmitted Transmits 1 Byte of Data Memory at Address Counter N Y bq2022A Waits for Reset (No Further Response) NOTE: Individual bytes of address and data are transmitted LSB first Figure 9. WRITE MEMORY Command Flow Submit Documentation Feedback 9 bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 READ STATUS The READ STATUS command is used to read data from the EPROM status data field. After issuing a ROM command, the host issues the READ STATUS command, AAh, followed by the address low byte and then the address high byte. NOTE: An 8-bit CRC of the command byte and address bytes is computed by the bq2022A and read back by the host to confirm that the correct command word and starting address were received. If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the host issues read time slots and receives data from the bq2022A starting at the supplied address and continuing until the end of the EPROM Status data field is reached. At that point, the host receives an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte through the final factory-programmed byte that contains the 00h value. This feature is provided because the EPROM status information may change over time making it impossible to program the data once and include an accompanying CRC that is always valid. Therefore, the READ status command supplies an 8-bit CRC that is based on (and always is consistent with) the current data stored in the EPROM status data field. After the 8-bit CRC is read, the host receives logical 1s from the bq2022A until a reset pulse is issued. The READ STATUS command sequence can be ended at any point by issuing a reset pulse. Initialization and ROM Command Sequence READ MEMORY Command AAh Read STATUS Address High Read and Memory Until End Byte Verify CRC of STATUS Memory A7 A8 A15 Address Low Byte A0 Read and Verify CRC Figure 10. READ STATUS Command WRITE STATUS The Write Status command is used to program the EPROM Status data field after the bq2022A has been selected by a ROM command The flow chart in Figure 11 illustrates that the host issues the Write Status command, 55h, followed by the address low byte and then the address high byte the followed by the byte of data to be programmed. NOTE: Individual bytes of address and data are transmitted LSB first. An 8-bit CRC of the command byte, address bytes, and data byte is computed by the bq2022A and read back by the host to confirm that the correct command word, starting address, and data byte were received. If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the program command (5Ah) is issued. After the program command is issued, then the programming voltage, VPP is applied to the DATA pin for period tPROG. Prior to programming, the first seven bytes of the EPROM STATUS data field appear as logical 1s. For each bit in the data byte provided by the host that is set to a logical 0, the corresponding bit in the selected byte of the EPROM STATUS data field is programmed to a logical 0 after the programming pulse has been applied at the byte location. The eighth byte of the EPROM STATUS byte data field is factory-programmed to contain 00h. 10 Submit Documentation Feedback bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 Write Status Command? (55h) Selected State N Selected State Y bq2022A Receives Low Address Byte (LSB First) AD0 to AD7 bq2022A Receives High Address Byte (LSB First) AD8 to AD15 bq2022A Loads Address into Address Counter bq2022A Receives 1 Byte of Data and Stores in RAM Buffer bq2022A Transmits CRC of Write Status Command, Address, and Data bq2022A Calculates and Transmits CRC of Loaded Address and Shifted Data N Code 5Ah Received Y VDATA = VPP? N Y Contents of RAM buffer AND’ed with contents of data memory as pointed to by address counter . Programming time required to be at least t EPROG when VPP is applied to the data pin bq2022A Receives Data Byte bq2022A Increments Address Counter and Loads New Address into CRC Register bq2022A Transmits Data Byte of Status Memory Pointed to by Address Counter End of Status Memory? N Y bq2022A Waits for Reset Figure 11. WRITE STATUS Command Flow After the programming pulse is applied and the data line returns to VPU, the host issues eight read time slots to verify that the appropriate bits have been programmed. The bq2022A responds with the data from the selected EPROM STATUS address sent least significant bit first. This response should be checked to verify the Submit Documentation Feedback 11 bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 programmed byte. If the programmed byte is incorrect, then the host must reset the device and begin the write sequence again. If the bq2022A EPROM data byte programming was successful, the bq2022A automatically increments its address counter to select the next byte in the STATUS MEMORY data field. The least significant byte of the new two-byte address is also loaded into the 8-bit CRC generator as a starting value. The host issues the next byte of data using eight write time slots. As the bq2022A receives this byte of data into the RAM buffer, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address and the result is an 8-bit CRC of the new data byte and the LSB of the new address. After supplying the data byte, the host reads this 8-bit CRC from the bq2022A with eight read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be restarted. If the CRC is correct, the host issues a programming pulse and the selected byte in memory is programmed. NOTE: The initial write of the WRITE STATUS command, generates an 8-bit CRC value that is the result of shifting the command byte into the CRC generator, followed by the two-address bytes, and finally the data byte. Subsequent writes within this WRITE STATUS command due to the bq2022A automatically incrementing its address counter generates an 8-bit CRC that is the result of loading (not shifting) the LSB of the new (incremented) address into the CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue programming the EPROM Status registers is made entirely by the host, because the bq2022A is not able to determine if the 8-bit CRC calculated by the host agrees with the 8-bit CRC calculated by the bq2022A. If an incorrect CRC is ignored and a program pulse is applied by the host, incorrect programming could occur within the bq2022A. Also note that the bq2022A always increments its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The decision to continue is again made entirely by the host, therefore if the EPROM data byte does not match the supplied data byte but the master continues with the WRITE STATUS command, incorrect programming could occur within the bq2022A. The WRITE STATUS command sequence can be ended at any point by issuing a reset pulse. Table 3. Command Code Summary 12 COMMAND (HEX) DESCRIPTION 33h Read Serialization ROM and CRC 55h Match Serialization ROM F0h Search Serialization ROM CCh Skip Serialization ROM F0h Read Memory/Field CRC AAh Read EPROM Status C3h Read Memory/Page CRC 0Fh Write Memory 99h Programming Profile 55h Write EPROM Status 5Ah Program Control CATEGORY ROM Commands Available in Command Level I Memory Function Commands Available in Command Level II Program Command Available Only in WRITE MEMORY and WRITE STATUS Modes Submit Documentation Feedback bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 PROGRAM PROFILE BYTE The PROGRAM PROFILE byte is read to determine the WRITE MEMORY programming sequence required by a specific manufacturer. After issuing a ROM command, the host issues the PROGRAM PROFILE BYTE command, 99h. Figure 12 shows the the bq2022A responds with 55h. This informs the host that the WRITE MEMORY programming sequence is the one described in the WRITE MEMORY command section of this data sheet. From ROM Command Program Profile Command? 99h N Other Command Codes Y bq2022 Transmits 55h bq2022A is in Reset State Master Issues Reset Figure 12. PROGRAM PROFILE Command Flow SDQ SIGNALING All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, or to begin the start frame for a bit read. Figure 13 shows the initialization timing, whereas Figure 14 and Figure 15 show that the host initiates each bit by driving the DATA bus low for the start period, tWSTRB / tRSTRB. After the bit is initiated, either the host continues controlling the bus during a WRITE, or the bq2022A responds during a READ. RESET AND PRESENCE PULSE If the DATA bus is driven low for more than 120 µs, the bq2022A may be reset. Figure 13 shows that if the DATA bus is driven low for more than 480 µs, the bq2022A resets and indicates that it is ready by responding with a PRESENCE PULSE. VPU VIH VIL RESET (Sent by Host) t RST Presence Pulse (Sent by bq2022A) t PPD t PP t RSTREC Figure 13. Reset Timing Diagram WRITE The WRITE bit timing diagram in Figure 14 shows that the host initiates the transmission by issuing the tWSTRB portion of the bit and then either driving the DATA bus low for a WRITE 0, or releasing the DATA bus for a WRITE 1. Submit Documentation Feedback 13 bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 V PU Write ”1” V IH V IL Write ”0” t rec t WSTRB t WDSU t WDH Figure 14. Write Bit Timing Diagram READ The READ bit timing diagram in Figure 15 shows that the host initiates the transmission of the bit by issuing the tRSTRB portion of the bit. The bq2022A then responds by either driving the DATA bus low to transmit a READ 0 or releasing the DATA bus to transmit a READ 1. VPU Read ”1” V IH V IL Read ”0” t RSTRB t REC t ODD t ODHO Figure 15. Read Bit Timing Diagram PROGRAM PULSE VPP VPU tPSU tPFE tPRE tPREC tEPROG VSS Figure 16. Program Pulse Timing Diagram IDLE If the bus is high, the bus is in the IDLE state. Bus transactions can be suspended by leaving the DATA bus in IDLE. Bus transactions can resume at any time from the IDLE state. CRC Generation The bq2022A has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the bq2022A to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is: X8 + X5 + X4 +1. Under certain conditions, the bq2022A also generates an 8-bit CRC value using the same polynomial function just shown and provides this value to the bus master to validate the transfer of command, address, and data bytes from the bus master to the bq2022A. The bq2022A computes an 8-bit CRC for the command, address, and data bytes received for the WRITE MEMORY and the WRITE STATUS commands and then outputs this value to the bus master to confirm proper transfer. Similarly, the bq2022A computes an 8-bit CRC for the command and address bytes received from the bus master for the READ MEMORY, READ STATUS, and READ DATA/ GENERATE 8-BIT CRC commands to confirm that these bytes have been received correctly. The CRC generator on the bq2022A is also used to provide verification of error-free data transfer as each page of data from the 1024-bit EPROM is sent to the bus master during a READ DATA/GENERATE 8-BIT CRC command, and for the eight bytes of information in the status memory field. 14 Submit Documentation Feedback bq2022A www.ti.com SLUS724 – SEPTEMBER 2006 In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value using the polynomial function previously given and compare the calculated value to either the 8-bit CRC value stored in the 64-bit ROM portion of the bq2022A (for ROM reads) or the 8-bit CRC value computed within the bq2022A. The comparison of CRC values and decision to continue with an operation are determined entirely by the bus master. No circuitry on the bq2022A prevents a command sequence from proceeding if the CRC stored in or calculated by the bq2022A does not match the value generated by the bus master. Proper use of the CRC can result in a communication channel with a high level of integrity. CLK DAT Q D R Q D R Q D R Q D R + Q D + Q R D Q R D R Q D + R UDG-02065 8 5 4 Figure 17. 8-Bit CRC Generator Circuit (X + X + X + 1) Submit Documentation Feedback 15 PACKAGE OPTION ADDENDUM www.ti.com 24-Nov-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty BQ2022ADBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM BQ2022ADBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM BQ2022ALPR ACTIVE TO-92 LP 3 2000 Pb-Free (RoHS) Lead/Ball Finish CU SN MSL Peak Temp (3) N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 MECHANICAL DATA MSOT002A – OCTOBER 1994 – REVISED NOVEMBER 2001 LP (O-PBCY-W3) PLASTIC CYLINDRICAL PACKAGE 0.205 (5,21) 0.175 (4,44) 0.165 (4,19) 0.125 (3,17) DIA 0.210 (5,34) 0.170 (4,32) Seating Plane 0.157 (4,00) MAX 0.050 (1,27) C 0.500 (12,70) MIN 0.104 (2,65) FORMED LEAD OPTION 0.022 (0,56) 0.016 (0,41) 0.016 (0,41) 0.014 (0,35) STRAIGHT LEAD OPTION D 0.135 (3,43) MIN 0.105 (2,67) 0.095 (2,41) 0.055 (1,40) 0.045 (1,14) 1 2 3 0.105 (2,67) 0.080 (2,03) 0.105 (2,67) 0.080 (2,03) 4040001-2 /C 10/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Lead dimensions are not controlled within this area D. FAlls within JEDEC TO -226 Variation AA (TO-226 replaces TO-92) E. Shipping Method: Straight lead option available in bulk pack only. Formed lead option available in tape & reel or ammo pack. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOT002A – OCTOBER 1994 – REVISED NOVEMBER 2001 LP (O-PBCY-W3) PLASTIC CYLINDRICAL PACKAGE 0.539 (13,70) 0.460 (11,70) 1.260 (32,00) 0.905 (23,00) 0.650 (16,50) 0.610 (15,50) 0.020 (0,50) MIN 0.098 (2,50) 0.384 (9,75) 0.335 (8,50) 0.748 (19,00) 0.217 (5,50) 0.433 (11,00) 0.335 (8,50) 0.748 (19,00) 0.689 (17,50) 0.114 (2,90) 0.094 (2,40) 0.114 (2,90) 0.094 (2,40) 0.169 (4,30) 0.146 (3,70) DIA 0.266 (6,75) 0.234 (5,95) 0.512 (13,00) 0.488 (12,40) TAPE & REEL 4040001-3 /C 10/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Tape and Reel information for the Format Lead Option package. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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