A4490 Triple Output Step-Down Switching Regulator Features and Benefits Description ▪ Three buck converters ▪ 4.5 to 34 V input voltage range ▪ 550 kHz fixed frequency ▪ Multiphase switching ▪ Independent control of each converter ▪ Power-on-reset flag ▪ Internal compensation ▪ 4 × 4 mm QFN Package, small PCB footprint Designed to provide the power supply requirements of printers, office automation, industrial, and portable equipment, the A4490 provides three high current, high performance, switching regulator outputs with independent soft start. High frequency switching allows selection of inexpensive inductors and small ceramic output capacitors. The turn-on cycles of the regulators are interleaved to minimize stresses on the input capacitors and to reduce EMI. A charge pump is used to provide the supply for driving the power switches, ensuring operation at very wide operating duty cycles and avoiding the need for power-draining clamp circuits. A power-on-reset circuit with user configurable delay indicates when enabled regulators are in specification. The power-onreset flag also indicates when the input voltage drops below specification, giving the system controller advance warning while the switchers continue to operate down to the shutdown level. Package: 20-contact QFN (suffix ES) Internal diagnostics provide comprehensive protection against overloads, input undervoltages, and overtemperatures. Continued on the next page… Approximate size Typical Application VBB VDD CP1 CP2 PORZ VCP VBB1 LX1 CPOR Microcontroller or Controller Logic VREG1 A4490 ENB1 ENB2 FB1 VBB2 LX2 ENB3 VREG2 FB2 PGND GND VBB3 LX3 VREG3 FB3 4490-DS, Rev. 9 A4490 Triple Output Step-Down Switching Regulator Description (continued) The A4490 is provided in a 20-contact, 4 mm × 4 mm, 0.75 mm nominal overall height QFN, with exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating. Applications include the following: ▪ Photo, inkjet, and portable printers ▪ Industrial ▪ Hand-held devices ▪ Portable applications Selection Guide Part Number A4490EESTR-T Operating Temperature Range (°C) Packing 1500 pieces per 7-in. reel –40 to 85 Absolute Maximum Ratings (reference to GND) Characteristic Symbol Rating Units 36 V VLXn –1 to 36 V VIN –0.3 to 7 V 1 mA Load Supply Voltage VBB LX1, LX2, and LX3 Pins PORZ and VDD Pins ENBx Pin Input Current IENBx Notes Driven by a current-limited voltage source Operating Ambient Temperature TA –40 to 85 ºC Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC Storage Temperature Range E Recommended Operating Conditions Characteristic Symbol Conditions Min. Typ. Max. Units Load Supply Voltage VBB To operate at VBB < 6 V, connect VDD supply to the VBB supply. See Powering Configurations section. 4.5 – 34 V LX1, LX2, and LX3 Pins VLXn –0.7 – 34 V Operating Ambient Temperature TA –40 – 85 ºC Junction Temperature TJ –40 – 125 ºC Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* On 4-layer PCB based on JEDEC standard Value Units 37 ºC/W *Additional thermal information available on the Allegro website. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4490 Triple Output Step-Down Switching Regulator Functional Block Diagram C2 47 nF Regulator VDD CP2 C1 CP1 V BB Charge Pump VCP C3 100 nF 47 nF Switch V BB VBB1 V BB C4 Bias Supply 10 μF VCP LX1 100 kΩ ENB1 SS V REG1 L1 Switcher #1 PWM Control 5 V / 1.5 A 15 μH C5 D1 R1 10 μF FB1 R2 VBB2 C6 VCP L2 LX2 ENB2 SS V DD Switcher #2 PWM Control V REG2 10 μF 3.3 V / 1.5 A 10 μH C7 C8 10 μF 10 μF D2 R3 FB2 R4 PORZ POR Block C14 VBB3 C9 CPOR 10 μF VCP 470 nF LX3 ENB3 SS V REG3 1.0 V / 1.5 A L3 4.7 μH C10 C11 C12 C13 D3 Switcher #3 PWM Control 10 μF 10 μF 10 μF 10 μF R5 FB3 PGND GND R6 Note: All capacitors ceramic X5R. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4490 Triple Output Step-Down Switching Regulator 16 LX3 17 VBB3 18 VBB1 19 LX1 20 ENB1 Pin-out Diagram FB1 1 15 ENB3 VDD 2 14 FB3 GND 3 13 PGND FB2 4 12 CP1 ENB2 5 11 CP2 7 8 9 CPOR PORZ VCP 10 6 LX2 VBB2 PAD Terminal List Number Name 1 FB1 Feedback REG1 2 VDD Bias supply 3 GND1 Ground 4 FB2 5 ENB2 Function Feedback REG2 Enable REG2, logic input, active high 6 LX2 7 VBB22 Switch node REG2 Input supply for REG2 8 CPOR POR delay adjustment 9 PORZ Power on reset output, active low 10 VCP Charge pump reservoir 11 CP2 Charge pump capacitor terminal 12 CP1 Charge pump capacitor terminal 13 PGND1 14 FB3 15 ENB3 16 LX3 17 VBB32 Input supply for REG3 18 VBB12 Input supply for REG1 Ground for charge pump circuitry Feedback REG3 Enable REG3, logic input, active high Switch node REG3 19 LX1 20 ENB1 Switch node REG1 Enable REG1, logic input, active high – PAD3 Exposed pad for enhanced thermal dissipation 1GND and PGND should be connected externally. 2The three VBBx pins should be connected together externally. 3Thermal pad should be connected to the ground (0 V) plane using thermal vias. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4490 Triple Output Step-Down Switching Regulator ELECTRICAL CHARACTERISTICS1,2 at TA = 25°C, VBB = 6.0 to 34 V, VDD supplied externally, unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Unit – 1 2 mA General VBB Quiescent Current IBBON ENBx = high, ILOAD = 0 mA, VBB = 12 V, current drawn by feedback resistors ignored IBBOFF ENBx = 0 V VDD Supply Range VDD VDD Quiescent Current IDD – 1 – μA 3.3 – 5.5 V ENBx = high – – 5 mA ENBx = 0 V – 1 – μA –400 –100 100 nA – ±1.5 – % VREGx = 5 V, IOUT = 0 to 1.5 A, TA = –20°C to 85°C –2.5 – 2.5 % VREGx = 5 V, IOUT = 0 to 1.5 A, TA = –40°C to 85°C –3.5 – 3.5 % REG1, REG2, and REG3 Feedback Input Bias Current IBIAS Feedback Voltage VFB Output Voltage Regulation3 PWM Frequency VOUT With respect to 0.8 V target voltage fSW 470 550 630 kHz Maximum Duty Cycle Dmax 90 – – % Minimum Duty Cycle Dmin – 5 – % – 450 – mΩ TJ = 25°C, ILOAD = 1.5 A, VBB = 6.0 V Buck Switch On-Resistance RDS(on) TJ = 125°C, ILOAD = 1.5 A, VBB = 6.0 V – 700 – mΩ TJ = 25°C, ILOAD = 1.5 A, VBB = 4.5 V – 560 – mΩ TJ = 125°C, ILOAD = 1.5 A, VBB = 4.5 V – 870 – mΩ Current Limit Threshold ILIM Soft Start Duration tss 0.625 1.25 1.875 ms VIL – – 0.8 V Peak current through switch with D = 0.9 2.0 A Logic Inputs and Outputs ENBx Input Voltage ENBx Input Hysteresis ENBx Input Current VIH 2.0 – – V VI(hys) 300 500 – mV IIL VIH ≤ 5 V –1 – 1 μA PORZ Output (Open Drain) VPORZL IPORZL = 1 mA, fault asserted – – 0.4 V PORZ Output Leakage Current IPORZH VPORZ = 5 V, fault not asserted –1 – 1 μA CPOR = 470 nF 75 115 155 ms Power-On Reset Duration tPOR Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4490 Triple Output Step-Down Switching Regulator ELECTRICAL CHARACTERISTICS1,2 (continued) at TA = 25°C, VBB = 6.0 to 34 V, VDD supplied externally, unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Unit Protection VREGx Undervoltage Lockout Startup VREGUV(su) FB1, FB2, and FB3 rising – 85 – %VFB VREGx Undervoltage Lockout Shutdown VREGUV(sd) FB1, FB2, and FB3 falling – 80 – %VFB – 5 – % V VREGx Undervoltage Lockout Startup Hysteresis VBB Undervoltage Lockout Startup VBB Undervoltage Lockout Shutdown VBB Undervoltage Lockout Shutdown Hysteresis VBB Undervoltage Warning Threshold VREGUV(suhys) VBBUV(su) No external VDD supply, VBB rising 3.9 4.3 4.6 External VDD supply, VBB rising 3.9 4.2 4.4 V No external VDD supply, VBB falling 3.7 4.1 4.5 V VBBCPUV(sd) External VDD supply, VBB falling 3.0 3.5 4.1 V VBBUV(sdhys) No external VDD supply – 500 – mV VBBCPUV(su) VBBUV(sd) VBBCPUV(sdhys) External VDD supply VBBUV(por) Junction Overtemperature Shutdown TJTSD Junction Overtemperature Shutdown Hysteresis TJTSD(hys) – 600 – mV VBB falling (forces PORZ low); switchers continue to operate – 3.6 – V Temperature rising – 165 – °C Recovery = TJTSD –TJTSD(hys) – 15 – °C 1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified pin. over the junction temperature range of –40°C to 125°C are assured by design and characterization. 3Average value of V OUT relative to target voltage. The effects of the feedback resistors are not taken into account. 2Specifications Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4490 Triple Output Step-Down Switching Regulator Functional Description Basic Operation The A4490 contains three fixed frequency, buck switching converters with peak current-mode control, including slope compensation. Each converter can be independently turned on and off via the enable inputs (EN1, EN2, and EN3), which are active high. When enabled, the corresponding output is brought-up under the control of a soft start routine, which avoids output voltage overshoot and minimizes input inrush current. The output voltage is typically divided down by an external potential divider, and is compared against an internal reference voltage to produce an error signal, also known as the current demand signal. The current signal through the buck switch is converted into a voltage. This signal is then compared against the current demand signal to create the required duty cycle. At the beginning of each switching cycle, the buck switch is turned on. When the current signal through the switch reaches the level of the current demand signal, the on-time of the switch is terminated. On the next switching cycle, the switch is turned on again and the cycle is repeated. One shared clock is used to define the switching frequency for each regulator. Each of the three switching cycles (REG1, REG2, and REG3) are phase shifted with respect to one another by 120° in an attempt to minimize the pulsed current drawn from the input filter capacitors. Under certain conditions, for example at low VBB conditions and relatively high user-set output voltages, switching overlap between channels is inevitable. Under conditions, such as light loads or high VBB voltages, that cause duty cycles (DC) of less than the minimum value, the converter enters a pulse-skipping mode to ensure regulation is maintained. A charge pump regulator is provided to ensure a sufficient gate drive is available for all three power switches across the full input voltage range. This regulator allows operation even at very wide operating duty cycles. On initial power-up, an internal regulator is used to provide the bias supply for on-chip control functions. Each regulator channel utilizes pulse-by-pulse current limiting in the event of either a short circuit or an overload. If the overload is applied long enough, the IC temperature may rise sufficiently to cause the thermal shutdown circuit to operate. The part will auto-restart under control of the soft start circuit after the thermal disable condition is removed, and assuming all other conditions are met. See the Shutdown section for more information. Power Configuration The A4490 supports alternative schemes for providing logic supply voltage on the VDD pin. In addition, the IC can be powered up and down using either the VBB or ENB pins. Powering VDD To minimize power dissipation, especially at high input voltages, it is recommended that an external supply be applied to the VDD input pin. Typically, this voltage is derived from one of the three regulated outputs that are set-up for between 3.3 and 5 V (VREGx). Another advantage of powering the VDD externally is that the VBB undervoltage lockout level is lowered. To maximize the run time of the switchers during a VBB power-down condition, two alternative undervoltage shutdown conditions are supported, depending on which VDD-powering configuration has been implemented. When no external VDD is applied, the minimum VBB, VBBUV(sd) , is 4.1 V typical. When an external VDD is applied, the minimum VBB, VBBCPUV(sd) , is 3.5 V typical. One note of caution when deriving VDD from a VREG output: during initial application of VBB, the internal bias supply automatically starts from the internal regulator because VREG has not yet reached regulation. This means the startup threshold is determined by VBBUV(su) (4.3 V typical) because there is no external VDD. When VREG has begun to supply VDD externally, the shutdown threshold reduces to VBBCPUV(sd) (3.5 V typical). This assumes that VREG is present. Powering Up and Down with VBB Referring to figure 1, each of the enable inputs (ENBx) are held high by being tied to the VBB rail via a 100 kΩ resistor and the VDD is supplied from one of the regulator outputs. When the VBB voltage reaches the minimum threshold, VBBUV(su) , the charge pump supply (VCP) ramps up. When VBB + VCP has reached the minimum threshold VBBCPUV(su), the soft start routines are initiated (tSS) for all three regulator channels (VREGx). When all three regulators have reached the 85% FBx threshold, the power-on-reset timer is initiated. After the power-on-reset period, tPOR , has elapsed, PORZ goes high, indicating that all the regulators and VBB are in specification. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4490 Triple Output Step-Down Switching Regulator V BBUV(su) VBB V BBUV(por) 0V V BB+5.5 V V BBCPUV(su) VBB+VCP VREG1 V BBCPUV(sd) 85%FB1 VREG2 85%FB2 VREG3 85%FB3 PORZ t POR t SS Figure 1. Timing diagram for powering up and down using the VBB pin VBB 0V ENB1 ENB2 ENB3 VREG1 VREG2 VREG3 85%FB1 80%FB2 85%FB2 85%FB2 85%FB3 PORZ tSS tSS tPOR tSS tPOR tPOR Figure 2. Timing diagram for powering up and down using the ENB pin Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4490 Triple Output Step-Down Switching Regulator When the VBB voltage starts to fall below the undervoltage warning level, VBBUV(por) , of 3.6 V typical, the PORZ flag resets. This gives advance warning to the system controller that the VBB voltage is falling. Note that this feature is only guaranteed when VDD is supplied externally. During this interval, the three switchers continue to operate. While VBB falls further, the VCP supply also tends to fall, which degrades the drive voltage to the series switches. In addition, the higher voltage rails start to fall out of regulation first, as the corresponding maximum duty cycle (Dmax) for these particular converters is reached. The regulators that have the lower output voltages achieve some level of steady state, before the A4490 powers down when all of the corresponding VBB undervoltage thresholds have been reached. For example, it may be possible for a 1 V output to continue to operate down to a VBB of 3.4 V typical, if the VDD supply is derived externally. The extent of this effect depends on a myriad of factors, including input and output filter capacitance, output loads, gate drive amplitude, MOSFET RDS(on), and so forth. Powering Up and Down with Enable Referring to figure 2, VBB is present and the UVLO start-up thresholds, VBBUV(su) and VBBCPUV(su) have been reached. Each of the regulators are enabled in turn. Initially, VREG1 is enabled and is brought-up under the control of the soft start circuit (tSS). Before VREG1 reaches 85% FB1, VREG2 is enabled and is brought-up under a separate soft start control. When both regulators have reached their respective 85% FB thresholds, the power-on-reset (POR) timer is initiated. Note that the POR timer is only enabled after all of the enabled regulators reach their corresponding 85% FB levels. After the power-onreset time, tPOR , has elapsed, if the FB levels of VREG1 and VREG2 are not below their respective 80% FB levels, then the PORZ signal will go high. At some point later, if VREG3 is enabled, then the PORZ is reset and VREG3 is brought-up under the control of the soft start circuit. When the 85% FB3 threshold is reached, the POR timer is initiated. After tPOR has elapsed, if all the FB levels are above their respective 80% FB levels, then the PORZ signal will go high. Note that if any regulator channel is not enabled, the channel will not influence PORZ. To avoid multiple signal changes of the PORZ signal, it is recommended that the system be designed such that all three regulator channels are within specification before tPOR has elapsed. If any regulator channel drops below 80% FB, the PORZ signal will be reset. If the voltage then recovers to within 85% FB, the POR timer is initiated again. Note that a soft start is not initiated when the feedback voltage drops below the 80% FB level. This is to allow a rapid auto-restart in the event of an overload or similar fault. If a soft start is required, it is recommended that on receipt of the PORZ reset signal, the system controller disables and then re-enables the relevant regulator channels again. As soon as the last regulator is disabled the PORZ signal is reset. Power on Reset The power-on-reset duration, tPOR , is determined by selecting an appropriate capacitor connected to the CPOR pin. The value of tPOR can be determined by the following formula: tPOR = 2.131 ×105 × CPOR . (1) The PORZ output goes high when both VBB is above the undervoltage warning levels, and the FB pins of the regulators that are enabled are > 85% of the VREG voltage. Because the external capacitor is charged via a 5 μA current source, care must be taken in the layout to avoid additional leakage paths. The capacitor should be positioned adjacent to the CPOR pin, and the ground connection to the A4490 GND pin should be as short as possible. It is recommended that the tPOR period be set to exceed the start-up phases of all three regulators, to avoid the possibility of multiple triggerings of the PORZ output. Output Voltage Selection The output voltage on each of the three regulators is set by the following relationship, shown here for the VREG1 channel: ⎛V ⎞ R1 = R2 ⎜⎜ REG1 – 1 ⎟⎟ , (2) ⎝ VFB ⎠ where R2 (connected between GND and the FB1 pin) should be a value between 4.7 and 12 kΩ. R1 is connected between the output rail and the FB1 pin. VREG1 is the set output regulator voltage. VFB is the reference voltage. The tolerances of the feedback resistors influence the voltage setpoint. It is therefore important to consider the tolerance selection when targeting an overall regulation figure. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4490 Triple Output Step-Down Switching Regulator The bias current, IBIAS , flowing out of the FB1 node into R2, will introduce a small voltage offset to the output. to check the implications on the thermal performance. See the Thermal Considerations section. Enable Each regulator channel can be individually enabled via the corresponding ENBx pin. If any channel is required to startup automatically after the VBB voltage is applied, that particular channel should have the ENB pin tied to the VBB rail via a pullup resistor. Component Selection Soft Start Each regulator channel contains a soft start circuit. A soft start cycle is initiated when the appropriate regulator enable input is set to high; the VBB, charge pump, and bias supply voltages are above the minimum values; and no thermal shutdown condition exists. Note that an overload or short circuit will not cause a soft start cycle, unless a thermal shutdown event occurs. During a soft start cycle, the reference voltage is ramped from 0 to 0.8 V typical, which in turn forces the current demand signal to increase in a linear fashion. Shutdown All converter channels are disabled in the event of either a thermal shutdown event or an undervoltage on VBB (VBBUV(sd) or VBBCPUV(sd)). As soon as the above fault conditions have been removed, and assuming the ENB inputs are enabled, the appropriate channels will auto-restart under control of the soft start. Current Limit The typical peak current limit for each channel is specified as 2.5 A minimum, with a duty cycle of 0.9. The minimum current limit occurs at maximum duty cycle (0.9), because the slope compensation has a maximum effect under this condition. As the duty cycle reduces, the current limit increases. This means for applications that operate with a narrow duty cycle, it is possible to operate with a load current greater than 2.0 A. Figure 3 illustrates the typical peak current limit versus duty cycle. For example, it is possible to operate with a peak current limit of 3.75 A with a duty cycle of 0.3. As well as ensuring the peak current limit is not exceeded, under worst case load and input voltage conditions, it is also important It is recommended that gapped ferrite solutions be used as opposed to powdered iron solutions, the latter of which exhibit relatively high core losses that can have a large impact on long term reliability. Inductors are typically specified at two current levels, rms current and saturation current. With regard to the rms current, it is important to understand how the rms current level is specified, in terms of ambient temperature. Some manufacturers quote an ambient only, whilst others quote a temperature that includes a self-induced temperature rise. For example, if an inductor is rated for 85°C and includes a self-induced temperature rise of 25°C at maximum load, then the inductor cannot be safely operated beyond an ambient temperature of 60°C at full load. The rms current can be assumed to be simply the maximum load current, with perhaps some margin to allow for overloads, and so forth. The first stage of determining the inductor value is to specify a peak-to-peak ripple current of typically about 20% to 25% of the maximum load. Current Limit (A) This resistor should be selected to limit the current to less than the maximum specified value, 1 mA. This prevents the internal protection clamps from turning on. It is recommended that a 100 kΩ pull-up resistor be used. This would ensure the current remains below the maximum value when VBB = 36 V. Inductor The inductance value, L, determines the ripple current. It is important to ensure that the minimum current limit is not exceeded under worst-case conditions: VBB(min), ILOAD(max), fSW(min), and L(min). 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 0.5 1.0 0.5 0 0 20 40 60 80 100 Duty Cycle (%) Figure 3. Current limit versus duty cycle Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A4490 Triple Output Step-Down Switching Regulator The maximum peak-to-peak ripple current, IRIPPLE , occurs at the maximum input voltage. Therefore the duty cycle, D, should be found under these conditions (for the VREG1 channel): D(min) = VREG1+Vf VBB(max)+Vf . (3) where Vf is the forward voltage drop of the recirculation diode. The required inductance can be found: L (min) = 1 fSW(min) VBB(max) – VREG1 × D(min) × IRIPPLE , (4) Note that the manufacturers inductance tolerance should also be taken into account. This value may be as high as ±20%. The peak-to-peak current should not exceed 1 A, to avoid instability in the innermost circuit loops due to insufficient slope compensation. The maximum peak current can be found from to ensure that the saturation current level of the chosen inductor is not exceeded: Isat IRIPPLE = ILOAD + 2 . (5) Recommended inductor manufacturers and ranges are: • Taiyo Yuden: NR6045 series for 1.5 A outputs • Taiyo Yuden: NRG4026 series for 1.0 A outputs • Sumida: CDH74 series for 1.5 A outputs Output Capacitor In the interests of size, cost and performance, it is highly recommended that ceramic X5R or X7R capacitor types be used. When using ceramic capacitors another important consideration is the E-field effects on the actual value of the capacitor. To minimize the effects of the capacitance reducing with output voltage, it is recommended that the working voltage of the capacitor be considerably more than the set output voltage. As a suggestion, it is recommended that 6.3 V-rated capacitors should be used for output voltages of 3.3 V and below. For output voltages of 5 V, a 10 V-rated capacitor should be used. The output capacitor determines the output voltage ripple and is used to close the control loop. To guarantee stability, the capacitance has to increase as the output voltage is reduced. This is actually reasonable from a ripple voltage point of view, as the ripple voltage is typically specified as a percentage of output voltage. The following table outlines what the minimum output capacitance should be for a given output voltage: Output Voltage (V) Minimum Output Capacitance (μF) 15 3.3 12 4.7 5 10 3.3 20 1.8 to 2.5 30 <1.8 40 Capacitance values with greater than the above values can be used with the effect of reducing the bandwidth. This may be necessary in systems that have extremely low ripple/noise requirements. The output ripple is largely determined by the output capacitance and the effects of ESR and ESL can largely be ignored assuming good layout practice is observed. The output voltage ripple can be approximated to: VRIPPLE ≈ IRIPPLE 8 × fSW × COUT , (6) When using ceramic capacitors, there is generally no need to consider the current carrying capability due to the negligible heating effects of the ESR. Also, the rms current flowing into the output capacitor is extremely low. Input Capacitor Again it is highly recommended that ceramic, X5R or X7R capacitors be used. The value of the input capacitance determines the amount of current ripple (EMI) that appears at the source (VBB supply) terminals. The amounts of current flowing in and out of the input capacitor depend on the relative impedances between the input capacitor impedance and the source impedance. To achieve a low impedance filter solution it is recommended to place at least two capacitors in parallel. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A4490 Triple Output Step-Down Switching Regulator Again, there is generally no need to consider the heating effects of the rms current flowing through the ESR. Also, the phaseshifting of the input current drawn by each of the regulators helps to reduce the overall rms current. The following steps can be used as a guideline for determining a suitable thermal solution. It should be noted that this process is usually an iterative one to achieve the optimum solution. These factors can be considered as follows: Flyback Diode This diode conducts during the switch off-time. A Schottky diode is recommended to minimize both the forward drop and switching losses. Step 1. Estimate the maximum ambient temperature, TA(max) , of the application. The worst case dissipation occurs at maximum VBB , when the duty cycle, D, is a minimum. The average current through the diode can be found: IDIODE(av) = ILOAD × (1 – D(min)) . (7) The forward voltage drop, Vf , can be found from the diode characteristics by using the actual load current (not the average current). The static power dissipation can be found: PSTAT = ILOAD(av) × Vf . Step 2. Define the maximum junction temperature, TJ(max). Note that the absolute maximum is 150°C. Step 3. Determine the worst case power dissipation, PD(max). The evaluation should consider these at maximum load and minimum VBB. Contributors are switch static and dynamic losses, and control losses. These are described in the following sections Switch Static Losses The following steps can be used to determine switch static losses: Estimate the maximum duty cycle: (8) It is also important to take into account the thermal rating of the package, RθJA , and the ambient temperature, to ensure that enough heatsinking is provided to maintain the diode junction temperature within the safe operating area for the device. To minimize the heating effects from the A4490 on the diode and vice-versa, it is recommended that the diode be mounted on the reverse side of the printed circuit board. Support Components POR capacitor (C11), charge pump capacitor (C1), reservoir capacitor (C2) and VDD filter capacitor (C12) should be ceramic X5R or X7R. Thermal Considerations To ensure the A4490 operates in the safe operating area, which effectively means restricting the junction temperature to less than 150°C, several checks should be made. The general approach is to work out what thermal impedance (RJA) is required to maintain the junction temperature at a given level, for a particular power dissipation. Another factor worth considering is that other power dissipating components on the system PCB may influence the thermal performance of the A4490. For example, the power loss contribution from the recirculation diode and the sense resistor may cause the junction temperature of the A4490 to be higher than expected. D(max) = VREG + Vf VBB (min) + Vf , (9) where Vf is the forward voltage drop of the Schottky diode under the given load current. Estimate the RDS(on) of the each regulator switch at the given junction temperature: ⎛ TJ – 25 ⎞ ⎟ . RDS(on)TJ = RDS(on)25C ⎜⎜ 1+ (10) 200 ⎟ ⎝ ⎠ Note that if the VBB range is restricted to between 4.5 and 5.5 V, the RDS(on) increases. For example, the RDS(on) at 25°C with a VBB greater than 6 V is 450 mΩ typical, as stated in the Electrical Characteristics table. Under the same temperature conditions, with the VBB = 4.5 V, the RDS(on) is 560 mΩ typical. For VBB voltages between 4.5 and 6 V, the RDS(on) can be found by linear approximation. For more information on operating the A4490 between a VBB voltage of 4.5 and 5.5 V, see the Power Configurations section. The static loss for each switch can be determined: PSTAT = ILOAD2 × D(max) × RDS(on)TJ , (11) where ILOAD is the load for that particular regulator channel. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A4490 Triple Output Step-Down Switching Regulator Switch Dynamic Losses The following can be used to determine switch dynamic losses: ILOAD 2 30 10–9 fSW , (12) The RDS(on) of each switch can be found: where fSW is the switching frequency. Control Losses The following steps can be used to determine control losses: PVBB = IBBON × VBB , (13) where IBBON is the quiescent current assuming all three regulators are on. The static loss of each switch can be found: PSTAT1 = 12 × 0.84 × 0.653 = 0.55 W PSTAT2 = 12 × 0.58 × 0.653 = 0.379 W (b) Switch dynamic losses (15) 1 30 10–9 500 103 = 0.045 W 2 1 PDYN2 = 6 30 10–9 500 103 = 0.045 W 2 0.8 PDYN3 = 6 30 10–9 500 103 = 0.036 W 2 (c) Control losses PVBB = 0.005 × 6 = 0.03 W PDYN1 = 6 Total Losses The total losses can now be estimated: PTOTAL = PSTAT1 + PSTAT2 + PSTAT2 +PDYN1 +PDYN2 + PDYN3 +PVBB + PVDD . Thermal Impedance The thermal impedance required for the solution can now be determined: RQJA = T J – TA PTOTAL Example Selected parameters: VBB(min) = 6 V VREG1 = 5 V at 1 A VREG2 = 3.3 V at 1 A VREG3 = 1.8 V at 800 mA Vf = 0.4 V ⎞ ⎟ = 0.653 Ω ⎟ ⎠ (14) where IVDD and is the quiescent current on VDD. TJ = 115°C ⎛ 115 – 25 RDS(on)TJ = 450×10–3 ⎜⎜ 1+ 200 ⎝ PSTAT3 = 0.82 × 0.34 × 0.653 = 0.14 W PVDD = IVDD × VDD , TA= 70°C 5+0.4 = 0.84 6+0.4 3.3+0.4 = 0.58 VREG2 duty cycle, D2 = 6+0.4 1.8+0.4 = 0.34 VREG3 duty cycle, D3 = 6+0.4 VREG1 duty cycle, D1 = Both turn on and turn off losses can be estimated: PDYN = VBB (min) (a) Switch static losses . (16) PVDD = 0.001 × 3.3 = 0.003 W (d) The total power dissipation can now be found: PTOTAL = 0.55 + 0.379 + 0.14 + 0.045 + 0.045 + 0.036 + 0.03 + 0.003 = 1.228 W (e) The thermal impedance required for the solution can be found: 115 – 70 = 36.6 °C/W RQJA = 1.228 For this particular solution a high thermal efficiency board is required to ensure the junction temperature is kept below 115°C. For maximum effectiveness, the PCB pad area underneath the thermal pad of the A4490 should be exposed copper. Several thermal vias (say between 4 and 8) should be used to connect the thermal pad to the internal ground plane. If possible, an additional thermal copper plane should be applied to the bottom side of the PCB and connected to the thermal pad of the A4490 through the vias. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A4490 Triple Output Step-Down Switching Regulator This calculation assumes no thermal influence from other components. If possible, it is advisable to mount the flyback diodes on the reverse side of the printed circuit board. Ensure low impedance electrical connections are implemented between board layers. PCB Layout Guidelines The ground plane is largely dictated by the thermal requirements described in the previous section. The ground referenced power components should be referenced to a star ground, located away from the A4490 to minimize ground bounce issues. A small, local, relatively quiet ground plane near the A4490 should be used for the ground referenced support components, to minimize interference effects of ground noise from the power circuitry. Figure 4 illustrates the recommended grounding architecture. A4490 Support Components Power Circuitry Cin D A4490 Local “Quiet’ Ground Plane GND Cout PGND Star Connection Thermal Vias Internal Ground Plane A local quiet ground plane around these components can be implemented, however, this ground plane should have a high impedance connection to the star connection of the power stages. If a ground plane is used, it is recommended that it does not overlap the switching nodes (LX1, LX2, and LX3) to avoid the possibility of noise pick-up. To minimize the possibility of noise injection issues, it is recommended to isolate the ground plane around high impedance nodes such as: FBx, ENBx and CPOR. In terms of grounding the power components, a star connection should be made to minimize the ground loop impedances. Note that although a ground plane may be required to meet the thermal characteristics of the solution it is still imperative to implement a ground star connection for the power components. The ground for the charge pump (PGND) should be connected to the thermal vias. Figures 5 and 6 below illustrates the importance of keeping the ground connections as short as possible and forming good star connections. Figure 5 also illustrates the current conduction paths during the on-cycle of the switching FET. The following points should be noted: • The capacitor CIN should be placed as close as possible to the VBB terminals. The capacitance should be split between the VBB terminals for VREG1 and VREG3 and the VBB terminal for VREG2. Figure 4. Ground plane configurations Q To avoid ground bounce and offset issues, it is highly recommended that the ground referenced feedback resistors (R2, R4, and R6) should be connected as close to the GND connection of the A4490 as possible. L LX VREG VBB Q VREG VBB D CIN L LX D COUT CIN COUT RLOAD Star Connection Figure 5. FET on-cycle current conduction paths RLOAD Star Connection Figure 6. FET off-cycle current conduction paths Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A4490 Triple Output Step-Down Switching Regulator The VBB terminals for VREG1 and VREG2 should be connected via short and wide traces to the VBB terminal for VREG3. • Support components: POR capacitor (C11), charge pump capacitor (C1), reservoir capacitor (C2), and VDD filter capacitor • Each inductor should be connected as close as possible to the respective switching FET (LX1, LX2, and LX3) and output capacitors. (C12) should be located as close as possible to their respective Figure 6 shows the current conduction path during the off-cycle of the switching FET. The following points should be noted: Powering Configurations The following three diagrams show • The diode D should be placed as close as possible to both the switching FET and the inductor. middle diagram corresponds to the typical application shown on Only VBB supplied terminal connections. The ground referenced capacitors should be connected as close to the GND terminal as possible. typical configurations for providing power to the application. The the front page. VDD applied externally (second option) VDD applied externally (first option) 6 to 34 V 4.5 to 5.5 V 6 to 34 V VDD VBB VBB VBB L LX VREG D Comments: - Simple configuration, only one supply required - Increased power losses at higher VBB voltages - VBB start-up = 4.3 V (typical), shutdown = 4.1 V (typical) C VDD L LX VREG D Comments: - Reduced power losses at higher VBB voltages - VBB start-up = 4.3 V (typical), shutdown = 3.5 V (typical). In this case, the start-up threshold (VBBUV(su) ) is higher because VREG is not present C VDD L LX VREG D C Comments: - Power restricted as VBB < 6 V, due to increase in RDS(on) of buck switches - VBB start-up = 4.2 V (typical), shutdown = 3.5 V (typical) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 A4490 Triple Output Step-Down Switching Regulator Package ES, 20-Pin QFN 0.30 4.00 ±0.15 1 2 0.50 20 20 0.95 A 1 2 4.00 ±0.15 2.60 4.10 2.60 4.10 21X D SEATING PLANE 0.08 C +0.05 0.25 –0.07 0.75 ±0.05 0.50 C C PCB Layout Reference View For Reference Only (reference JEDEC MO-220WGGD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) +0.15 0.40 –0.10 B 2.60 2 1 C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 20 2.60 Copyright ©2008-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16