BSI BH62UV8001AIG55

Ultra Low Power/High Speed CMOS SRAM
1M X 8 bit
BH62UV8001
Green package materials are compliant to RoHS
„ FEATURES
„ DESCRIPTION
y Wide VCC low operation voltage : 1.65V ~ 3.6V
y Ultra low power consumption :
Operation current : 12mA (Max.)at 55ns
VCC = 3.6V
2mA (Max.) at 1MHz
O
Standby current : 15uA (Max.) at 3.6V/85 C
O
Data retention current : 7uA (Max.) at 85 C
VCC = 1.2V
y High speed access time :
-55
55ns (Max.) at VCC=3.0V
70ns (Max.) at VCC=1.8V
y Automatic power down when chip is deselected
y Easy expansion with CE1, CE2 and OE options
y Three state outputs and TTL compatible
y Fully static operation, no clock, no refresh
y Data retention supply voltage as low as 1.0V
The BH62UV8001 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 1,048,576 by 8 bits
and operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with maximum standby current of
O
15uA at 3.6V at 85 C and maximum access time of 55/70ns at
Vcc=3.0V/1.8V.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH62UV8001 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BH62UV8001 is available in DICE form and 48-ball BGA
package.
„ POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BH62UV8001DI
BH62UV8001AI
OPERATING
TEMPERATURE
STANDBY
Operating
(ICCSB1, Max)
VCC=3.6V
VCC=1.8V
15uA
12uA
1MHz
fMax.
2mA
6mA
12mA
3
4
5
6
A
NC
OE
A0
A1
A2
CE2
B
NC
NC
A3
A4
CE1
NC
C
DQ0
NC
A5
A6
NC
DQ4
D
VSS
DQ1
A17
A7
DQ5
VCC
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
Address
A16
5mA
8mA
DQ6
1024
10
Input
Row
Buffer
Decoder
Memory Array
1024 x 8192
8192
DQ0
8
DQ1
NC
1.5mA
„ BLOCK DIAGRAM
2
DQ2
fMax.
BGA-48-0608
1
VCC
1MHz
VCC=1.8V
10MHz
DICE
Industrial
O
O
-40 C to +85 C
„ PIN CONFIGURATIONS
E
PKG TYPE
(ICC, Max)
VCC=3.6V
10MHz
DQ2
VSS
Data
Input
Buffer
8
Write Driver
Sense Amp
DQ3
DQ4
8
DQ5
F
DQ3
NC
A14
A15
NC
DQ7
DQ6
G
NC
NC
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
CE1
CE2
WE
OE
VCC
GND
Data
Output
Buffer
Column I/O
8
1024
Column Decoder
DQ7
10
Control
Address Input Buffer
A19 A18 A17 A15 A14 A13 A16 A2 A1 A0
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH62UV8001
1
Revision
1.2
Oct.
2008
BH62UV8001
„ PIN DESCRIPTIONS
Name
Function
A0-A19 Address Input
These 20 address inputs select one of the 1,048,576 x 8 bit in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
VCC
8 bi-directional ports are used to read data from or write data into the RAM.
VSS
Ground
Power Supply
„ TRUTH TABLE
MODE
CE1
CE2
WE
OE
I/O OPERATION
VCC CURRENT
Chip De-selected
(Power Down)
H
X
X
X
X
L
X
X
High Z
ICCSB, ICCSB1
Output Disabled
L
H
H
H
High Z
ICC
Read
L
H
H
L
DOUT
ICC
Write
L
H
L
X
DIN
ICC
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
„ ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM
TBIAS
TSTG
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
RATING
(2)
-0.5
to 4.6V
„ OPERATING RANGE
UNITS
RANG
AMBIENT
TEMPERATURE
V
Industrial
-40 C to + 85 C
-40 to +125
O
C
-60 to +150
O
C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
O
O
VCC
1.65V ~ 3.6V
„ CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
CIN
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. –2.0V in case of AC pulse width less than 30 ns
R0201-BH62UV8001
CIO
Input
Capacitance
Input/Output
Capacitance
VIN = 0V
6
pF
VI/O = 0V
8
pF
1. This parameter is guaranteed and not 100% tested.
2
Revision
1.2
Oct.
2008
BH62UV8001
„ DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
PARAMETER
NAME
PARAMETER
VCC
Power Supply
VIL
Input Low Voltage
TEST CONDITIONS
VCC=1.8V
MIN.
TYP.(1)
MAX.
UNITS
1.65
--
3.6
V
(2)
-0.3
--
VCC=3.6V
VIH
Input High Voltage
IIL
Input Leakage Current
ILO
Output Leakage Current
VOL
Output Low Voltage
VOH
ICC
ICC1
ICCSB
ICCSB1
VCC=1.8V
1.4
VCC=3.6V
2.2
VIN = 0V to VCC,
CE1 = VIH or CE2 = VIL
VI/O = 0V to VCC,
CE1 = VIH or CE2 = VIL or OE = VIH
--
--
--
1
uA
--
--
VCC = Min, IOH = -0.1mA
VCC=1.8V
VCC-0.2
VCC = Min, IOH = -1.0mA
VCC=3.6V
2.4
Operating Power Supply
CE1 = VIL, CE2 = VIH,
VCC=1.8V
Current
IDQ = 0mA, f = FMAX
CE1 = VIL and CE2 = VIH,
VCC=1.8V
VCC=3.6V
Standby Current – TTL
Standby Current – CMOS
--
--
VCC=3.6V
IDQ = 0mA, f = 1MHz
CE1 = VIH, or CE2 = VIL,
VCC=1.8V
IDQ = 0mA
VCC=3.6V
CE1≧VCC-0.2V or CE2≦0.2V,
VCC=1.8V
VIN ≧VCC-0.2V or V IN ≦0.2V
VCC=3.6V
V
uA
VCC=3.6V
Current
(3)
1
VCC=1.8V
Operating Power Supply
VCC+0.3
--
VCC = Max, IOL = 2.0mA
(4)
V
--
VCC = Max, IOL = 0.1mA
Output High Voltage
0.4
0.6
---
0.4
--
--
8
--
12
mA
--
1.5
2.0
2.0
2.5
(5)
V
V
---
--
0.2
0.5
1.0
12
mA
mA
uA
15
O
1. Typical characteristics are at TA=25 C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. VCC=3.0V
„ DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
PARAMETER
VDR
VCC for Data Retention
ICCDR(3)
Data Retention Current
tCDR
tR
TEST CONDITIONS
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
VCC=1.2V
Chip Deselect to Data
Retention Time
MIN.
TYP. (1)
MAX.
UNITS
1.0
--
--
V
--
1.2
7.0
uA
0
--
--
ns
--
--
ns
See Retention Waveform
Operation Recovery Time
tRC
(2)
O
1. Typical characteristics are at TA=25 C and not 100% tested.
2. tRC = Read Cycle Time.
„ LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
VCC
CE1
R0201-BH62UV8001
VDR≧1.0V
VCC
tCDR
VCC
tR
CE1≧VCC - 0.2V
VIH
3
VIH
Revision
1.2
Oct.
2008
BH62UV8001
„ LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
VDR≧1.0V
VCC
VCC
VCC
tCDR
CE2
tR
CE2≦0.2V
VIL
VIL
„ AC TEST CONDITIONS
„ KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
VCC / 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
tCLZ1, tCLZ2, tOLZ, tCHZ1,
tCHZ2, tOHZ, tWHZ, tOW
Output Load
Others
WAVEFORM
0.5Vcc
CL = 5pF+1TTL
CL = 30pF+1TTL
ALL INPUT PULSES
VCC
1 TTL
Output
90%
GND
(1)
L
C
90%
10%
10%
→ ←
Rise Time:
1V/ns
→ ←
Fall Time:
1V/ns
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
WILL BE CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
1. Including jig and scope capacitance.
„ AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
CYCLE TIME : 55ns
(VCC = 3.0V)
MIN. TYP. MAX.
DESCRIPTION
CYCLE TIME : 70ns
(VCC = 1.8V)
MIN. TYP. MAX.
UNITS
tAVAX
tRC
Read Cycle Time
55
--
--
70
--
--
ns
tAVQX
tAA
Address Access Time
--
--
55
--
--
70
ns
tE1LQV
tACS1
Chip Select Access Time
(CE1)
--
--
55
--
--
70
ns
tE2HQV
tACS2
Chip Select Access Time
(CE2)
--
--
55
--
--
70
ns
tGLQV
tOE
--
--
30
--
--
30
ns
tE1LQX
tCLZ1
Chip Select to Output Low Z
(CE1)
10
--
--
10
--
--
ns
tE2HQX
tCLZ2
Chip Select to Output Low Z
(CE2)
10
--
--
10
--
--
ns
tGLQX
tOLZ
Output Enable to Output Low Z
5
--
--
10
--
--
ns
tE1HQZ
tCHZ1
Chip Select to Output High Z
(CE1)
--
--
25
--
--
35
ns
tE2LQZ
tCHZ2
Chip Select to Output High Z
(CE2)
--
--
25
--
--
35
ns
tGHQZ
tOHZ
Output Enable to Output High Z
--
--
25
--
--
30
ns
tAVQX
tOH
Data Hold from Address Change
10
--
--
10
--
--
ns
R0201-BH62UV8001
Output Enable to Output Valid
4
Revision
1.2
Oct.
2008
BH62UV8001
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
READ CYCLE 2 (1,3,4)
CE1
tACS1
CE2
DOUT
tACS2
tCLZ
tCHZ1, tCHZ2(5)
(5)
READ CYCLE 3 (1, 4)
tRC
ADDRESS
tAA
OE
tOE
tOH
tOLZ
CE1
tACS1
tCLZ1(5)
CE2
tACS2
tCLZ2(5)
tOHZ(5)
tCHZ1(1,5)
tCHZ2(2,5)
DOUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BH62UV8001
5
Revision
1.2
Oct.
2008
BH62UV8001
„ AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
CYCLE TIME : 55ns
(VCC = 3.0V)
MIN. TYP. MAX.
DESCRIPTION
CYCLE TIME : 70ns
(VCC = 1.8V)
MIN. TYP. MAX.
UNITS
tAVAX
tWC
Write Cycle Time
55
--
--
70
--
--
ns
tAVWL
tAS
Chip Select to End of Write
0
--
--
0
--
--
ns
tAVWH
tAW
Address Set up Time
40
--
--
50
--
--
ns
tE1LWH
tCW
Address Valid to End of Write
40
--
--
50
--
--
ns
tWLWH
tWP
Write Pulse Width
30
--
--
35
--
--
ns
tWHAX
tWR1
Write Recovery Time
(CE1, WE)
0
--
--
0
--
--
ns
tE2LAX
tWR2
Write Recovery Time
(CE2)
0
--
--
0
--
--
ns
tWLQZ
tWHZ
Write to Output High Z
--
--
25
--
--
30
ns
tDVWH
tDW
Data to Write Time Overlap
25
--
--
30
--
--
ns
tWHDX
tDH
Data Hold from Write Time
0
--
--
0
--
--
ns
tGHQZ
tOHZ
Output Disable to Output in High Z
--
--
25
--
--
30
ns
tWHQX
tOW
End of Write to Output Active
5
--
--
5
--
--
ns
„ SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
tWR1(3)
OE
tCW(11)
CE1
(5)
CE2
(5)
tAW
WE
tCW(11)
tWR2(3)
tWP(2)
tAS
tOHZ(4,10)
DOUT
tDH
tDW
DIN
R0201-BH62UV8001
6
Revision
1.2
Oct.
2008
BH62UV8001
WRITE CYCLE 2 (1,6)
tWC
ADDRESS
CE1
tCW(11)
(5)
CE2
(5)
tAW
WE
tAS
tCW(11)
tWR2(3)
tWP(2)
tWHZ(4,10)
tOW
(7)
(8)
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE
low. All signals must be active to initiate a write and any one signal can terminate a write by
going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.tCW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BH62UV8001
7
Revision
1.2
Oct.
2008
BH62UV8001
„ ORDERING INFORMATION
BH62UV8001
X
X
Z
YY
SPEED
55: 55ns
PKG MATERIAL
G: Green, RoHS Compliant
GRADE
o
o
I: -40 C ~ +85 C
PACKAGE
D: DICE
A: BGA-48-0608
Note:
Brilliance Semiconductor Inc. (BSI) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
„ PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
1.2 Max.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
E1
e
D1
VIEW A
48 mini-BGA (6 x 8)
R0201-BH62UV8001
8
Revision
1.2
Oct.
2008
BH62UV8001
„ Revision History
Revision No.
History
Draft Date
Remark
1.0
Initial Production Version
May 10,2006
Initial
1.1
Change I-grade operation temperature range
- from –25OC to –40OC
May. 25, 2006
1.2
Change -55 55ns(Max.) at VCC=1.65~3.6V to
55ns(Max.) at VCC=3.0V and 70ns(Max.) at
VCC=1.8V
Oct. 31, 2008
Typical value of standby current is replaced by
maximum value in Featues and Description
section
Remove “-: Normal” (Leaded) PKG Material in
ordering information
R0201-BH62UV8001
9
Revision
1.2
Oct.
2008