EON EN25S32

EN25S32
EN25S32
32 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
•
-
• Single power supply operation
- Full voltage range: 1.65-1.95 volt
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
Uniform Sector Architecture:
1024 sectors of 4-Kbyte
64 blocks of 64-Kbyte
Any sector or block can be erased individually
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
• 32 M-bit Serial Flash
- 32 M-bit / 4096 KByte /16384 pages
- 256 bytes per programmable page
•
-
Standard, Dual or Quad SPI
Standard SPI: CLK, CS#, DI, DO, WP#
Dual SPI: CLK, CS#, DQ0, DQ1, WP#
Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
•
-
High performance
104MHz clock rate for one data bit
80MHz clock rate for two data bits
80MHz clock rate for four data bits
•
-
High performance program/erase speed
Page program time: 0.7ms typical
Sector erase time: 40ms typical
64KB Block erase time 300ms typical
Chip erase time: 17 seconds typical
• Write Suspend and Write Resume
• Lockable 512 byte OTP security sector
• Minimum 100K endurance cycle
• Burst Modes
- Continuous linear burst
- 8/16/32/64/128/256 linear burst with wraparound
•
-
• Low power consumption
- 12 mA typical active current
- 1μA typical power down current
Package Options
8 pins VSOP 200mil body width
8 contact VDFN
All Pb-free packages are RoHS compliant
• Industrial temperature Range
GENERAL DESCRIPTION
The EN25S32 is a 32 Megabit (4096K-byte) Serial Flash memory, with advanced write protection
mechanisms. The EN25S32 supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual output as well as Dual, Quad I/O using SPI pins: Serial Clock, Chip Select, Serial
DQ0 (DI) and DQ1(DO), DQ2(WP#) and DQ3(NC). SPI clock frequencies of up to 80MHz are supported
allowing equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output when using
the Dual/Quad Output Fast Read instructions. The memory can be programmed 1 to 256 bytes at a
time, using the Page Program instruction.
The EN25S32 also offers a sophisticated method for protecting individual blocks against erroneous or
malicious program and erase operations. By providing the ability to individually protect and unprotect
blocks, a system can unprotect a specific block to modify its contents while keeping the remaining
blocks of the memory array securely protected. This is useful in applications where program code is
patched or updated on a subroutine or module basis or in applications where data storage segments
need to be modified without running the risk of errant modifications to the program code segments.
The EN25S32 is designed to allow either single Sector/Block at a time or full chip erase operation. The
EN25S32 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
Figure.1 CONNECTION DIAGRAMS
CS#
1
8
VCC
DO (DQ1)
2
7
NC (DQ3)
WP# (DQ2)
3
6
CLK
4
5
DI (DQ0)
VSS
8 - LEAD VSOP
CS#
1
8
VCC
DO (DQ1)
2
7
NC (DQ3)
WP# (DQ2)
3
6
CLK
4
5
DI (DQ0)
VSS
8 - LEAD VDFN
Table 1. Pin Names
Symbol
Pin Name
CLK
Serial Clock Input
DI (DQ0)
Serial Data Input (Data Input Output 0)
DO (DQ1)
Serial Data Output (Data Input Output 1)
CS#
Chip Enable
WP# (DQ2)
Write Protect (Data Input Output 2)
NC(DQ3)
Not Connect (Data Input Output 3)
Vcc
Supply Voltage (1.65-1.95 V)
Vss
Ground
NC
No Connect
*1
*1
*2
*2
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ0 ~ DQ3 are used for Quad instructions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
Figure 2. BLOCK DIAGRAM
Note:
1. DQ0 and DQ1 are used for Dual instructions.
2. DQ0 ~ DQ3 are used for Quad instructions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
SIGNAL DESCRIPTION
Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1, DQ2, DQ3)
The EN25S32 support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2 and DQ3) pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from
the device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1, BP2, BP3) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function
is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ2) for Quad I/O operation.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
MEMORY ORGANIZATION
The memory is organized as:
z
4,194,304 bytes
z
Uniform Sector Architecture
64 blocks of 64-Kbyte
128 blocks of 32-Kbyte
1024 sectors of 4-Kbyte
16384 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
Table 2. Uniform Block Sector Architecture ( 1/2 )
800
799
320000h
31F000h
320FFFh
31FFFFh
784
783
310000h
30F000h
310FFFh
30FFFFh
768
300000h
300FFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
34
33
32
6
….
2A0FFFh
29FFFFh
290FFFh
28FFFFh
280000h
27F000h
280FFFh
27FFFFh
270000h
26F000h
270FFFh
26FFFFh
260000h
25F000h
260FFFh
25FFFFh
592
591
250000h
24F000h
250FFFh
24FFFFh
….
….
608
607
….
….
624
623
….
….
640
639
….
….
290000h
28F000h
….
656
655
….
….
2A0000h
29F000h
….
672
671
….
….
….
….
….
….
….
2B0FFFh
2AFFFFh
….
….
….
….
….
….
….
….
….
….
2B0000h
2AF000h
….
688
687
576
575
240000h
23F000h
240FFFh
23FFFFh
….
35
2C0FFFh
2BFFFFh
560
559
230000h
22F000h
230FFFh
22FFFFh
….
330FFFh
32FFFFh
2C0000h
2BF000h
544
543
220000h
21F000h
220FFFh
21FFFFh
….
330000h
32F000h
704
703
528
527
210000h
20F000h
210FFFh
20FFFFh
….
816
815
36
2D0FFFh
2CFFFFh
….
340FFFh
33FFFFh
37
2D0000h
2CF000h
….
340000h
33F000h
38
720
719
….
832
831
39
2E0FFFh
2DFFFFh
….
350FFFh
34FFFFh
40
2E0000h
2DF000h
….
….
350000h
34F000h
….
848
847
….
360FFFh
35FFFFh
….
360000h
35F000h
….
864
863
41
736
735
….
370FFFh
36FFFFh
….
370000h
36F000h
….
880
879
42
2F0FFFh
2EFFFFh
….
380FFFh
37FFFFh
43
2F0000h
2EF000h
….
380000h
37F000h
44
752
751
….
….
896
895
45
2FFFFFh
….
390FFFh
38FFFFh
46
2FF000h
….
….
390000h
38F000h
….
912
911
….
….
3A0FFFh
39FFFFh
….
3A0000h
39F000h
….
928
927
767
47
Address range
….
….
….
3B0FFFh
3AFFFFh
….
….
….
….
….
….
3B0000h
3AF000h
….
….
….
….
….
….
….
….
….
944
943
….
3C0FFFh
3BFFFFh
Sector
….
48
3C0000h
3BF000h
….
49
960
959
….
50
3D0FFFh
3CFFFFh
….
51
3D0000h
3CF000h
….
52
976
975
….
53
3E0FFFh
3DFFFFh
….
54
3E0000h
3DF000h
….
55
992
991
….
56
3F0FFFh
3EFFFFh
….
57
3F0000h
3EF000h
….
58
1008
1007
….
59
3FFFFFh
….
60
3FF000h
….
61
1023
….
62
64KB
Block
Address range
….
63
Sector
….
64KB
Block
512
200000h
200FFFh
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
Table 2. Uniform Block Sector Architecture ( 2/2 )
288
287
120000h
11F000h
120FFFh
11FFFFh
272
271
110000h
10F000h
110FFFh
10FFFFh
256
100000h
100FFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
1
0
7
….
0A0FFFh
09FFFFh
090FFFh
08FFFFh
080000h
07F000h
080FFFh
07FFFFh
070000h
06F000h
070FFFh
06FFFFh
060000h
05F000h
060FFFh
05FFFFh
80
79
050000h
04F000h
050FFFh
04FFFFh
….
….
96
95
….
….
112
111
….
….
128
127
….
….
090000h
08F000h
….
144
143
….
….
0A0000h
09F000h
….
160
159
….
….
….
….
….
….
….
0B0FFFh
0AFFFFh
….
….
….
….
….
….
….
….
….
….
0B0000h
0AF000h
….
176
175
64
63
040000h
03F000h
040FFFh
03FFFFh
….
3
0C0FFFh
0BFFFFh
48
47
030000h
02F000h
030FFFh
02FFFFh
….
130FFFh
12FFFFh
0C0000h
0BF000h
32
31
020000h
01F000h
020FFFh
01FFFFh
….
130000h
12F000h
192
191
16
15
010000h
00F000h
010FFFh
00FFFFh
….
304
303
4
0D0FFFh
0CFFFFh
….
140FFFh
13FFFFh
5
0D0000h
0CF000h
….
140000h
13F000h
6
208
207
….
320
319
7
0E0FFFh
0DFFFFh
….
150FFFh
14FFFFh
8
0E0000h
0DF000h
….
….
150000h
14F000h
….
336
335
….
160FFFh
15FFFFh
….
160000
15F000
….
352
351
9
224
223
….
170FFFh
16FFFFh
….
170000h
16F000h
….
368
367
10
0F0FFFh
0EFFFFh
….
180FFFh
17FFFFh
11
0F0000h
0EF000h
….
180000h
17F000h
12
240
239
….
….
384
383
13
0FFFFFh
….
190FFFh
18FFFFh
14
0FF000h
….
….
190000h
18F000h
….
400
399
….
….
1A0FFFh
19FFFF
….
1A0000h
19F000h
….
416
415
255
15
Address range
….
….
….
1B0FFFh
1AFFFFh
….
….
….
….
….
….
1B0000h
1AF000h
….
….
….
….
….
….
….
….
….
432
431
….
1C0FFFh
1BFFFFh
Sector
….
16
1C0000h
1BF000h
….
17
448
447
….
18
1D0FFFh
1CFFFFh
….
19
1D0000h
1CF000h
….
20
464
463
….
21
1E0FFFh
1DFFFFh
….
22
1E0000h
1DF000h
….
23
480
479
….
24
1F0FFFh
1EFFFFh
….
25
1F0000h
1EF000h
….
26
496
495
….
27
1FFFFFh
….
28
1FF000h
….
29
511
….
30
64KB
Block
Address range
….
31
Sector
….
64KB
Block
0
000000h
000FFFh
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
OPERATING FEATURES
Standard SPI Modes
The EN25S32 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0
(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in
Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby and data
is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the
CLK signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the
CLK. Data output on the DO pin is clocked out on the falling edge of CLK.
Figure 3. SPI Modes
Dual SPI Instruction
The EN25S32 supports Dual SPI operation when using the “ Dual Output Fast Read and Dual I/ O
FAST_READ “ (3Bh and BBh) instructions. These instructions allow data to be transferred to or from
the Serial Flash memory at two to three times the rate possible with the standard SPI. The Dual Read
instructions are ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing)
or for application that cache code-segments to RAM for execution. The Dual output feature simply
allows the SPI input pin to also serve as an output during this instruction. When using Dual SPI
instructions the DI and DO pins become bidirectional I/O pins; DQ0 and DQ1. All other operations use
the standard SPI interface with single output signal.
Quad SPI Instruction
The EN25S32 supports Quad output operation when using the Quad I/O Fast Read (EBh).This
instruction allows data to be transferred to or from the Serial Flash memory at four to six times the rate
possible with the standard SPI. The Quad Read instruction offer a significant improvement in
continuous and random access transfer rates allowing fast code-shadowing to RAM or for application
that cache code-segments to RAM for execution. The EN25S32 also supports full Quad Mode function
while using the Enable Quad Peripheral Interface mode (EQPI) (38h). When using Quad SPI instruction
the DI and DO pins become bidirectional I/O pins; DQ0 and DQ1, and the WP# and NC pins become
DQ2 and DQ3 respectively.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
8
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
Figure 4. Quad SPI Modes
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and
a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal
Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed
at a time (changing bits from 1 to 0) provided that they lie in consecutive addresses on the same page
of memory.
Sector Erase, Block Erase and Chip Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a time,
using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or
throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle
(of duration tSE tBE or tCE). The Erase instruction must be preceded by a Write Enable (WREN)
instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or
CE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE or tCE). The Write In
Progress (WIP) bit is provided in the Status Register so that the application program can monitor its
value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip
Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal
cycles have completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains
in this mode until another specific instruction (the Release from Deep Power-down Mode and Read
Device ID (RDI) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used
as an extra software protection mechanism, when the device is not in active use, to protect the device
from inadvertent Write, Program or Erase instructions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
9
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
Status Register and Suspend Status Register
The Status Register and Suspend Status Register contain a number of status and control bits that can
be read or set (as appropriate) by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions.
WPDIS bit. The Write Protect disable (WPDIS) bit, non-volatile bit, when it is reset to “0” (factory
default) to enable WP# function or is set to “1” to disable WP# function (can be floating during SPI
mode.)
SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit operates in conjunction with the Write
Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status
Register (SRP, BP3, BP2, BP1, BP0) become read-only bits.
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only
be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before entering OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
WSE bit. The Write Suspend Erase Status (WSE) bit indicates when an Erase operation has been
suspended. The WSE bit is “1” after the host issues a suspend command during an Erase operation.
Once the suspended Erase resumes, the WSE bit is reset to “0”.
WSP bit. The Write Suspend Program Status (WSP) bit indicates when a Program operation has been
suspended. The WSP is “1” after the host issues a suspend command during the Program operation.
Once the suspended Program resumes, the WSP bit is reset to “0”.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the EN25S32
provides the following data protection mechanisms:
z
Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z
Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
z
All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction
completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction
completion
z
The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as readonly. This is the Software Protected Mode (SPM).
z
The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z
In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
10
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
Table 3. Protected Area Sizes Sector Organization
Status Register Content
BP3
Bit
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BP2
Bit
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
Bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Memory Content
Protect Areas
Addresses
None
Block 0 to 62
Block 0 to 61
Block 0 to 59
Block 0 to 55
Block 0 to 47
Block 0 to 31
All
None
Block 63 to 1
Block 63 to 2
Block 63 to 4
Block 63 to 8
Block 63 to 16
Block 63 to 32
All
None
000000h-3EFFFFh
000000h-3DFFFFh
000000h-3BFFFFh
000000h-37FFFFh
000000h-2FFFFFh
000000h-1FFFFFh
000000h-3FFFFFh
None
3FFFFFh-010000h
3FFFFFh-020000h
3FFFFFh-040000h
3FFFFFh-080000h
3FFFFFh-100000h
3FFFFFh-200000h
000000h-3FFFFFh
Density(KB)
None
4032KB
3968KB
3840KB
3584KB
3072KB
2048KB
4096KB
None
4032KB
3968KB
3840KB
3584KB
3072KB
2048KB
4096KB
Portion
None
Lower 63/64
Lower 62/64
Lower 60/64
Lower 56/64
Lower 48/64
Lower 32/64
All
None
Upper 63/64
Upper 62/64
Upper 60/64
Upper 56/64
Upper 48/64
Upper 32/64
All
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is
driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has
been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output
FAST_READ (EBh), Read Status Register (RDSR), Read Suspend Status Register (RDSSR) or
Release from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write
Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction
is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock
pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at
any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down
(RES ) minimum number of bytes specified has to be given, without which, the command will be
ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any
less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
11
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
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EN25S32
Table 4A. Instruction Set
Instruction Name
Byte 1
Code
RSTEN
66h
RST(1)
EQPI
99h
RSTQIO(2)
Release Quad I/O or
Fast Read Enhanced
Mode
Write Enable
Write Disable / Exit
OTP mode
Read Status
Register
Read Suspend
Status Register
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
38h
FFh
06h
04h
05h
(S7-S0)(3)
continuous(4)
09h
(S7-S0)(3)
continuous(4)
Write Status
Register
01h
S7-S0
Page Program
02h
A23-A16
A15-A8
A7-A0
Write Suspend
B0h
Write Resume
Sector Erase / OTP
erase
64K Block Erase
30h
20h
A23-A16
A15-A8
A7-A0
D8h
A23-A16
A15-A8
A7-A0
Chip Erase
C7h/ 60h
Deep Power-down
Release from Deep
Power-down, and
read Device ID
Release from Deep
Power-down
Manufacturer/
Device ID
Read Identification
Enter OTP mode
B9h
D7-D0
Next byte
continuous
(5)
dummy
dummy
90h
dummy
dummy
9Fh
3Ah
(M7-M0)
(ID15-ID8)
dummy
(ID7-ID0)
00h
01h
(ID7-ID0)
(M7-M0)
(ID7-ID0)
(7)
ABh
(ID7-ID0)
(M7-M0)
(6)
Notes:
1. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
2. Device accepts eight-clocks command in Standard SPI mode, or two-clocks command in Quad SPI mode
3. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the
device on the DO pin.
4. The Status Register contents will repeat continuously until CS# terminate the instruction.
5. The Device ID will repeat continuously until CS# terminates the instruction.
6. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminates the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.
7. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN25S32
Table 4B. Instruction Set (Read Instruction)
Instruction Name
Byte 1
Code
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
Read Data
03h
A23-A16
A15-A8
A7-A0
(D7-D0)
(Next byte)
continuous
Fast Read
0Bh
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
Dual Output Fast
Read
3Bh
A23-A16
A15-A8
A7-A0
dummy
(D7-D0, …) (1)
Dual I/O Fast Read
BBh
A23-A8(2)
A7-A0,
dummy (2)
(D7-D0, …) (1)
Quad I/O Fast Read
EBh
A23-A0,
dummy (4)
(dummy,
D7-D0 ) (5)
(D7-D0, …) (3)
Set Burst
Read Burst with
wrap
C0h,
(Next Byte)
continuous
(one byte
per 4 clocks,
continuous)
(one byte
per 4 clocks,
continuous)
(one byte
per 2 clocks,
continuous)
(6)
(D7-D0)
0Ch,
dummy (7),
A23-A0,
(D7-D0 ) (3)
(one byte
per 2 clocks,
continuous)
(D7-D0, …) (3)
Notes:
1. Dual Output data
DQ0 = (D6, D4, D2, D0)
DQ1 = (D7, D5, D3, D1)
2. Dual Input Address
DQ0 = A22, A20, A18, A16, A14, A12, A10, A8 ; A6, A4, A2, A0, dummy 6, dummy 4, dummy 2, dummy 0
DQ1 = A23, A21, A19, A17, A15, A13, A11, A9 ; A7, A5, A3, A1, dummy 7, dummy 5, dummy 3, dummy 1
3. Quad Data
DQ0 = (D4, D0, …… )
DQ1 = (D5, D1, …… )
DQ2 = (D6, D2, …... )
DQ3 = (D7, D3, …... )
4. Quad Input Address
DQ0 = A20, A16, A12, A8, A4, A0, dummy 4, dummy 0
DQ1 = A21, A17, A13, A9, A5, A1, dummy 5, dummy 1
DQ2 = A22, A18, A14, A10, A6, A2, dummy 6, dummy 2
DQ3 = A23, A19, A15, A11, A7, A3, dummy 7, dummy 3
5. Quad I/O Fast Read Data
DQ0 = ( dummy 12, dummy 8, dummy 4, dummy 0, D4, D0 )
DQ1 = ( dummy 13, dummy 9, dummy 5, dummy 1, D5, D1 )
DQ2 = ( dummy 14, dummy 10, dummy 6, dummy 2, D6, D2 )
DQ3 = ( dummy 15, dummy 11, dummy 7, dummy 3, D7, D3 )
6. Set burst and Wrap Length
Table 5. Burst length configuration table
Data to setup
00h
01h
02h
03h
04h
05h
Burst length
8 Bytes ( default)
16 Bytes
32 Bytes
64 Bytes
128 Bytes
256 Bytes
Burst wrap (A[7:A0]) address range
00-07H, 08-0FH, 10-17H, 18-1FH...
00-0FH, 10-1FH, 20-2FH, 30-3FH...
00-1FH, 20-3FH, 40-5FH, 60-7FH...
00-3FH, 40-7FH, 80-BFH, C0-FFH
00-7FH, 80-FFH
00-FFH
If input data is not between 00h~05h or user does not Set Burst, the Burst length will be 8 Bytes in
default.
7. Two dummy cycles (4 clocks) are necessary for Read Burst with Wrap mode.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN25S32
Table 6. Manufacturer and Device Identification
OP Code
(M7-M0)
(ID15-ID0)
(ID7-ID0)
ABh
75h
90h
1Ch
9Fh
1Ch
75h
3816h
Reset-Enable (RSTEN) (66h) and Reset (RST) (99h)
The Reset operation is used as a system (software) reset that puts the device in normal operating
Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST).
To reset the EN25S32 the host drives CS# low, sends the Reset-Enable command (66h), and drives
CS# high. Next, the host drives CS# low again, sends the Reset command (99h), and drives CS# high.
The Reset operation requires the Reset-Enable command followed by the Reset command. Any
command other than the Reset command after the Reset-Enable command will disable the ResetEnable.
A successful command execution will reset the Status register and the Suspend Status register to data
= 00h, see Figure 5 for SPI Mode and Figure 5.1 for Quad Mode. A device reset during an active
Program or Erase operation aborts the operation, which can cause the data of the targeted address
range to be corrupted or lost. Depending on the prior operation, the reset timing may vary. Recovery
from a Write operation requires more software latency time ( tSR) than recovery from other operations.
Figure 5. Reset-Enable and Reset Sequence Diagram
Figure 5.1 . Reset-Enable and Reset Sequence Diagram under EQPI Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN25S32
Software Reset Flow
Initial
No
Command
= 66h ?
Yes
Reset enable
No
Command
= 99h ?
Yes
Reset start
No
WIP = 0 ?
Embedded
Reset Cycle
Yes
Reset done
Note:
1. Reset-Enable (RSTEN) (66h) and Reset (RST) (99h) commands need to match standard SPI or
EQPI (quad) mode.
2. Continue (Enhance) EB mode need to use quad Reset-Enable (RSTEN) (66h) and quad Reset (RST)
(99h) commands.
3. If user is not sure it is in SPI or Quad mode, we suggest to execute sequence as follows:
Quad Reset-Enable (RSTEN) (66h) -> Quad Reset (RST) (99h) -> SPI Reset-Enable (RSTEN) (66h)
-> SPI Reset (RST) (99h) to reset.
4. The reset command could be executed during embedded program and erase process, EQPI mode,
Continue EB mode and suspend mode to back to SPI mode.
5. This flow cannot release the device from Deep power down mode.
6. The Status Register Bit and Suspend Status Register Bit will reset to default value after reset done.
7. If user reset device during erase, the embedded reset cycle software reset latency will take about
28us in worst case.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN25S32
Enable Quad Peripheral Interface mode (EQPI) (38h)
The Enable Quad Peripheral Interface mode (EQPI) instruction will enable the flash device for Quad
SPI bus operation. Upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed
input/output until a power cycle or “ Reset Quad I/O instruction “ instruction, as shown in Figure 6. The
device did not support the Read Data Bytes (READ) (03h), Dual Output Fast Read (3Bh) and Dual
Input/Output FAST_READ (BBh) modes while the Enable Quad Peripheral Interface mode (EQPI) (38h)
turns on.
Figure 6. Enable Quad Peripheral Interface mode Sequence Diagram
Reset Quad I/O (RSTQIO) or Release Quad I/O Fast Read Enhancement Mode (FFh)
The Reset Quad I/O instruction resets the device to 1-bit Standard SPI operation. To execute a Reset
Quad I/O operation, the host drives CS# low, sends the Reset Quad I/O command cycle (FFh) then,
drives CS# high. This command can’t be used in Standard SPI mode.
User also can use the FFh command to release the Quad I/O Fast Read Enhancement Mode. The
detail description, please see the Quad I/O Fast Read Enhancement Mode section.
Note:
If the system is in the Quad I/O Fast Read Enhance Mode under EQPI Mode, it is necessary to execute
FFh command by two times. The first FFh command is to release Quad I/O Fast Read Enhance Mode,
and the second FFh command is to release EQPI Mode.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN25S32
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit. The Write
Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase
(BE), Chip Erase (CE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the
instruction code, and then driving Chip Select (CS#) High.
The instruction sequence is shown in Figure 8.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 7. Write Enable Instruction Sequence Diagram
Write Disable (WRDI) (04h)
The Write Disable instruction (Figure 8) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip
Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#)
high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write
Status Register, Page Program, Sector Erase, Block Erase (BE) and Chip Erase instructions.
The instruction sequence is shown in Figure 8.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 8. Write Disable Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN25S32
Figure 8.1 Write Enable/Disable Instruction Sequence under EQPI Mode
Read Status Register (RDSR) (05h)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status
Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register
continuously, as shown in Figure 9.
The instruction sequence is shown in Figure 9.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 9. Read Status Register Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN25S32
Figure 9.1 Read Status Register Instruction Sequence under EQPI Mode
Table 7. Status Register Bit Locations
S7
SRP
Status
Register
Protect
1 = status
register write
disable
OTP_LOCK
bit
(note 1)
1 = OTP
sector is
protected
Non-volatile bit
S6
S5
S4
S3
S2
S1
WPDIS
BP3
BP2
BP1
BP0
WEL
(Block
(Block
(Block
(Block
(Write Enable
(WP# disable)
Protected bits) Protected bits) Protected bits) Protected bits)
Latch)
1 = WP#
disable
0 = WP#
enable
(note 2)
(note 2)
(note 2)
(note 2)
S0
WIP
(Write In
Progress bit)
(Note 3)
1 = write
enable
0 = not write
enable
1 = write
operation
0 = not in write
operation
volatile bit
volatile bit
Non-volatile bit Non-volatile bit. Non-volatile bit Non-volatile bit Non-volatile bit
Note
1. In OTP mode, SRP bit is served as OTP_LOCK bit.
2. See the table 3 “Protected Area Sizes Sector Organization”.
3. When executed the (RDSR) (05h) command, the WIP (S0) value is the same as WIP (S7) in table 8.
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3,
BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected
This Data Sheet may be revised by subsequent versions
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EN25S32
against Page Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect
(BP3, BP2, BP1, BP0) bits can be written and provided that the Hardware Protected mode has not
been set. The Chip Erase (CE) instruction is executed if, and only if, all Block Protect (BP3, BP2, BP1,
BP0) bits are 0.
WPDIS bit. The Write Protect disable (WPDIS) bit, non-volatile bit, when it is reset to “0” (factory
default) to enable WP# function or is set to “1” to disable WP# function (can be floating during SPI
mode.)
SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit is operated in conjunction with the
Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal
allow the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit
is set to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status
Register (SRP, BP3, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR)
instruction is no longer accepted for execution.
In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command,
the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be
programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Read Suspend Status Register (RDSSR) (09h)
The Read Suspend Status Register (RDSSR) instruction allows the Suspend Status Register to be
read. The Suspend Status Register may be read at any time, even while a Write Suspend or Write
Resume cycle is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the
Suspend Status Register continuously, as shown in Figure 10.
The instruction sequence is shown in Figure 10.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 10. Read Suspend Status Register Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN25S32
Figure 10.1 Read Suspend Status Register Instruction Sequence under EQPI Mode
Table 8. Suspend Status Register Bit Locations
S7
WIP
(Write In
Progress bit)
(Note 1)
1 = write
operation
0 = not in write
operation
volatile bit
S6
S5
S4
S3
Fail bit
index
Reserved 1 = erase or Reserved
bit
bit
program or
WRSR
failed
0 = passed
volatile bit
S2
S1
S0
WSP
WSE
WEL
(Write Suspend
Program bits)
(Write Suspend
Erase status bit)
(Write Enable
Latch)
1 = Program
suspended
0 = Program is
not suspended
1 = Erase
1 = write enable
suspended
0 = not write
0 = Erase is not
enable
suspended
volatile bit
volatile bit
Reserved
bit
volatile bit
Note:
1. When executed the (RDSSR) (09h) command, the WIP (S7) value is the same as WIP (S0) in table 7.
2. Default at Power-up is “0”
The status and control bits of the Suspend Status Register are as follows:
Reserved bit. Suspend Status register bit locations 0, 4 and 6 are reserved for future use. Current
devices will read 0 for these bit locations. It is recommended to mask out the reserved bit when testing
the Suspend Status Register. Doing this will ensure compatibility with future devices.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Suspend or Write Resume instruction is accepted.
This Data Sheet may be revised by subsequent versions
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EN25S32
WSE bit. The Write Suspend Erase Status (WSE) bit indicates when an Erase operation has been
suspended. The WSE bit is “1” after the host issues a suspend command during an Erase operation.
Once the suspended Erase resumes, the WSE bit is reset to “0”.
WSP bit. The Write Suspend Program Status (WSP) bit indicates when a Program operation has been
suspended. The WSP is “1” after the host issues a suspend command during the Program operation.
Once the suspended Program resumes, the WSP bit is reset to “0”.
Fail bit. The fail bit, volatile bit, it will latched high when erase or program or WRSR failed. It will be
reset after new embedded program and erase cycle re-stared or power on or software reset.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Suspend or
Write Resume cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in
progress.
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write
Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by
the instruction code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no
effect on S1 and S0 of the Status Register. Chip Select (CS#) must be driven High after the eighth bit of
the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose
duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may
still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect
(BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table 3. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register
Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware
Protected Mode (HPM) is entered.
The instruction sequence is shown in Figure 11.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1.
Figure 11. Write Status Register Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN25S32
Figure 11.1 Write Status Register Instruction Sequence under EQPI Mode
Read Data Bytes (READ) (03h)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the
rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum frequency fR, during the falling edge of
Serial Clock (CLK).
The instruction sequence is shown in Figure 12. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When
the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select
(CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN25S32
Figure 12. Read Data Instruction Sequence Diagram
Read Data Bytes at Higher Speed (FAST_READ) (0Bh)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory
contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a
maximum frequency FR, during the falling edge of Serial Clock (CLK).
The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select
(CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes
at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
The instruction sequence is shown in Figure 13.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
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EN25S32
Figure 13. Fast Read Instruction Sequence Diagram
Figure 13.1 Fast Read Instruction Sequence under EQPI Mode
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EN25S32
Dual Output Fast Read (3Bh)
The Dual Output Fast Read (3Bh) is similar to the standard Fast Read (0Bh) instruction except that
data is output on two pins, DQ0 and DQ1, instead of just DQ0. This allows data to be transferred from
the EN25S32 at twice the rate of standard SPI devices. The Dual Output Fast Read instruction is ideal
for quickly downloading code from to RAM upon power-up or for applications that cache codesegments to RAM for execution.
Similar to the Fast Read instruction, the Dual Output Fast Read instructions can operation at the
highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding
eight “dummy clocks after the 24-bit address as shown in Figure 14. The dummy clocks allow the
device’s internal circuits additional time for setting up the initial address. The input data during the
dummy clock is “don’t care”. However, the DI pin should be high-impedance prior to the falling edge of
the first data out clock.
Figure 14. Dual Output Fast Read Instruction Sequence Diagram
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Dual Input / Output FAST_READ (BBh)
The Dual I/O Fast Read (BBh) instruction allows for improved random access while maintaining two IO
pins, DQ0 and DQ1. It is similar to the Dual Output Fast Read (3Bh) instruction but with the capability to
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
The Dual I/O Fast Read instruction enable double throughput of Serial Flash in read mode. The
address is latched on rising edge of CLK, and data of every two bits (interleave 2 I/O pins) shift out on
the falling edge of CLK at a maximum frequency. The first address can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single Dual I/O Fast Read instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing Dual I/O Fast Read instruction, the following
address/dummy/data out will perform as 2-bit instead of previous 1-bit, as shown in Figure 15.
Figure 15. Dual Input / Output Fast Read Instruction Sequence Diagram
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EN25S32
Quad Input / Output FAST_READ (EBh)
The Quad Input/Output FAST_READ (EBh) instruction is similar to the Dual I/O Fast Read (BBh)
instruction except that address and data bits are input and output through four pins, DQ0, DQ1, DQ2 and
DQ3 and six dummy clocks are required prior to the data output. The Quad I/O dramatically reduces
instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.
The Quad Input/Output FAST_READ (EBh) instruction enable quad throughput of Serial Flash in read
mode. The address is latching on rising edge of CLK, and data of every four bits (interleave on 4 I/O
pins) shift out on the falling edge of CLK at a maximum frequency FR. The first address can be any
location. The address is automatically increased to the next higher address after each byte data is
shifted out, so the whole memory can be read out at a single Quad Input/Output FAST_READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing Quad Input/Output FAST_READ instruction, the following address/dummy/data out will perform
as 4-bit instead of previous 1-bit.
The sequence of issuing Quad Input/Output FAST_READ (EBh) instruction is: CS# goes low ->
sending Quad Input/Output FAST_READ (EBh) instruction -> 24-bit address interleave on DQ3, DQ2,
DQ1 and DQ0 -> 6 dummy clocks -> data out interleave on DQ3, DQ2, DQ1 and DQ0 -> to end Quad
Input/Output FAST_READ (EBh) operation can use CS# to high at any time during data out, as shown
in Figure 16.
The instruction sequence is shown in Figure 16.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 16. Quad Input / Output Fast Read Instruction Sequence Diagram
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EN25S32
Figure 16.1. Quad Input / Output Fast Read Instruction Sequence under EQPI Mode
Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in
random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24bit address interleave on DQ3, DQ2, DQ1 and DQ0 -> performance enhance toggling bit P[7:0] -> 4
dummy clocks -> data out interleave on DQ3, DQ2, DQ1 and DQ0 till CS# goes high -> CS# goes low
(reduce Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit random access address, as shown
in Figure 17.
In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah,
F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh)
instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. These
commands will reset the performance enhance mode. And afterwards CS# is raised or issuing FF
command (CS# goes high -> CS# goes low -> sending FFh -> CS# goes high) instead of no toggling,
the system then will escape from performance enhance mode and return to normal operation.
While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh)
instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle.
The instruction sequence is shown in Figure 17.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
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EN25S32
Figure 17. Quad Input/Output Fast Read Enhance Performance Mode Sequence Diagram
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EN25S32
Figure 17.1 Quad Input/Output Fast Read Enhance Performance Mode Sequence under EQPI Mode
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EN25S32
Set Burst (C0h)
The Set Burst command specifies the number of bytes to be output during a Read Bust command
before the device wraps around. To set the burst length the host driver CS# low, sends the Set Burst
command cycle (C0h) and one data cycle, then drivers CS# high. A cycle is two nibbles, or two clocks,
long, most significant nibble first. After power-up or reset, the burst length is set to 8 bytes (00h), please
refer to Table 9 for burst length data and Figure 18 for the sequence.
Table 9. Burst Length Data
Burst length
8 Bytes ( default)
16 Bytes
32 Bytes
64 Bytes
128 Bytes
256 Bytes
High Nibble (H0)
0h
0h
0h
0h
0h
0h
Low Nibble (L0)
0h
1h
2h
3h
4h
5h
Figure 18 Set Burst Instruction Sequence Diagram
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EN25S32
Read Burst (0Ch)
To execute a Read Burst operation the host drivers CS# low, and sends the Read Burst command
cycle (0Ch), followed by three address cycles and two dummy cycles (4 clocks). Each of cycle is
consisted of two nibbles (clocks) long, most significant nibble first,
After the dummy cycle, the device outputs data on the falling edge of the CLK signal starting from the
specific address location. The data output stream is continuous through all addresses until terminated
by a low-to high transition of CS# signal.
During Read Burst, the internal address point automatically increments until the last byte of the burst
reached, then jumps to first byte of the burst. All bursts are aligned to addresses within the bust length,
see Table 10. For example, if the burst length is 8 bytes, and the start address is 06h, the burst
sequence should be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05, 06, etc. The pattern would repeat until the
command was terminated by pulling CS# as high status.
Table 10. Burst Address Range
Burst length
8 Bytes ( default)
16 Bytes
32 Bytes
64 Bytes
128 Bytes
256 Bytes
Burst wrap (A[7:A0]) address range
00-07H, 08-0FH, 10-17H, 18-1FH...
00-0FH, 10-1FH, 20-2FH, 30-3FH...
00-1FH, 20-3FH, 40-5FH, 60-7FH...
00-3FH, 40-7FH, 80-BFH, C0-FFH
00-7FH, 80-FFH
00-FFH
Figure 19 Read Burst Instruction Sequence Diagram
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EN25S32
Page Program (PP) (02h)
The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (DI). If the 8 least
significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the same page (from the address whose 8
least significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration
of the sequence.
The instruction sequence is shown in Figure 20. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page.
Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (CS#) is driven high, the self-timed Page Program cycle (whose duration is tPP)
is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the
value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page
Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 20.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 20. Page Program Instruction Sequence Diagram
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EN25S32
Figure 20.1 Program Instruction Sequence under EQPI Mode
Write Suspend (B0h)
Write Suspend allows the interruption of Sector Erase, Block Erase or Page Program operations in
order to erase, program, or read data in another portion of memory. The original operation can be
continued with Write Resume command. The instruction sequence is shown in Figure 21.
Only one write operation can be suspended at a time; if an operation is already suspended, the device
will ignore the Write Suspend command. Write Suspend during Chip Erase is ignored; Chip Erase is
not a valid command while a write is suspended.
Suspend to suspend ready timing: 20us.
Resume to another suspend timing: 1ms.
Figure 21. Write Suspend Instruction Sequence Diagram
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EN25S32
Write Suspend During Sector Erase or Block Erase
Issuing a Write Suspend instruction during Sector Erase or Block Erase allows the host to program or
read any sector that was not being erased. The device will ignore any programming commands
pointing to the suspended sector(s). Any attempt to read from the suspended sector(s) will out put
unknown data because the Sector or Block Erase will be incomplete.
To execute a Write Suspend operation, the host drives CS# low, sends the Write Suspend command
cycle (B0h), then drives CS# high. A cycle is two nibbles long, most significant nibble first. The
Suspend Status register indicates that the erase has been suspended by changing the WSE bit from
“0” to “1”, but the device will not accept another command until it is ready. To determine when the
device will accept a new command, poll the WIP bit in the Suspend Status register or after issue
program suspend command, latency time 20us is needed before issue another command. For
“Suspend to Read”, “Resume to Read”, “Resume to Suspend” timing specification please note Figure
22.1, 22.2 and 22.3.
Write Suspend During Page Programming
Issuing a Write Suspend instruction during Page Programming allows the host to erase or read any
sector that is not being programmed. Erase commands pointing to the suspended sector(s) will be
ignored. Any attempt to read from the suspended page will output unknown data because the program
will be incomplete.
To execute a Write Suspend operation, the host drives CS# low, sends the Write Suspend command
cycle (B0h), then drives CS# high. A cycle is two nibbles long, most significant nibble first. The
Suspend Status register indicates that the programming has been suspended by changing the WSP bit
from “0” to “1”, but the device will not accept another command until it is ready. To determine when the
device will accept a new command, poll the WIP bit in the Suspend Status register or after issue
program suspend command, latency time 20us is needed before issue another command. For
“Suspend to Read”, “Resume to Read”, “Resume to Suspend” timing specification please note Figure
22.1, 22.2 and 22.3.
The instruction sequence is shown in Figure 23.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 22.1 Suspend to Read Latency
Figure 22.2 Resume to Read Latency
Figure 22.3 Resume to Suspend Latency
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EN25S32
Write Resume (30h)
Write Resume restarts a Write command that was suspended, and changes the suspend status bit in
the Suspend Status register (WSE or WSP) back to “0”.
The instruction sequence is shown in Figure 23. To execute a Write Resume operation, the host drives
CS# low, sends the Write Resume command cycle (30h), then drives CS# high. A cycle is two nibbles
long, most significant nibble first. To determine if the internal, self-timed Write operation completed, poll
the WIP bit in the Suspend Status register, or wait the specified time tSE, tBE or tPP for Sector Erase,
Block Erase, or Page Programming, respectively. The total write time before suspend and after resume
will not exceed the uninterrupted write times tSE, tBE or tPP. Resume to another suspend operation
requires latency time of 1ms.
The instruction sequence is shown in Figure 23.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 23. Write Resume Instruction Sequence Diagram
Figure 23.1 Write Suspend/Resume Instruction Sequence under EQPI Mode
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Figure 24. Write Suspend/Resume Flow
Note:
1. The ‘WIP’ can be either checked by command ‘09’or ‘05’ polling.
2. ‘Wait for write cycle’ can be referring to maximum write cycle time or polling the WIP.
3. ‘Wait for suspend latency’, after issue program suspend command, latency time 20us is needed
before issue another command or polling the WIP.
4. The ‘WES’ and ‘WSE’ can be checked by command ‘09’ polling.
5. ‘Suspend done’ means the chip can do further operations allowed by suspend spec.
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EN25S32
Sector Erase (SE) (20h)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector (see
Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low
for the entire duration of the sequence.
The instruction sequence is shown in Figure 25. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 26.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 25. Sector Erase Instruction Sequence Diagram
64KB Block Erase (BE) (D8h)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Block Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Block (see
Table 2) is a valid address for the Block Erase (BE) instruction. Chip Select (CS#) must be driven Low
for the entire duration of the sequence.
The instruction sequence is shown in Figure 26. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Block Erase (BE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a block which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
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EN25S32
The instruction sequence is shown in Figure 26.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 26. Block Erase Instruction Sequence Diagram
Figure 26.1 Block/Sector Erase Instruction Sequence under EQPI Mode
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EN25S32
Chip Erase (CE) (C7h/60h)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Chip Erase (CE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 27. Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Chip Erase instruction is not executed. As
soon as Chip Select (CS#) is driven High, the self-timed Chip Erase cycle (whose duration is tCE) is
initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if all Block Protect (BP3, BP2, BP1, BP0) bits are 0.
The Chip Erase (CE) instruction is ignored if one, or more blocks are protected.
The instruction sequence is shown in Figure 27.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 27. Chip Erase Instruction Sequence Diagram
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Figure 27.1 Chip Erase Sequence under EQPI Mode
Deep Power-down (DP) (B9h)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection
mechanism, while the device is not in active use, since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (CS#) High deselects the device, and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep
Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce
the standby current (from ICC1 to ICC2, as specified in Table 13.)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down and Read Device ID (RDI) instruction. This releases the device from
this mode. The Release from Deep Power-down and Read Device ID (RDI) instruction also allows the
Device ID of the device to be output on Serial Data Output (DO).
The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in
the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 28. Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not
executed. As soon as Chip Select (CS#) is driven High, it requires a delay of tDP before the supply
current is reduced to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
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EN25S32
Figure 28. Deep Power-down Instruction Sequence Diagram
Release from Deep Power-down and Read Device ID (RDI)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down and Read Device ID (RDI) instruction. Executing this instruction takes
the device out of the Deep Power-down mode.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature
that is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for
reasons of backward compatibility, only, and should not be used for new designs. New designs should,
instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction.
When used only to release the device from the power-down state, the instruction is issued by driving
the CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 29. After
the time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other
instructions will be accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device
ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 30. The Device ID value for the EN25S32 are listed in Table 6. The Device ID can be read
continuously. The instruction is completed by driving CS# high.
When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device
was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is
immediate. If the device was previously in the Deep Power-down mode, though, the transition to the
Standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2
(max), as specified in Table 15. Once in the Stand-by Power mode, the device waits to be selected, so
that it can receive, decode and execute instructions.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep
Power-down and Read Device ID (RDI) instruction always provides access to the 8bit Device ID of the
device, and can be applied even if the Deep Power-down mode has not been entered.
Any Release from Deep Power-down and Read Device ID (RDI) instruction while an Erase, Program or
Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
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Figure 29. Release Power-down Instruction Sequence Diagram
Figure 30. Release Power-down / Device ID Instruction Sequence Diagram
Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device
ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code
“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Eon (1Ch)
and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in Figure 31. The Device ID values for the EN25S32 are listed in Table 6. If the 24-bit address is
initially set to 000001h the Device ID will be read first
The instruction sequence is shown in Figure 31.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
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©2004 Eon Silicon Solution, Inc.,
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www.eonssi.com
EN25S32
Figure 31. Read Manufacturer / Device ID Diagram
Figure 31.1. Read Manufacturer / Device ID Diagram under EQPI Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
45
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
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EN25S32
Read Identification (RDID) (9Fh)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read,
followed by two bytes of device identification. The device identification indicates the memory type in the
first byte , and the memory capacity of the device in the second byte .
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) instruction
should not be issued while the device is in Deep Power down mode.
The device is first selected by driving Chip Select Low. Then, the 8-bit instruction code for the
instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being
shifted out on Serial Data Output , each bit being shifted out during the falling edge of Serial Clock .
The instruction sequence is shown in Figure 32. The Read Identification (RDID) instruction is
terminated by driving Chip Select High at any time during data output.
When Chip Select is driven High, the device is put in the Standby Power mode. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
The instruction sequence is shown in Figure 32.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 32. Read Identification (RDID)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
46
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
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EN25S32
Figure 32.1. Read Identification (RDID) under EQPI Mode
Enter OTP Mode (3Ah)
This Flash has an extra 512 bytes OTP sector, user must issue ENTER OTP MODE command to read,
program or erase OTP sector. After entering OTP mode, the OTP sector is mapping to sector 1023,
SRP bit becomes OTP_LOCK bit and can be read with RDSR command. Program / Erase command
will be disabled when OTP_LOCK bit is ‘1’
WRSR command will ignore the input data and program OTP_LOCK bit to 1.
User must clear the protect bits before enter OTP mode.
OTP sector can only be program and erase before OTP_LOCK bit is set to ‘1’ and BP [3:0] = ‘0000’ In
OTP mode, user can read other sectors, but program/erase other sectors only allowed when
OTP_LOCK bit equal to ‘0’.
User can use WRDI (04H) command to exit OTP mode.
Erase OTP Command (20h)
User can use Sector Erase (20h) command only to erase OTP data.
The instruction sequence is shown in Figure 33.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Table 11. OTP Sector Address
Sector
Sector Size
Address Range
1023
512 byte
3FF000h – 3FF1FFh
Note: The OTP sector is mapping to sector 1023
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
47
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
Figure 33. Enter OTP Mode
Figure 33.1 Enter OTP Mode Sequence under EQPI Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
48
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
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EN25S32
Power-up Timing
All functionalities and DC specifications are specified for a VCC ramp rate of greater than 1V per 100 ms
(0V to 1.65V in less than 270 ms). See Table 12 and Figure 34 for more information.
Figure 34. Power-up Timing
Table 12. Power-Up Timing
Symbol
TPU-READ
(1)
TPU-WRITE
(1)
Parameter
Min.
Unit
VCC Min to Read Operation
100
µs
VCC Min to Write Operation
100
µs
Note:
1. This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh).
The Status Register contains 00h (all Status Register bits are 0).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
49
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
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EN25S32
Table 13. DC Characteristics
(Ta = - 40°C to 85°C; VCC = 1.65-1.95V)
Symbol
ILI
Parameter
Test Conditions
Min.
Input Leakage Current
ILO
Output Leakage Current
ICC1
Standby Current
ICC2
Deep Power-down Current
ICC3
Operating Current (READ)
CS# = VCC, VIN = VSS or VCC
CS# = VCC, VIN = VSS or VCC
CLK = 0.1 VCC / 0.9 VCC at
104MHz, DQ = open
CLK = 0.1 VCC / 0.9 VCC at
80MHz, DQ = open
CS# = VCC
ICC4
Operating Current (PP)
ICC5
Operating Current (WRSR)
ICC6
ICC7
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 100 µA, Vcc=Vcc Min.
VOH
Output High Voltage
IOH = –100 µA , Vcc=Vcc Min.
Max.
Unit
2
µA
2
µA
10
µA
5
µA
20
mA
25
mA
30
mA
15
mA
Operating Current (SE)
CS# = VCC
CS# = VCC
15
mA
Operating Current (BE)
CS# = VCC
15
mA
– 0.5
0.2 VCC
V
0.7VCC
VCC+0.4
V
0.3
V
VCC-0.2
V
Table 14. AC Measurement Conditions
Symbol
CL
Parameter
Min.
Max.
Load Capacitance
30
Input Rise and Fall Times
Unit
pF
5
ns
Input Pulse Voltages
0.2VCC to 0.8VCC
V
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
VCC / 2
V
Output Timing Reference Voltages
Figure 35. AC Measurement I/O Waveform
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
50
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
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EN25S32
Table 15. AC Characteristics
(Ta = - 40°C to 85°C; VCC = 1.65-1.95V)
Symbol
Alt
FR
fC
fR
tCH 1
tCL1
tCLCH
Parameter
Serial Clock Frequency for:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, WRSR, Fast Read Burst
Serial Clock Frequency for: Read Burst, Dual
Output Fast Read and Quad I/O Fast Read
Serial Clock Frequency for READ, RDSR,
RDSSR, RDID
Serial Clock High Time
Min
Max
Unit
D.C.
104
MHz
D.C.
80
MHz
D.C.
50
MHz
Serial Clock Low Time
2
Typ
6
ns
6
ns
Serial Clock Rise Time (Slew Rate)
0.1
V / ns
Serial Clock Fall Time (Slew Rate)
0.1
V / ns
CS# Active Setup Time
5
ns
tCHSH
CS# Active Hold Time
5
ns
tSHCH
CS# Not Active Setup Time
5
ns
tCHSL
CS# Not Active Hold Time
CS# High Time for read
CS# High Time for program/erase
Output Disable Time
5
30
40
ns
tCHCL 2
tSLCH
tCSS
tSHSL
tSHQZ
tCSH
2
tDIS
ns
6
ns
tCLQX
tHO
Output Hold Time
0
ns
tDVCH
tDSU
Data In Setup Time
2
ns
tCHDX
tDH
Data In Hold Time
5
ns
tCLQV
tV
Output Valid from CLK
8
ns
tWHSL3
Write Protect Setup Time before CS# Low
20
ns
tSHWL3
Write Protect Hold Time after CS# High
100
ns
tDP
2
CS# High to Deep Power-down Mode
3
µs
3
µs
1.8
µs
tW
CS# High to Standby Mode without Electronic
Signature read
CS# High to Standby Mode with Electronic
Signature read
Write Status Register Cycle Time
20
50
ms
tPP
Page Programming Time
0.7
5
ms
tSE
0.3
s
tRES1 2
tRES2 2
Sector Erase Time
0.04
tBE
64KB Block Erase Time
0.3
2
s
tCE
Chip Erase Time
17
50
s
WIP = write operation
28
µs
WIP = not in write operation
0
µs
tSR
Software Reset
Latency
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
51
©2004 Eon Silicon Solution, Inc.,
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EN25S32
Figure 36. Serial Output Timing
Figure 37. Input Timing
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
52
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
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EN25S32
ABSOLUTE MAXIMUM RATINGS
Stresses above the values so mentioned above may cause permanent damage to the device. These
values are for a stress rating only and do not imply that the device should be operated at conditions up
to or above these values. Exposure of the device to the maximum rating values for extended periods of
time may adversely affect the device reliability.
Parameter
Value
Unit
Storage Temperature
-65 to +150
°C
Plastic Packages
-65 to +125
°C
Output Short Circuit Current1
200
mA
Input and Output Voltage
(with respect to ground) 2
-0.5 to Vcc+0.5
V
Vcc
-0.5 to Vcc+0.5
V
Notes:
1.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of
up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V.
During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods up to 20ns. See figure below.
RECOMMENDED OPERATING RANGES 1
Parameter
Value
Ambient Operating Temperature
Industrial Devices
-40 to 85
Operating Supply Voltage
Vcc
Full: 1.65 to 1.95
Unit
°C
V
Notes:
1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
Maximum Negative Overshoot Waveform
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Maximum Positive Overshoot Waveform
53
©2004 Eon Silicon Solution, Inc.,
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EN25S32
Table 16. DATA RETENTION and ENDURANCE
Parameter Description
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
-40 to 85 °C
100k
cycles
Data Retention Time
Erase/Program Endurance
Table 17. CAPACITANCE
( VCC = 1.65-1.95V)
Parameter Symbol
Parameter Description
Test Setup
Max
Unit
CIN
Input Capacitance
VIN = 0
Typ
6
pF
COUT
Output Capacitance
VOUT = 0
8
pF
Note : Sampled only, not 100% tested, at TA = 25°C and a frequency of 20MHz.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
54
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
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EN25S32
PACKAGE MECHANICAL
Figure 38. VSOP 200 mil ( Official name = 208 mil )
SYMBOL
A
A1
A2
D
E
E1
e
b
L
MIN.
-0.05
0.75
5.18
7.70
5.18
--0.35
0.5
DIMENSION IN MM
NOR
-0.10
0.80
5.28
7.90
5.28
1.27
0.42
0.65
MAX
1.00
0.15
0.85
5.38
8.10
5.38
--0.48
0.80
θ
0
-10
Note : 1. Coplanarity: 0.1 mm
2. Max. allowable mold flash is 0.15 mm
at the pkg ends, 0.25 mm between leads.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
55
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
Figure 39. VDFN8 ( 5x6mm )
DIMENSION IN MM
MIN.
NOR
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.04
A2
--0.20
--D
5.90
6.00
6.10
E
4.90
5.00
5.10
D2
3.30
3.40
3.50
E2
3.90
4.00
4.10
e
--1.27
--b
0.35
0.40
0.45
L
0.55
0.60
0.65
Note: 1. Coplanarity: 0.1 mm
SYMBOL
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
56
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
Purpose
Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on
ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the
compositions of the ICs. Eon is still keeping the promise of quality for all the products with the
same as that of Eon delivered before. Please be advised with the change and appreciate your
kindly cooperation and fully support Eon’s product family.
Eon products’ Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX
Lot Number: XXXXX
Date Code:
XXXXX
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
57
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com
EN25S32
ORDERING INFORMATION
EN25S32
-
104
R
I
P
PACKAGING CONTENT
P = RoHS compliant
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
PACKAGE
R = 8-pin 200mil VSOP
W = 8-pin VDFN (5x6mm)
SPEED
104 = 104 MHz
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
25S = 1.8V Serial Flash with 4KB Uniform-Sector
32 = 32 Megabit (4096K x 8)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
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EN25S32
Revisions List
Revision No Description
Date
A
B
2010/06/24
2010/07/19
C
D
E
F
G
H
I
J
Initial Release
Revise the description of Reset Quad I/O (FFh) command on page 16.
1. Rename 38h command from Enable Quad I/O (EQIO) to Enable
Quad Peripheral Interface mode (EQPI).
2. Revise the description of RSTQIO (FFh) and add the function of
Release Quad I/O Fast Read Enhancement Mode.
3. Add Read Burst (0Dh) command on page 13 and 34.
4. Update Table 15. AC Characteristics on page 52.
Add package option of 8-pin 200mil VSOP
1. Add 32KB Block and related descriptions.
2. Revise tSHSL (CS# High Time for read) from 10ns to 30ns and update
tCLQV from 9ns to 8ns on page 52.
1. Correct the typo of 6 dummy clocks on page 28.
2011/01/03
2011/02/08
2011/02/21
2011/05/26
2. Update Figure 24. Write Suspend/Resume Flow on page 39.
1. Add the note “5. This flow cannot release the device from Deep power
down mode.” on page 16.
2011/06/28
2. Update Table 15. AC Characteristics on page 52.
Remove the 8-pin 200mil SOP package option.
2011/07/06
Supplement the description of suspend and resume latency timing on
2011/12/15
page 36, 37, 38 and 39.
1. Remove 32KB blocks and relative description.
2. Remove Fast Read Burst with wrap (0Dh) command and relative 2012/01/19
description.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
59
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com