UCC5630 Low Voltage Differential (LVD/SE) SCSI 9 Line Terminator FEATURES DESCRIPTION • Auto Selection Multi-Mode Single Ended or Low Voltage Differential Termination The UCC5630 Multi-Mode Low Voltage Differential and Single Ended Terminator is both a single ended terminator and a low voltage differential terminator for the transition to the next generation SCSI Parallel Interface (SPI-2). The low voltage differential is a requirement for the higher speeds at a reasonable cost and is the only way to have adequate skew budgets. The transceivers can be incorporated into the controller, unlike SCSI high power differential (EIA485) which requires external transceivers. Low Voltage differential is specified for Fast-40 and Fast-80, but has the potential of speeds up to Fast-320. The UCC5630 is SPI-2, SPI and Fast-20 compliant. Consult SSOP-36 and LQFP-48 Package Diagram for exact dimensions. • 2.7V to 5.25V Operation • Differential Failsafe Bias • Thermal Packaging for Low Junction Temperature and Better MTBF • Master/Slave Inputs • Supports Active Negation The UCC5630 can not be used with SCSI high voltage differential (HVD) EIA485. It will shut down when it sees high power differential to protect the bus. The pinning for high power differential is not the same as LVD or single ended and the bias voltage, current and power are also different for EIA485 differential. • Standby (Disable Mode) 5µA • 3pF Channel Capacitance BLOCK DIAGRAM SOURCE ONLY FROM TRMPWR AND THE ENABLED TERMINATORS SOURCE 5 < 15mA SINK 200µA MAXIMUM (NOISE LOAD) TRMPWR 36 +VDD OPEN CIRCUIT ON POWER OFF OR OPEN CIRCUIT IN A DISABLED TERMINATOR MODE REEF 1.3V 20 MSTR/SLV 19 1.3V ± –0.1V DIFFSENS 35 2.2 > 1.9V HIPD DIFFB 20k 21 0.1µF 0.7 > 0.6V LOW FREQUENCY FILTER 50Hz – 60Hz REF 2.7V 125 +50mV TO +62.5mV HS/GND 9 33 SE 5 L1– 4 L1+ 32 L9– 31 L9+ 52 REF 1.25V 8 LVD 110 SOURCE/SINK REGULATOR HS/GND 34 HIGH IMPEDANCE RECEIVER EVEN WITH POWER OFF 52 110 HS/GND 10 HS/GND 26 125 +50mV TO +62.5mV HS/GND 27 52 HS/GND 28 52 GND 18 SWITCHES UP ARE SINGLE ENDED SWITCHES DOWN ARE LOW VOLTAGE DIFFERENTIAL DISCNCT 17 SE GND SWITCH REG 1 MWP 36 PINOUT 4.7µF Circuit Design Patented 01/99 UDG-98049 UCC5630 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAM TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . 0V to TRMPWR Package Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 2W Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C SSOP-36 (Top View) MWP Package All voltages are with respect to PIN1. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Databook for thermal limitations and considerations of packages. LQFP-48 (Top View) FQP Package HS/GND HS/GND L6+ HS GND HS GND N/C L6– L7+ L7– DIFFB DIFSENS MSTR/SLV 12 11 10 9 8 7 6 5 4 3 2 1 L8+ 13 48 GND L8– 14 47 DISCNCT L9+ 15 46 L5– L9– 16 45 L5+ HS/GND 17 44 HS/GND HS/GND 18 43 HS/GND HS/GND 19 42 HS/GND SE 20 41 L4– LVD 21 40 L4+ HIPD 22 39 L3– TERMPWR 23 38 L3+ 37 NC NC 24 25 26 27 28 29 30 31 32 33 34 35 REG 1 36 N/C 2 35 HIPD N/C 3 34 LVD L1+ 4 33 SE L1– 5 32 L9– L2+ 6 31 L9+ L2– 7 30 L8– HS/GND 8 29 L8+ HS/GND 9 28 HS/GND HS/GND 10 27 HS/GND L3+ 11 26 HS/GND L3– 12 25 L7– L4+ 13 24 L7+ L4– 14 23 L6– L5+ 15 22 L6+ L5– 16 21 DIFF B DISCNCT 17 20 DIFSENS GND 18 19 MSTR/SLV TRMPWR 36 NC REG NC NC HS/GND L2– HS/GND HS/GND RECOMMENDED OPERATING CONDITIONS TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . 2.7V TO 5.25V L2+ L1– L1+ HS/GND ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C, TRMPWR = 3.3V. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TRMPWR Supply Current Section TRMPWR Supply Current Disable Terminator, in DISCNCT mode. 20 mA 35 µA Regulator Section 1.25V Regulator LVD Mode 1.15 1.25 1.25V Regulator Source Current LVD Mode, Differential Sense Floating –80 –100 1.25V Regulator Sink Current LVD Mode, Differential Sense Floating 80 100 1.3V Regulator DIFSENS 1.2 1.3 1.3V Regulator Source Current DIFSENS 1.3V Regulator Sink Current DIFSENS 2 1.35 V mA mA 1.4 V –5 –15 mA 50 200 µA UCC5630 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C, TRMPWR = 3.3V. MIN TYP 2.7V Regulator PARAMETER Single Ended Mode TEST CONDITIONS 2.5 2.7 MAX UNITS 3 2.7V Regulator Source Current Single Ended Mode –200 –400 –800 mA 2.7V Regulator Sink Current Single Ended Mode 100 200 400 mA 2.7V Regulator Dropout Voltage VTRMPWR – (VREG – 2.7 Min) 200 mV Ω V Differential Termination Section Differential Impedance 100 105 110 Common Mode Impedance 110 125 165 Ω 125 mV 3.5 pF 117.7 Ω Differential Bias Voltage Drivers Tri-stated 100 Common Mode Bias Output Capacitance 1.25 Single Ended Measurement to Ground (Note 1) V Single Ended Termination Section Impedance Termination Current Signal Level 0.2V 102.3 110 –21 –23 Signal Level 0.5V Output Leakage Disabled, TRMPWR = 0V to 5.25V Output Capacitance Single Ended Measurement to Ground (Note 1) Single Ended GND SW Impedance –25.4 mA –22.4 mA 400 nA 3 pF 60 Ω Disconnect (DISCNCT) Input Section DISCNCT Threshold DISCNCT Input Current VDISCNCT = 0V and 3.3V 0.8 2.0 V –30 30 µA 0.6 0.7 V Differential Sense (DIFFB) Input Sections DIFFB Single Ended Threshold DIFFB Sense LVDS Threshold 1.9 2.2 V –30 30 µA MSTR/SLV Threshold 0.8 2 V MSTR/SLV Input Current –30 30 µA DIFFB Input Current VDIFFB = 0V and 3.3V Master/Slave (MSTR/SLV) Input Section Status Bits (SE, LVD, HIPD) Output Section ISOURCE VLOAD = 2.4V –4 –8.7 mA ISINK VLOAD = 0.5V 3 6 mA VLOAD = 0.4V 2 5 mA Note 1: Guaranteed by design. Not 100% tested in production. PIN DESCRIPTIONS DIFFB: DIFSENS filter pin should be connected to a 0.1µF capacitor to GND and 20k resistor to SCSI/Bus DIFSENS Line. is in shutdown. (Not valid in disconnect mode.) DIFSENS: The SCSI bus DIFSENS line is driven to 1.3V to detect what type of devices are connected to the SCSI bus. GND: Power Supply Return. HS/GND: Heat Sink GND. Connect to large area PC board traces to increase power dissipation capability. L1– thru L9–: Signal line/active line for single ended or negative line in differential applications for the SCSI bus. DISCNCT: Disconnect shuts down the terminator when it is not at the ended of the bus. The disconnect pin low enables the terminator. L1+ thru L9+: Ground line for single ended or positive line for differential applications for the SCSI bus. LVD: TTL compatible status bit indicating low voltage differential level on DIFFB. The terminator is in LVD mode.(Not valid in disconnect mode.) HIPD: TTL compatible status bit indicating high voltage differential has been detected on DIFFB. The terminator 3 UCC5630 PIN DESCRIPTIONS (cont.) MSTR/SLV: Mode select for the non-controlling terminator. MSTR enables the 1.3V regulator, when the terminator is enabled. Note: Theis function will be removed on further generations of the multimode terminators. capacitor. REG: Regulator bypass, must be connected to a 4.7µF TRMPWR: VIN 2.7V to 5.25V supply. SE: TTL compatible status bit indicating single ended device has been detected on DIFFB. The terminator is in single ended mode. APPLICATION INFORMATION TERMPWR 36 TERMPWR TERMPWR 36 CONTROL LINES 19 MSTR/SLV 17 DISCNCT DIFFSENSE 20 20 DIFFSENSE DIFFB DIFF B REG 1 21 21 1 20k 20k 0.1µF . 0.1µF . 36 TERMPWR 4.7µF TERMPWR 36 DATA LINES (9) 19 MSTR/SLV 4.7µF . DISCNCT 17 REG 4.7µF . TERMPWR CONTROL LINES MSTR/SLV 19 DATA LINES (9) MSTR/SLV 19 17 DISCNCT DISCNCT 17 REG DIFF B DIFFB REG 1 21 21 1 4.7µF . 4.7µF . 4.7µF 36 TERMPWR TERMPWR 36 DATA LINES (9) 19 MSTR/SLV DATA LINES (9) MSTR/SLV 19 17 DISCNCT DISCNCT 17 REG DIFFB DIFFB REG 1 21 21 1 4.7µF . 4.7µF UDG-96211 The master is selected by placing TRMPWR on MSTR/SLV and the terminator enabled by grounding DISCNCT, enabling the 1.3V regulator. The master is the only terminator connected directly to DIFSENS bus line, all the other terminators receive the mode signal by connecting the DIFFB pins together. Balancing capacitor is very important in high speed operation. The typical balance between the positive (+) and negative (–) signals is 0.1pF except for L8 and L9, 0.23pF and 0.4pF respecitvely on the MWP package. The negative (–) signal has higher capacitance than the positive (+) signal. The FQP package is typically 0.2pF less than the MWP. Typical balance is 0.1pF except for L8 and L3, where it is 0.4pF. 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