TI TPS2320

TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
features
D
D
D
D
D
D
D
D
D
D OR PW PACKAGE
(TOP VIEW)
Dual-Channel High-Side MOSFET Drivers
1
16
DISCH1
GATE1
IN1: 3 V to 13 V; IN2: 3 V to 5.5 V
2
15
DISCH2
GATE2
Inrush Current Limiting With dv/dt Control
3
14
ENABLE
DGND
Independent Circuit-Breaker Control With
4
13
TIMER
FAULT
Programmable Current Limit and Transient
5
12
VREG
ISET1
Timer
6
11
AGND
ISET2
7
10
ISENSE2
IN2
CMOS- and TTL-Compatible Enable Input
8
9
ISENSE1
IN1
Low, 5-µA Standby Supply Current . . . Max
Available in 16-Pin SOIC and TSSOP
NOTE: Terminal 14 is active high on TPS2321.
Package
– 40°C to 85°C Ambient Temperature Range
typical application
Electrostatic Discharge Protection
VO1
applications
D
D
D
+
V1
Hot-Swap/Plug/Dock Power Management
Hot-Plug PCI, Device Bay
Electronic Circuit Breaker
3 V – 13 V
IN1
ISET1
DISCH1
ISENSE1 GATE1
VREG
AGND
description
TPS2320
DGND
The TPS2320 and TPS2321 are dual-channel
hot-swap controllers that use external N-channel
MOSFETs as high-side switches in power
applications. Features of these devices, such as
overcurrent protection (OCP), inrush-current
control, and separation of load transients from
actual load increases, are critical requirements for
hot-swap applications.
FAULT
TIMER
ENABLE
IN2
ISET2
ISENSE2
GATE2
DISCH2
VO2
+
V2
3 V – 5.5 V
The TPS2320/21 devices incorporate undervoltage lockout (UVLO) to ensure the device is off at startup. Each
internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully
enhance the N-channel MOSFETs. The charge pumps control both the rise times and fall times (dv/dt) of the
MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the
ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have
high peak currents during power-state transitions, to disregard transients for a programmable period.
AVAILABLE OPTIONS
TA
– 40°C to 85°C
PACKAGES
PIN
COUNT
ENABLE
ENABLE
Dual-channel with independent OCP and adjustable PG
20
TPS2300IPW
TPS2301IPW
Dual-channel with interdependent OCP and adjustable PG
20
TPS2310IPW
TPS2311IPW
Dual-channel with independent OCP
16
TPS2320ID
TPS2320IPW
TPS2321ID
TPS2321IPW
Single-channel with OCP and adjustable PG
14
TPS2330ID
TPS2330IPW
TPS2331ID
TPS2331IPW
HOT SWAP CONTROLLER DESCRIPTION
HOT-SWAP
† The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2321IPWR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
functional block diagram
IN1
ISET1
ISENSE1
GATE1
PREREG
VREG
DISCH1
Clamp
dv/dt Rate
Protection
50 µA
Circuit
Breaker
Charge
Pump
Pulldown FET
Circuit Breaker
UVLO and
Power-Up
AGND
75 µA
DGND
ENABLE
FAULT
Logic
50-µs Deglitch
TIMER
Second Channel
IN2
ISET2
ISENSE2 GATE2
DISCH2
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
6
I
Analog ground, connects to DGND as close as possible
DGND
3
I
Digital ground
DISCH1
16
O
Discharge transistor 1
DISCH2
15
O
Discharge transistor 2
ENABLE/ ENABLE
14
I
Active low (TPS2320) or active high enable (TPS2321)
FAULT
13
O
Overcurrent fault, open-drain output
GATE1
1
O
Connects to gate of channel 1 high-side MOSFET
GATE2
2
O
Connects to gate of channel 2 high-side MOSFET
IN1
9
I
Input voltage for channel 1
IN2
10
I
Input voltage for channel 2
ISENSE1
8
I
Current-sense input channel 1
ISENSE2
7
I
Current-sense input channel 2
ISET1
12
I
Adjusts circuit-breaker threshold with resistor connected to IN1
ISET2
11
I
Adjusts circuit-breaker threshold with resistor connected to IN2
TIMER
4
O
Adjusts circuit-breaker deglitch time
VREG
5
O
Connects to bypass capacitor, for stable operation
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
detailed description
DISCH1, DISCH2 – DISCH1 and DISCH2 should be connected to the sources of the external N-channel
MOSFET transistors connected to GATE1 and GATE2, respectively. These pins discharge the loads when the
MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate
voltage-clamp circuitry.
ENABLE or ENABLE – ENABLE for TPS2320 is active low. ENABLE for TPS2321 is active high. When the
controller is enabled, both GATE1 and GATE2 voltages will power up to turn on the external MOSFETs. When
the ENABLE pin is pulled high for TPS2320 or the ENABLE pin is pulled low for TPS2321 for more than 50 µs,
the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to
discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see
VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than
5 µA.
FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is
sustained long enough to charge TIMER to 0.5 V, the overcurrent channel latches off and pulls FAULT low. The
other channel will run normally if not in overcurrent.
GATE1, GATE2 – GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When
the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15 µA to
each. The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If
desired, the turnon slew rates can be further reduced by connecting capacitors between these pins and ground.
These capacitors also reduce inrush current and protect the device from false overcurrent triggering during
powerup. The charge-pump circuitry will generate gate-to-source voltages of 9 V–12 V across the external
MOSFET transistors.
IN1, IN2 – IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET
transistors connected to GATE1 and GATE2, respectively. The TPS2320/TPS2321 draws its operating current
from IN1, and both channels will remain disabled until the IN1 power supply has been established. The IN1
channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been
constructed to support 3-V or 5-V operation
ISENSE1, ISENSE2, ISET1, ISET2 – ISENSE1 and ISENSE2, in combination with ISET1 and ISET2,
implement overcurrent sensing for GATE1 and GATE2. ISET1 and ISET2 set the magnitude of the current that
generates an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current
source draws 50 µA from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2,
which is also connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load
current. An overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled
below ISET2.
TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning
off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which
charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker
latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled
to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly
recommended from TIMER to ground, to prevent any false triggering.
VREG – The VREG pin is the output of an internal low-dropout voltage regulator. This regulator draws current
from IN1. A 0.1-µF ceramic capacitor should be connected between VREG and ground. VREG can be
connected to IN1, IN2, or to a separated power supply through a low-resistance resistor. However, the voltage
on VREG must be less than 5.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Input voltage range: VI(IN1), VI(ISENSE1), VI(ISET1), VI(ENABLE) . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
VI(IN2), VI(ISENSE2), VI(ISET2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Output voltage range: VO(GATE1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V
VO(GATE2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 22V
VO(DISCH1), VO(FAULT), VO(VREG), VO(DISCH2), VO(TIMER), . . . . . –0.3 V to 15V
Sink current range: IGATE1, IGATE2, IDISCH1, IDISCH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 100 mA
ITIMER, IFAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 10 mA
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are respect to DGND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PW-16
823 mW
10.98 mW/°C
329 mW
165 mW
D-16
674 mW
8.98 mW/°C
270 mW
135 mW
recommended operating conditions
MIN
Input voltage
voltage, VI
VI(IN1), VI(ISENSE1), VI(ISET1)
VI(IN2), VI(ISENSE2), VI(ISET2)
NOM
MAX
3
13
3
5.5
UNIT
V
VREG voltage, VO(VREG), when VREG is directly connected to IN1
2.95
5.5
V
Operating virtual junction temperature, TJ
–40
100
°C
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
electrical characteristics over recommended operating temperature range (–40°C < TA < 85°C),
3 V ≤ VI(IN1) ≤13 V, 3 V ≤ VI(IN2) ≤ 5.5 V (unless otherwise noted)
general
PARAMETER
II(IN1)
II(IN2)
II(stby)
TEST CONDITIONS
Input current, IN1
MIN
VI(ENABLE) = 5 V (TPS2321),
VI(ENABLE) = 0 V (TPS2320)
Input current, IN2
Standby
y current ((sum of currents into IN1, IN2,
ISENSE1, ISENSE2, ISET1, and ISET2)
TYP
MAX
UNIT
0.5
1
mA
75
200
µA
5
µA
VI(ENABLE) = 0 V (TPS2321),
VI(ENABLE) = 5 V (TPS2320)
GATE1
PARAMETER
TEST CONDITIONS
VG(GATE1_3V)
VG(GATE1_4.5V)
nA
II(GATE1) = 500 nA,
DISCH1 o
open
en
Gate voltage
VG(GATE1_10.8V)
MIN
TYP
9
11.5
VI(IN1) = 4.5 V
10.5
14.5
VI(IN1) = 10.8 V
16.8
21
9
10
12
V
VI(IN1) = 3 V
MAX
UNIT
V
VC(GATE1)
Clamping voltage, GATE1
to DISCH1
IS(GATE1)
Source current, GATE1
3 V ≤ VI(IN1) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE1) = VI(IN1) + 6 V
10
14
20
µA
Sink current, GATE1
3 V ≤ VI(IN1) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE1) = VI(IN1)
50
75
100
µA
tr(GATE1)
(
)
Rise time, GATE1
Cg to GND = 1 nF (see Note 2)
VI(IN1) = 3 V
VI(IN1) = 4.5 V
0.5
tf(GATE1)
(
)
Fall time, GATE1
Cg to GND = 1 nF (see Note 2)
ms
0.6
VI(IN1) = 10.8 V
VI(IN1) = 3 V
1
0.1
VI(IN1) = 4.5 V
VI(IN1) = 10.8 V
ms
0.12
0.2
GATE2
PARAMETER
VG(GATE2_3V)
Gate voltage
VG(GATE2_4.5V)
TEST CONDITIONS
nA DISCH2 o
open
II(GATE2) = 500 nA,
en
VI(IN2) = 3 V
VI(IN2) = 4.5 V
MIN
TYP
9
11.7
MAX
UNIT
10.5
14.7
9
10
12
V
V
VC(GATE2)
Clamping voltage,
GATE2 to DISCH2
IS(GATE2)
Source current,
GATE2
3 V ≤ VI(IN2) ≤ 5.5 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE2) = VI(IN2) + 6 V
10
14
20
µA
Sink current, GATE2
3 V ≤ VI(IN2) ≤ 5.5 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
VI(GATE2) = VI(IN2)
50
75
100
µA
tr(GATE2)
(GATE2)
Rise time
time, GATE2
Cg to GND = 1 nF
(see Note 2)
VI(IN2) = 3 V
VI(IN2) = 4.5 V
tf(GATE2)
Fall time
time, GATE2
Cg to GND = 1 nF
(see Note 2)
VI(IN2) = 3 V
VI(IN2) = 4.5 V
0.5
VO(VREG) = 3 V
0.6
0.1
0.12
ms
ms
NOTE 2: Specified, but not production tested.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
electrical characteristics over recommended operating temperature range (–40°C < TA < 85°C),
3 V ≤ VI(IN1) ≤13 V, 3 V ≤ VI(IN2) ≤ 5.5 V ( unless otherwise noted) (continued)
TIMER
PARAMETER
VOT(TIMER)
TEST CONDITIONS
Threshold voltage, TIMER
Charge current, TIMER
VI(TIMER) = 0 V
VI(TIMER) = 1 V
Discharge current, TIMER
MIN
TYP
MAX
0.4
0.5
0.6
UNIT
35
50
65
1
2.5
MIN
TYP
MAX
50
60
mV
0.1
5
µA
V
µA
mA
circuit breaker
PARAMETER
VIT(CB)
IIB(ISENSEx)
tpd(CB)
TEST CONDITIONS
Undervoltage voltage, circuit breaker
RISETx = 1 kΩ
40
Input bias current, ISENSEx
Discharge current,
current GATEx
VO(GATEx) = 4 V
VO(GATEx) = 1 V
Propagation (delay) time, comparator inputs to
gate output
Cg = 50 pF,
(50% to 10%)
400
800
25
150
10 mV overdrive,
CO(timer) = 50 pF
UNIT
mA
µs
1.3
ENABLE, active low (TPS2320)
PARAMETER
VIH(ENABLE)
VIL(ENABLE)
TEST CONDITIONS
MIN
High-level input voltage, ENABLE
TYP
MAX
2
V
Low-level input voltage, ENABLE
RI(ENABLE)
Input pullup resistance,
ENABLE
See Note 3
td_off(ENABLE)
Turnoff delay time, ENABLE
VI(ENABLE) increasing above stop threshold; 100
ns rise time, 20 mV overdrive (see Note 2)
td_on(ENABLE)
Turnon delay time, ENABLE
VI(ENABLE) decreasing below start threshold;
100 ns fall time, 20 mV overdrive (see Note 2)
100
UNIT
200
0.8
V
300
kΩ
60
µs
125
µs
NOTES: 2. Specified, but not production tested.
3. Test IO of ENABLE at VI(ENABLE) = 1 V and 0 V, then RI(ENABLE) =
I
* O_1V
1 V
I
O_ 0V
ENABLE, active high (TPS2321)
PARAMETER
VIH(ENABLE)
VIL(ENABLE)
TEST CONDITIONS
High-level input voltage, ENABLE
MIN
TYP
MAX
2
UNIT
V
Low-level input voltage, ENABLE
0.7
V
300
kΩ
RI(ENABLE)
Input pulldown resistance,
ENABLE
td_on(ENABLE)
Turnon delay time, ENABLE
VI(ENABLE) increasing above start threshold;
100 ns rise time, 20 mV overdrive (see Note 2)
85
µs
td_off(ENABLE)
Turnoff delay time, ENABLE
VI(ENABLE) decreasing below stop threshold;
100 ns fall time, 20 mV overdrive (see Note 2)
100
µs
100
150
NOTE 2: Specified, but not production tested.
PREREG
PARAMETER
TEST CONDITIONS
VREG
PREREG output voltage
4.5 ≤ VI(IN1) ≤ 13 V
Vdrop_PREREG
PREREG dropout voltage
VI(IN1) = 3 V
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP
MAX
UNIT
3.5
4.1
5.5
V
0.1
V
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
electrical characteristics over recommended operating temperature range (–40°C < TA < 85°C),
3 V ≤ VI(IN1) ≤13 V, 3 V ≤ VI(IN2) ≤ 5.5 V (unless otherwise noted) (continued)
VREG UVLO
MIN
TYP
MAX
UNIT
VOT(UVLOstart)
VOT(UVLOstop)
Output threshold voltage, start
PARAMETER
TEST CONDITIONS
2.75
2.85
2.95
V
Output threshold voltage, stop
2.65
2.78
Vhys(UVLO)
Hysteresis
50
75
UVLO sink current, GATEx
VI(GATEx) = 2 V
V
mV
10
mA
FAULT output
PARAMETER
VO(sat)(FAULT)
Ilkg(FAULT)
TEST CONDITIONS
Output saturation voltage, FAULT
Leakage current, FAULT
MIN
TYP
IO = 2 mA
VO(FAULT) = 13 V
MAX
UNIT
0.4
V
1
µA
DISCH1 and DISCH2
PARAMETER
TEST CONDITIONS
IDISCH
VIH(DISCH)
Discharge current, DISCHx
VI(DISCHx) = 1.5 V, VI(VIN1) = 5 V
VIL(DISCH)
Discharge on low-level input voltage
Discharge on high-level input voltage
POST OFFICE BOX 655303
MIN
TYP
5
10
MAX
mA
2
V
1
• DALLAS, TEXAS 75265
UNIT
V
7
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
Load 12 Ω
Load 12 Ω
VI(ENABLE)
5 V/div
VI(ENABLE)
5 V/div
VO(GATE1)
10 V/div
VO(DISCH1)
5 V/div
VO(GATE1)
10 V/div
VO(DISCH1)
5 V/div
t – Time – 10 ms/div
t – Time – 10 ms/div
Figure 1. Turnon Voltage Transition of
Channel 1
Figure 2. Turnoff Voltage Transition of
Channel 1
Load 5 Ω
Load 5 Ω
VI(ENABLE)
5 V/div
VI(ENABLE)
5 V/div
VO(GATE2)
10 V/div
VO(GATE2)
10 V/div
VO(DISCH2)
5 V/div
VO(DISCH2)
5 V/div
t – Time – 10 ms/div
Figure 3. Turnon Voltage Transition of
Channel 2
8
POST OFFICE BOX 655303
t – Time – 10 ms/div
Figure 4. Turnoff Voltage Transition of
Channel 2
• DALLAS, TEXAS 75265
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
No Capacitor
on Timer
VI(ENABLE)
5 V/div
VI(ENABLE)
5 V/div
VO(GATE1)
10 V/div
No Capacitor
on Timer
VO(GATE1)
10 V/div
VO(FAULT)
10 V/div
VO(FAULT)
10 V/div
IO(OUT1)
2 A/div
IO(OUT1)
2 A/div
t – Time – 1 ms/div
t – Time – 5 ms/div
Figure 5. Channel 1 Overcurrent Response:
Enabled Into Overcurrent Load
VI(ENABLE)
5 V/div
Figure 6. Channel 1 Overcurrent Response: an
Overcurrent Load Plugged Into the Enabled Board
No Capacitor
on Timer
No Capacitor
on Timer
VI(ENABLE)
5 V/div
VO(GATE2)
10 V/div
VO(GATE2)
10 V/div
VO(FAULT)
10 V/div
VO(FAULT)
10 V/div
IO(OUT2)
2 A/div
IO(OUT2)
2 A/div
t – Time – 2 ms/div
Figure 7. Channel 2 Overcurrent Response:
Enabled Into Overcurrent Load
POST OFFICE BOX 655303
t – Time – 0.5 ms/div
Figure 8. Channel 2 Overcurrent Response: an
Overcurrent Load Plugged Into the Enabled Board
• DALLAS, TEXAS 75265
9
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
No Capacitor
on Timer
VI(ENABLE)
5 V/div
No Capacitor
on Timer
VI(ENABLE)
5 V/div
VO(GATE1)
10 V/div
VO(GATE2)
5 V/div
VO(FAULT)
10 V/div
VO(FAULT)
10 V/div
IO(IN1)
2 A/div
IO(IN2)
2 A/div
t – Time – 1 ms/div
t – Time – 1 ms/div
Figure 9. Channel 1 – Enabled Into Short
Circuit
No Capacitor
on Timer
Figure 10. Channel 2 – Enabled Into Short Circuit
VI(IN1)
10 V/div
No Capacitor
on Timer
VO(GATE1)
10 V/div
VI(IN1)
10 V/div
VO(GATE1)
10 V/div
VO(OUT1)
10 V/div
VO(OUT1)
10 V/div
IO(OUT1)
1 A/div
IO(OUT1)
1 A/div
t – Time – 5 ms/div
Figure 11. Channel 1 – Hot Plug
10
POST OFFICE BOX 655303
t – Time – 1 ms/div
Figure 12. Channel 1 – Hot Removal
• DALLAS, TEXAS 75265
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
No Capacitor
on Timer
VI(IN2)
5 V/div
VO(GATE2)
10 V/div
VO(OUT2)
5 V/div
IO(OUT2)
1 A/div
t – Time – 5 ms/div
Figure 13. Channel 2 – Hot Plug
No Capacitor
on Timer
VI(IN2)
5 V/div
VO(GATE2)
10 V/div
VO(OUT2)
5 V/div
IO(OUT2)
1 A/div
t – Time – 1 ms/div
Figure 14. Channel 2 – Hot Removal
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11
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT (ENABLED)
vs
VOLTAGE
SUPPLY CURRENT (ENABLED)
vs
VOLTAGE
52
71.5
IN1 = 13 v
IN2 = 5.5 V
TA = 85°C
50
TA = 25°C
49
48
47
TA = 0°C
46
TA = 0°C
71
I I2 – Input Current 2 – µ A
I I1 – Input Current 1 – µ A
51
TA = –40°C
TA = –40°C
70.5
TA = 25°C
70
TA = 85°C
69.5
69
45
68.5
44
43
4
5
6
8
9
10 11 12
VI1 – Input Voltage 1 – V
13
7
68
2.5
14
3
Figure 15
5.5
6
Figure 16
SUPPLY CURRENT (DISABLED)
vs
VOLTAGE
SUPPLY CURRENT (DISABLED)
vs
VOLTAGE
15
IN2 = 5.5 V
3.5
4
4.5
5
VI2 – Input Voltage 2 – V
23
TA = 85°C
IN1 = 13 V
21
14
TA = –40°C
12
TA = 0°C
11
10
9
8
7
4
5
6
7
8
9
10 11 12
VI1 – Input Voltage 1 – V
13
14
TA = –40°C
17
15
13
11
9
TA = 0°C
7
TA = 25°C
5
2.5
Figure 17
12
TA = 85°C
19
13
I I2 – Input Current 2 – nA
I I1 – Input Current 1 – nA
TA = 25°C
3
3.5
4
4.5
5
VI2 – Input Voltage 2 – V
Figure 18
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5.5
6
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
GATE1 VOLTAGE
vs
INPUT VOLTAGE
GATE1 VOLTAGE RISE TIME
vs
GATE1 LOAD CAPACITANCE
22
20
18
IN1 = 12 V
TA = 25°C
TA = 85°C
TA = 25°C
TA = 0°C
18
TA = –40°C
16
14
12
t r – GATE1 Voltage Rise Time – ms
VO – GATE1 Output Voltage – V
CL(GATE1) = 1000 pF
10
2
3
9
10
6
7
8
VI1 – Input Voltage1 – V
4
5
11
15
12
9
6
3
0
12
0
9
12
3
6
CL(GATE1) – GATE1 Load Capacitance – nF
Figure 19
Figure 20
GATE1 VOLTAGE FALL TIME
vs
GATE1 LOAD CAPACITANCE
GATE1 OUTPUT CURRENT
vs
GATE1 VOLTAGE
15
IN1 = 12 V
TA = 25°C
14.5
I – GATE1 Current – µ A
t f – GATE1 Voltage Fall Time – ms
4
3
2
1
14
TA = –40°C
13.5
TA = 85°C
TA = 25°C
TA = 0°C
13
12.5
12
11.5
0
0
3
6
9
12
IN1 = 13 V
11
14 15
CL(GATE1) – GATE1 Load Capacitance – nF
Figure 21
16
17 18 19 20 21
V – GATE1 Voltage
22
23
24
Figure 22
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13
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
CIRCUIT-BREAKER RESPONSE
vs
TIMER CAPACITANCE
LOAD VOLTAGE 1 DISCHARGE TIME
vs
LOAD CAPACITANCE
320
IN1 = 12 V
TA = 25°C
IN1 = 12 V
IO1 = 0 A
TA = 25°C
280
9
t – Discharge Time – ms
t res – Circuit Braker Response Time –µ s
12
6
3
240
200
160
120
80
40
0
0
0.8
0.2
0.4
0.6
C(timer) – TIMER Capacitance – nF
0
1
0
Figure 23
400
100
200
300
CL – Load Capacitance – µF
Figure 24
UVLO START AND STOP THRESHOLDS
vs
TEMPERATURE
V ref – Reference Voltage UVLO Threshold – V
2.9
2.88
2.86
Start
2.84
2.82
2.8
2.78
Stop
2.76
2.74
2.72
2.7
–45–35–25–15 –5 5 15 25 35 45 55 65 75 85 95
TA – Temperature – °C
Figure 25
14
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500
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
APPLICATION INFORMATION
typical application diagram
Figure 26 shows a typical dual hot-swap application. The pullup resistor at FAULT should be relatively large
(e.g., 100 kΩ) to reduce power loss, unless it is required to drive a large load.
System
Board
RSENSE1
3 V ∼ 13 V IN1
1 µF ∼ 10 µF
VO1
+
RISET1
0.1 µF
VREG IN1 ISET1 ISENSE1 GATE1
TPS2321
TIMER IN2 ISET2 ISENSE2 GATE2
DISCH2
RISET2
3 V ∼ 5.5 V IN2
1 µF ∼ 10 µF
FAULT
FAULT
ENABLE
DGND
AGND
ENABLE
DISCH1
RSENSE2
VO1 or VO2
+
VO2
Figure 26. Typical Dual Hot-Swap Application
input capacitor
A 0.1-µF ceramic capacitor in parallel with a 1-µF ceramic capacitor should be placed on the input power
terminals near the connector on the hot-plug board to help stabilize the voltage rails on the cards. The
TPS2320/01 does not need to be mounted near the connector or to these input capacitors. For applications with
more severe power environments, a 2.2-µF, or higher, ceramic capacitor is recommended near the input
terminals of the hot-plug board. A bypass capacitor for IN1 and for IN2 should be placed close to the device.
output capacitor
A 0.1-µF ceramic capacitor is recommended per load on the TPS2320/21; these capacitors should be placed
close to the external FETs and to TPS2320/21. A larger bulk capacitor is also recommended on the load. The
value of the bulk capacitor should be selected based on the power requirements and the transients generated
by the application.
external FET
To deliver power from the input sources to the loads, each channel needs an external N-channel MOSFET. A
few widely used MOSFETs are shown in Table 1. But many other MOSFETs on the market can also be used
with TPS23xx in hot-swap systems.
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15
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
APPLICATION INFORMATION
Table 1. Some Available N-Channel MOSFETs
CURRENT RANGE
(A)
0 to 2
2 to 5
5 to 10
PART NUMBER
DESCRIPTION
MANUFACTURER
IRF7601
N-channel, rDS(on) = 0.035 Ω, 4.6 A, Micro-8
International Rectifier
MTSF3N03HDR2
N-channel, rDS(on) = 0.040 Ω, 4.6 A, Micro-8
ON Semiconductor
MMSF5N02HDR2
Dual N-channel, rDS(on) = 0.04 Ω, 5 A, SO-8
ON Semiconductor
IRF7401
N-channel, rDS(on) = 0.022 Ω, 7 A, SO-8
International Rectifier
MMSF5N02HDR2
N-channel, rDS(on) = 0.025 Ω, 5 A, SO-8
ON Semiconductor
IRF7313
Dual N-channel, rDS(on) = 0.029 Ω, 5.2 A, SO-8
International Rectifier
SI4410
N-channel, rDS(on) = 0.020 Ω, 8 A, SO-8
Vishay Dale
IRLR3103
N-channel, rDS(on) = 0.019 Ω, 29 A, d-Pak
International Rectifier
IRLR2703
N-channel, rDS(on) = 0.045 Ω, 14 A, d-Pak
International Rectifier
timer
For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. A capacitor
should be connected between TIMER and ground. The presence of an overcurrent condition on either channel
of the TPS2320/TPS2321 causes a 50-µA current source to begin charging this capacitor. If the overcurrent condition persists until the capacitor has been charged to approximately 0.5 V, the TPS2320/TPS2321
will latch off the offending channels and will pull the FAULT pin low. The timer capacitor can be made as large
as desired to provide additional time delay before registering a fault condition.
output-voltage slew-rate control
When enabled, the TPS2320/TPS2321 controllers supply the gates of each external MOSFET transistor with
a current of approximately 15 µA. The slew rate of the MOSFET source voltage is thus limited by the
gate-to-drain capacitance Cgd of the external MOSFET capacitor to a value approximating:
dvs
dt
+ 15C mA
gd
If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external
MOSFET and ground.
VREG capacitor
The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-µF
or 0.22-µF ceramic capacitor is recommended.
16
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TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
APPLICATION INFORMATION
gate-drive circuitry
The TPS2320/TPS2321 includes four separate features associated with each gate-drive terminal:
D
A charging current of approximately 15 µA is applied to enable the external MOSFET transistor. This current
is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH1
or DISCH2) of 9 V–12 V. DISCH1 and DISCH2 must be connected to the respective external MOSFET
source terminals to ensure proper operation of this circuitry.
D
A discharge current of approximately 75 µA is applied to disable the external MOSFET transistor. Once the
transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO
discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while
ensuring that the gates of the external MOSFET transistors remain at a low voltage.
D
D
During a UVLO condition, the gates of both MOSFET transistors are pulled down by internal PMOS
transistors. These transistors continue to operate even if IN1 and IN2 are both at 0 V. This circuitry also helps
hold the external MOSFET transistors off when power is suddenly applied to the system.
During an overcurrent fault condition, the external MOSFET transistor that exhibited an overcurrent
condition will be rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at
4 V) from the pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and
the UVLO driver is enabled instead. If one channel experiences an overcurrent condition and the other does
not, then only the channel that is conducting excessive current will be turned off rapidly. The other channel
will continue to operate normally.
setting the current-limit circuit-breaker threshold
Using Channel 1 as an example, the current sensing resistor RISENSE1 and the current-limit-setting resistor
RISET1 determine the current limit of the channel, and can be calculated by the following equation:
I LMT1
+ RISET1R
10 –6
50
ISENSE1
Typically RISENSE1 is very small (0.001 Ω to 0.1 Ω). If the trace and solder-junction resistances between the
junction of RISENSE1 and ISENSE1 and the junction of RISENSE1 and RISET1 are greater than 10% of the
RISENSE1 value, then these resistance values should be added to the RISENSE1 value used in the calculation
above.
The above information and calculation also apply to Channel 2. Table 2 shows some of the current sense
resistors available in the market.
Table 2. Some Current Sense Resistors
CURRENT RANGE
(A)
PART NUMBER
DESCRIPTION
0 to 1
WSL-1206, 0.05 1%
0.05 Ω, 0.25 W, 1% resistor
1 to 2
WSL-1206, 0.025 1%
0.025 Ω, 0.25 W, 1% resistor
2 to 4
WSL-1206, 0.015 1%
0.015 Ω, 0.25 W, 1% resistor
4 to 6
WSL-2010, 0.010 1%
0.010 Ω, 0.5 W, 1% resistor
6 to 8
WSL-2010, 0.007 1%
0.007 Ω, 0.5 W, 1% resistor
8 to 10
WSR-2, 0.005 1%
0.005 Ω, 0.5 W, 1% resistor
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MANUFACTURER
Vishay Dale
17
TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
APPLICATION INFORMATION
undervoltage lockout (UVLO)
The TPS2320/TPS2321 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on
the VREG pin. This feature will disable both external MOSFETs if the voltage on VREG drops below 2.78 V
(nominal) and will re-enable normal operation when it rises above 2.85 V (nominal). Since VREG is fed from
IN1 through a low-dropout voltage regulator, the voltage on VREG will track the voltage on IN1 within 50 mV.
While the undervoltage lockout is engaged, both GATE1 and GATE2 are held low by internal PMOS pulldown
transistors, ensuring that the external MOSFET transistors remain off at all times, even if all power supplies have
fallen to 0 V.
single-channel operation
Some applications may require only a single external MOS transistor. Such applications should use GATE1 and
the associated circuitry (IN1, ISENSE1, ISET1, DISCH1). The IN2 pin should be grounded to disable the
circuitry associated with the GATE2 pin.
power-up control
The TPS2320/TPS2321 includes a 500 µs (nominal) startup delay that ensures that internal circuitry has
sufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered only
upon the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockout
circuitry will provide adequate protection against undervoltage operation.
3-channel hot-swap application
Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensing
of the status of the output power on all three of the voltage rails. One such application is device bay, where dv/dt
control of 3.3 V, 5 V, and 12 V is required. By using Channel 2 to drive both the 3.3-V and 5-V power rails and
Channel 1 to drive the 12-V power rail, as is shown below, TPS2320/01 can deliver three different voltages to
three loads while monitoring the status of two of the loads.
18
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TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
APPLICATION INFORMATION
System
Board
RSENSE1
12 V IN1
1 µF ∼ 10 µF
+
VO1
RISET1
0.1 µF
Vreg IN1 ISET1 ISENSE1
TIMER
1 µF ∼ 10 µF
FAULT
TPS2321
IN2 ISET2 ISENSE2
RISET2
3.3 V IN2
DISCH1
FAULT
ENABLE
DGND
AGND
ENABLE
GATE1
GATE2
DISCH2
VO1 or VO2
Rg1
+
RSENSE2
VO2
Rg2
5 V IN3
1 µF ∼ 10 µF
+
VO3
Figure 27. Three-Channel Application
Figure 28 shows ramp-up waveforms of the three output voltages.
VO – Output Voltage – 2 V/div
VO1
VO3
VO2
t – Time – 2.5 ms/div
Figure 28
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TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
20
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
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TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER
SLVS276A – MARCH 200 – REVISED APRIL 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
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