HOLTEK HT46R75D-3

HT46R75D-3
Dual Slope A/D Type 8-Bit OTP MCU with LCD
Features
· Operating voltage:
· Buzzer output
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Internal 12kHz RC oscillator
· External 32.768kHz Crystal oscillator
· Three system oscillators:
· Power-down and wake-up features reduce power
External Crystal oscillator -- HXT
External RC oscillator -- ERC
Internal High Frequency RC oscillator -- HIRC
consumption
· Voltage regulator (3.3V) and charge pump
· Embedded voltage reference generator (1.5V)
· Up to 22 bidirectional I/O lines
· 8 subroutine nesting levels
· One external interrupt input shard with an I/O lines
· 16-bit table read instruction
· One 8-bit and two 16-bit programmable timer/event
· Low Voltage Reset function
counter with overflow interrupt and an 8-bit prescaler
· LCD driver with 24´8 or 28´4 segments
· One vibration sensor input
· LCD bias type: 1/3 bias R type or C type
· Four touch-key inputs
· Bit manipulation instruction
· Program Memory: 8K´16
· Up to 0.5ms instruction cycle with 8MHz system clock
· Data Memory: 192´8
· 63 powerful instructions
· Single differential input channel dual slope Analog to
· All instructions in 1 or 2 machine cycles
Digital Converter with Operational Amplifier
· 64-pin LQFP package
· Watchdog Timer with regulator power
General Description
The HT46R75D-3 is an 8-bit high performance, RISC
architecture microcontroller device specifically designed for A/D with LCD applications that interface directly to analog signals, such as those from sensors.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, Dual slope A/D
Rev. 1.00
converter, LCD display, HALT and wake-up functions,
watchdog timer, as well as low cost, enhance the versatility of these devices to suit for a wide range of AD with
LCD application possibilities such as sensor signal processing, scales, consumer products, subsystem controllers, etc.
1
July 19, 2011
HT46R75D-3
Block Diagram
Prescaler
M
U
X
TMR0C
TMR0
M
U
X
fSYS
M
U
X
fSYS/4
M
U
X
fSYS/4
LF
TMR0
Interrupt
Circuit
STACK
Program
ROM
Program
Counter
Instruction
Register
INTC
TMR1
M
U
X
MP
DATA
Memory
Prescaler
M
U
X
TMR1C
Prescaler
M
U
X
TMR2C
TMR2
WDT
M
U
X
HALT
WDT
OSC
fRTC
fSYS/4
MUX
Instruction
Decoder
TCKF
TMR2
fWDT
WDT
Prescaler
LF
TMR1
EN/DIS
fRTC
ALU
Timing
Generator
RTC OSC
OSC4
OSC3
OSC2
VDD
CHPC1
CHPC2
LVR Circuits
STATUS
Shifter
OSC1
RES
VDD
VSS
Charge
Pump
1-Channel
Dual-Slope
Converter
with OP
BP
ACC
PAC
LCD
Memory
Regulator
Amplifier
DOPAN
DCHOP
DSRC
TH/LB
PA0/VIB
PA5/OSC2
PA1/BZ
PA6/OSC1
PA2/BZ/KREF PA7/RES
PA3/OSC4
PA4/OSC3
Vibration Sensor input
LCD DRIVER
VMAX VLCD
COM0~COM3
SEG0~SEG15
Port B
PB
Touch Key
circuits
VOREG
Rev. 1.00
Port A
PA
PBC
VOCHP
DOPAP
DOPAO
DSRR
DSCC
2
PB0/TK0
PB1/TK1
PB2/TK2
PB3/TK3
PB4/INT/SEG0
PB5/TMR0/SEG1
PB6/TMR1/SEG2
PB7/TMR2/SEG3
Touch Key inputs
July 19, 2011
HT46R75D-3
Pin Assignment
PC5/SEG5
PC4/SEG4
PC3/SEG3
PC2/SEG2
PC1/TMR2/SEG1
PC0/TMR1/SEG0
PA0/VIB
PA1/BZ
PA2/BZ
PA3/OSC4
PA4/OSC3
PA5/OSC2
PA6/OSC1
VDD
VSS
PB0/TK1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PB1/TK2
PB2/TK3
PB3/TK4
PB4/INT
PB5/TMR0
AVDD
1
48
2
47
3
46
4
45
5
44
AI
TH/LB
VOBGP
CHPC2
CHPC1
VOCHP
7
VOREG
AVSS
DOPAP
DOPAN
6
43
42
HT46R75D-3
64 LQFP-A
8
9
41
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
PC6/SEG6
PC7/SEG7
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
COM7/SEG24
COM6/SEG25
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
COM5/SEG26
COM4/SEG27
COM3
COM2
COM1
COM0
VAB
VC
C1
C2
PA7/RES
DSCC
DSRC
DSRR
DCHOP
DOPAO
PC5/SEG5
PC4/SEG4
PC3/SEG3
PC2/SEG2
PC1/TMR2/SEG1
PC0/TMR1/SEG0
PA0/VIB
PA1/BZ
PA2/BZ
PA3/OSC4
PA4/OSC3
PA5/OSC2
PA6/OSC1
VDD
VSS
PB0/TK1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PB1/TK2
PB2/TK3
PB3/TK4
PB4/INT
1
48
2
47
3
46
4
45
PB5/TMR0
AVDD
5
44
6
43
AI
TH/LB
VOBGP
CHPC2
7
10
39
CHPC1
VOCHP
11
38
12
37
SEG16
SEG17
VOREG
13
36
SEG18
AVSS
DOPAP
DOPAN
14
35
15
34
16
33
SEG19
SEG20
SEG21
42
HT46R75D-3
64 LQFP-B
8
9
41
40
PC6/SEG6
PC7/SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
3
SEG22
SEG23
COM7/SEG24
COM6/SEG25
COM5/SEG26
COM4/SEG27
COM3
COM2
COM1
COM0
PA7/RES
DSCC
DSRC
DSRR
DCHOP
DOPAO
Rev. 1.00
July 19, 2011
HT46R75D-3
Pin Description
Pin Name
PA0/VIB
PA1/BZ
PA2/BZ
PA3/OSC4
PA4/OSC3
PA5/OSC2
PA6/OSC1
PA7/RES
PB0/TK1~
PB3/TK4
PB4/INT
PB5/TMR0
I/O
Options
Description
I/O
Bidirectional 8-bit input/output port. Each individual bit on this port can be
configured to have a wake-up function using a register control bit. Software instructions determine if the pin is a CMOS output or Schmitt Trigger
input. Also the register control bits determine which pins on this port have
pull-high resistors except for PA7.
VIB is the vibration sensor analog input which is pin-shared with PA0.
BZ and BZ are buzzer outputs pin-shared with PA1 and PA2 and are to be
used as buzzer outputs or normal I/O functions determined by a register
OSCn or
control bit.
I/O
OSC1 and OSC2 can be used as system oscillator pins which are
RES or I/O
pin-shared with PA6 and PA5. Configuration options determine if these
pins are used as I/O pins or system oscillator pins.
OSC3 and OSC4 can be configured to be used as the 32.768kHz oscillator pins or as the normal I/O pins named PA4 and PA3 using a configuration option.
RES is pin-shared with PA7 determined by a configuration option. When
PA7 is configured as an I/O pin, software instructions determine if this pin
is open drain output or Schmitt Trigger input without pull-high resistor.
I/O
¾
Bidirectional 8-bit input/output port. Software instructions determine if the
pin is a CMOS output or Schmitt Trigger input. Register control bits determine which pins on this port have pull-high resistors.
TK0~TK3 are touch sensor input pins which are pin-shared with
PB0~PB3. PB4~PB5 are pin-shared with INT and TMR0 respectively.
PC0/TMR1/SEG0
PC1/TMR2/SEG1
PC2/SEG2
PC3/SEG3
PC4/SEG4
PC5/SEG5
PC6/SEG6
PC7/SEG7
I/O
¾
Bidirectional 8-bit input/output port. Software instructions determine if the
pin is a CMOS output or Schmitt Trigger input. Register control bits determine which pins on this port have pull-high resistors.
PC0 and PC1 are pin-shared with TMR1 and TMR2 respectively.
PC0~PC7 are also pin-shared with the LCD segments SEG0~SEG7 respectively which are selected by register control bits. Once these pins are
selected as segments, the I/O function including Schmitt trigger input and
pull-high function are disabled. However, these pins will default to an input
mode with pull-high resistors after a reset.
SEG8~SEG23
O
¾
LCD segment outputs
COM0~COM3
O
¾
LCD common outputs
COM4/SEG27
COM5/SEG26
COM6/SEG25
COM7/SEG24
O
¾
LCD common/segment outputs.
The common or segment output function are determined by the register
control bits.
VAB, VC, C1, C2
AI
¾
LCD voltage pump
AI
AI
¾
Analog to digital converter input
VOBGP
AO
VOREG
O
¾
Regulator output 3.3V
VOCHP
O
¾
Charge pump output -- a capacitor is required to be connected
CHPC1
¾
¾
Charge pump capacitor (positive)
CHPC2
¾
¾
Charge pump capacitor (negative)
DOPAN,
DOPAP,
DOPAO,
DCHOP
AI/AO
¾
Dual Slope A/D converter pre-stage OPA related pins. DOPAN is the OPA
Negative input pin, DOPAP is the OPA Positive input pin, DOPAO is the
OPA output pin and DCHOP is the OPA Chopper pins.
AI
¾
Temperature sensor/Low battery voltage input pin.
TH/LB
Rev. 1.00
Band gap voltage output pin (for internal use)
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July 19, 2011
HT46R75D-3
Pin Name
I/O
Options
Description
DSRR
DSRC
DSCC
AI/AO
¾
Dual slope A/D converter main function RC circuit. DSRR is the input or
reference signal, DSRC is the Integrator negative input, and DSCC is the
comparator negative input.
VDD
PWR
¾
Digital positive power supply
VSS
PWR
¾
Digital Negative Power supply, ground
AVDD
PWR
¾
Analog positive power supply
AVSS
PWR
¾
Analog negative power supply, ground
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-20°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
VDD
Min.
Typ.
Max.
Unit
Conditions
¾
fSYS=4MHz
2.2
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
¾
4
8
mA
Operating Voltage
IDD1
Operating Current (Crystal OSC,
Ext. RC OSC, Int. RC OSC)
5V
No load, fSYS=8MHz,
analog block off
IDD2
Operating Current (Crystal OSC, 3V
Ext. RC OSC, Int. RC OSC)
5V
No load, fSYS=4MHz,
ADC block off
¾
0.8
1.5
mA
¾
2.5
4
mA
3V
No load, fSYS=2MHz,
ADC block off
¾
0.5
1
mA
¾
1.5
3
mA
¾
3
5
mA
No load, system HALT,
LCD off at HALT
¾
¾
1
mA
¾
¾
2
mA
¾
2.5
5
mA
5V
No load, system HALT,
LCD off at HALT, ADC off
¾
8
15
mA
Standby Current (WDT Disable In- 3V
ternal RC 12kHz OSC ON)
5V
No load, system HALT,
LCD off at HALT, ADC off
¾
2
5
mA
¾
6
10
mA
Standby Current
(WDT Disable,
LCD On and Regulator On)
No load, system osc HALT,
internal RC 12kHz OSC
On, ADC block Off,
LCD ON (1/3 bias, R type)
at HALT
¾
380
500
mA
IDD3
Operating Current
(Crystal OSC, Ext. RC OSC)
5V
IDD4
Operating Current
(Crystal OSC, Ext. RC OSC)
ISTB1
Standby Current
(WDT Disable)
3V
Standby Current
(WDT Enable)
3V
ISTB2
ISTB3
ISTB4
Rev. 1.00
5V
5V
5V
VREGO=3.3V, fSYS=4MHz,
ADC on, ADCCCLK=
125kHz (all other analog devices off)
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July 19, 2011
HT46R75D-3
Test Conditions
Symbol
Parameter
VDD
ISTB5
Standby Current (Internal RC
12kHz OSC Off, RTC On)
ISTB6
Standby Current
(WDT Disable,
LCD On and Regulator On)
ISTB7
Standby Current
(WDT Disable)
3V
5V
5V
3V
5V
Min.
Typ.
Max.
Unit
¾
¾
5
mA
¾
¾
15
mA
¾
390
510
mA
¾
2
4
mA
¾
8
16
mA
V
Conditions
No load, system HALT
RTC osc slowly start-up
No load, system osc Off,
RTC OSC On, ADC block
Off, LCD On (1/3 bias,
R type)
No load, Only vibration
sensor turn on & VIB pin
connected a 0.1mF cap to
VSS
Input Low Voltage for I/O Ports or ¾
Input Pins except RES pin.
5V
¾
0
¾
0.2VDD
¾
0
¾
1.5
Input High Voltage for I/O Ports or ¾
Input Pins except RES pin.
5V
¾
0.8VDD
¾
VDD
¾
3.5
¾
5.0
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLCD
LCD Highest Voltage
¾
¾
0
¾
VDD
V
Configuration option: 2.1V
1.98
2.10
2.22
V
VLVR
Low Voltage Reset
Configuration option: 3.15V
2.98
3.15
3.32
V
Configuration option: 4.2V
3.98
4.20
4.42
V
¾
2.2
2.3
2.4
V
4
8
¾
mA
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
210
420
¾
mA
350
700
¾
mA
-80
-160
¾
mA
-180
-360
¾
mA
2
3
¾
mA
¾
20
60
100
kW
5V
¾
10
30
50
kW
VPOR
VDD Start Voltage to ensure
Power-on Reset
¾
¾
¾
¾
100
mV
RRPOR
VDD Rise Rate to ensure
Power-on Reset
¾
¾
0.035
¾
¾
V/ms
tPOR
Power-on Reset Low Pulse Width
¾
¾
1
¾
¾
ms
VVIBWK
Minimum Voltage to Wake MCU
by the Vibration Sensor Input
¾
250
¾
¾
mV
VIL1
VIH1
¾
VLVD
Low Voltage Detector
¾
IOL1
Sink Current for I/O ports
except PA7
3V
Source Current for I/O ports
except PA7
3V
IOH1
5V
3V
LCD Common and Segment
Current
3V
5V
IOL3
Sink Current for PA7
5V
RPH
Pull-high Resistance of I/O Ports
IOH2
Rev. 1.00
VOH=0.9VDD
5V
LCD Common and Segment
Current
IOL2
VOL=0.1VDD
VOL=0.1VDD
5V
VOH=0.9VDD
VOL=0.1VDD
3V
100Hz~1KHz sine wave
(note)
6
V
July 19, 2011
HT46R75D-3
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
Charge pump on
2.2
¾
3.6
V
Charge pump off
3.7
¾
5.5
V
VDD
Conditions
Charge Pump and Regulator
VCHPI
Input Voltage
VREGO
¾
Output Voltage
VREGDP1
¾
No load
3
3.3
3.6
V
¾
VDD=3.7V~5.5V
Charge pump off
Current£10mA
¾
100
¾
mV
¾
VDD=2.4V~3.6V
Charge pump on
Current£6mA
¾
100
¾
mV
@3.3V
¾
50
¾
Ppm/°C
¾
500
800
mV
Regulator Output Voltage Drop
(Compare with No Load)
VREGDP2
Dual Slope AD, Amplifier and Band Gap
VRFGTC
Reference Generator
Temperature Coefficient
¾
VADOFF
Input Offset Range
¾
VICMR
¾
¾
Amplifier, no load
0.2
¾
VREGO1.2
V
¾
Integrator, no load
1.2
¾
VREGO0.2
V
Common Mode Input Range
Note: 1.
V
D D
tP
O R
R R
P O R
V
P O R
T im e
2. Test Circuits for VVMBWK
V
0 .1 m F
T o V IB P in
t
A C
V
V IB W K
S in e W a v e
Rev. 1.00
7
July 19, 2011
HT46R75D-3
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
System Clock (External RC OSC)
fSYS
System Clock (Crystal OSC)
Min.
Typ.
Max.
Unit
¾
400
¾
4000
kHz
2.2V~
5.5V
¾
400
¾
4000
kHz
3.3V~
5.5V
¾
400
¾
8000
kHz
4.5V~
5.5V
¾
400
¾
12000
kHz
-2%
4/8
+2%
MHz
-2%
12
+2%
MHz
-5%
4/8
+5%
MHz
Ta=0~70°C
-5%
12
+5%
MHz
2.2V~
Ta=0~70°C
3.6V
-8%
4
+8%
MHz
3.0V~
Ta=0~70°C
5.5V
-8%
4/8
+8%
MHz
4.5V~
Ta=0~70°C
5.5V
-8%
12
+8%
MHz
2.2V~
Ta=-40~85°C
3.6V
-12%
4
+12%
MHz
3.0V~
Ta=-40~85°C
5.5V
-12%
4/8
+12%
MHz
4.5V~
Ta=-40~85°C
5.5V
-12%
12
+12%
MHz
VDD
Conditions
2.2V~
5.5V
3V/5V Ta=25°C
5V
Ta=25°C
3V/5V Ta=0~70°C
5V
fHIRC
Internal RC OSC
fERC
External RC OSC
Timer I/P Frequency
(TMR0/TMR1/TMR2)
fTIMER
tWDTOSC Watchdog Oscillator Period
5V
Ta=25°C, R=120kW
-2%
4
-2%
MHz
5V
Ta=0~70°C, R=120kW
-5%
4
-5%
MHz
5V
Ta=-40~85°C, R=120kW
-7%
4
-7%
MHz
2.2V~
Ta=-40~85°C, R=120kW
5.5V
-11%
4
-11%
MHz
2.2V~
5.5V
¾
0
¾
4000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
¾
1
¾
¾
ms
fSYS=Crystal Oscillator
¾
1024
¾
tSYS
fSYS= fERC or fHIRC
¾
1024 *
¾
tSYS
tRES
External Reset Low Pulse Width
¾
tSST
System Start-up Timer Period
(Wake-up from HALT)
¾
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1.00
2.00
ms
Note: tSYS= 1/fSYS
²*² When the system clock comes from the external RC or internal RC oscillator, the system start-up time
period can be 2 or 1024 clock cycles determined by a configuration option.
Rev. 1.00
8
July 19, 2011
HT46R75D-3
Functional Description
Execution Flow
After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1.
The PC then points to the memory word containing the
next instruction code.
The system clock is derived from a crystal, an external
RC or internal RC oscillator. It is internally divided into
four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two
cycles are required to complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction.
Program Counter - PC
The program counter (PC) is 13 bits wide and it controls
the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can
specify a maximum of 4096 addresses.
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
The lower byte of the PC (PCL) is a readable and writeable
register (06H). Moving data into the PCL performs a short
jump. The destination is within 256 locations.
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
0
1
1
0
0
Multi-function Interrupt
0
0
0
0
0
0
0
0
1
0
0
0
0
ADC Interrupt
0
0
0
0
0
0
0
0
1
0
1
0
0
Touch Key Interrupt
0
0
0
0
0
0
0
0
1
1
0
0
0
Skip
Program Counter+2
Loading PCL
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
PC12 PC11 PC10 PC9 PC8 @7
#12
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return From Subroutine
S11 S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
#11
Program Counter
Note:
*b12~*0: Program counter bits
#12~#0: Instruction code bits
Rev. 1.00
S12~S0: Stack register bits
@7~@0: PCL bits
9
July 19, 2011
HT46R75D-3
· Location 014H
When a control transfer takes place, an additional
dummy cycle is required.
Location 014H is reserved for the ADC interrupt service program. If an ADC interrupt occurs, and if the interrupt is enabled and the stack is not full, the program
begins execution at this location.
Program Memory
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192´16 bits which are addressed by the program
counter and table pointer.
· Location 018H
Certain locations in the ROM are reserved for special
usage:
· Table location
Location 018H is reserved for the touch key interrupt
service program. If a touch key interrupt occurs, and if
the interrupt is enabled and the stack is not full, the
program begins execution at this location.
Any location in the ROM can be used as a look-up table. The instructions ²TABRDC [m]² (the current page,
1 page=256 words) and ²TABRDL [m]² (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the contents of the
higher-order byte to TBLH (Table Higher-order byte
register) (08H). Only the destination of the lower-order
byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of
TBLH. The TBLH is read only, and the table pointer
(TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location
should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation.
These areas may function as a normal ROM depending upon the user¢s requirements.
· Location 000H
Location 000H is reserved for program initialization.
After chip reset, the program always begins execution
at this location.
· Location 004H
Location 004H is reserved for the external interrupt
service program. If the INT input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 004H.
· Location 008H
Location 008H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 008H.
0 0 0 H
· Location 00CH
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
Location 00CH is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
0 0 8 H
0 0 C H
0 1 0 H
· Location 010H
0 1 4 H
Location 010H is reserved for the Multi-function interrupt service program including the Timer/Event Counter 2 overflow, Touch Key module 16-bit and 10-bit
counters interrupt. If an interrupt results from the
Touch Key module or a Timer/Event Counter 2 overflow, and the interrupt is enabled, and the stack is not
full, the program begins execution at location 010H.
0 1 8 H
E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
M u lti- fu n c tio n In te r r u p t S u b r o u tin e
A /D
P ro g ra m
M e m o ry
C o n v e r te r In te r r u p t S u b r o u tin e
T o u c h K e y In te r r u p t S u b r o u tin e
1 0 0 H
L o o k - u p T a b le ( 2 5 6 W o r d s )
1 F F H
1 E F F H
1 F 0 0 H
L o o k - u p T a b le ( 2 5 6 W o r d s )
1 F F F H
1 6 b its
Program Memory
Instruction(s)
TABRDC [m]
TABRDL [m]
Table Location
b12
b11
b10
PC12 PC11 PC10
1
1
1
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
b12~b0: Table location
@7~@0: Table of TBLP
Rev. 1.00
PC12~PC8: Current Program Counter
10
July 19, 2011
HT46R75D-3
Stack Register - STACK
ations to Bank 1. Directly addressing the Data Memory
will always result in Bank 0 being accessed irrespective
of the value of BP.
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 8 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At a
commencement of a subroutine call or an interrupt acknowledgment, the content of the program counter is
pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or
RETI), the contents of the program counter is restored
to its previous value from the stack. After chip reset, the
SP will point to the top of the stack.
B a n k 0
T o p o f S ta c k
IA R 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
C T R L 0
0 A H
S T A T U S
0 B H
IN T C 0
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 7 H
A D C R
1 8 H
1 9 H
A D C D
1 A H
1 B H
C o u n te r
S ta c k L e v e l 1
S ta c k L e v e l 3
M P 0
0 2 H
1 6 H
S ta c k L e v e l 2
S ta c k
P o in te r
0 1 H
0 C H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent 8 return addresses are stored).
P ro g ra m
B a n k 0
IA R 0
0 0 H
P ro g ra m
M e m o ry
1 C H
W D T C
1 D H
W D T D
1 E H
IN T C 1
1 F H
C H P R C
2 0 H
T M R 2 H
2 1 H
T M R 2 L
2 2 H
T M R 2 C
S p e c ia l P u r p o s e
D a ta M e m o ry
2 3 H
2 4 H
2 5 H
B o tto m
o f S ta c k
S ta c k L e v e l 8
Data Memory - RAM
2 6 H
H A L T C
2 7 H
L C D O U T
2 8 H
C T R L 1
2 9 H
V IB R C
2 A H
R E G C
The data memory is divided into two functional groups,
namely the special function registers and the general
purpose data memory of 192´8 bit capacity. Most of
them are read/write, but some are read only.
2 B H
P C
2 C H
P C C
2 D H
P A W K
2 E H
P A P U
The unused space before 40H is reserved for future expanded usage and reading these locations will return
the result 00H. The general purpose data memory, addressed from 40H to FFH, is used for data and control
information under instruction command. The areas in
the RAM can directly handle arithmetic, logic, increment, decrement, and rotate operations. Except some
dedicated bits, each bit in the RAM can be set and reset
by ²SET [m].i² and ²CLR [m].i². They are also indirectly
accessible through the Memory pointer register 0 (MP0;
01H) or the Memory pointer register 1 (MP1; 03H).
P B P U
3 0 H
P C P U
3 1 H
S F S
3 2 H
3 3 H
L C D C
3 4 H
M F IC
3 5 H
3 6 H
3 7 H
3 8 H
T K M 0 1 6 D H
3 9 H
T K M 0 1 6 D L
3 A H
3 B H
3 C H
T K M 0 C 0
3 D H
T K M 0 C 1
3 E H
T K M 0 C 2
T K M 0 C 3
3 F H
4 0 H
Bank 1 contains the LCD Data Memory locations. After
first setting up BP to the value of ²01H² to access Bank 1
this bank must then be accessed indirectly using the
Memory Pointer MP1. With BP set to a value of ²01H²,
using MP1 to indirectly read or write to the data memory
areas with addresses from 40H~5BH will result in operRev. 1.00
2 F H
5 B H
G e
P u
D a ta
(1 9 2
n e ra l
rp o s e
M e m o ry
B y te s )
L C D R A M
(2 8 B y te s )
7 F H
: u n im p le m e n te d , r e a d a s " 0 "
RAM Mapping
11
July 19, 2011
HT46R75D-3
Indirect Addressing Register - IAR0, IAR1
means that the Special Function Registers can be accessed from within any bank. Directly addressing the
Data Memory will always result in Bank 0 being accessed
irrespective of the value of the Bank Pointer. Accessing
data from banks other than Bank 0 must be implemented
using Indirect addressing mode. As both the Program
Memory and Data Memory share the same Bank Pointer
Register, care must be taken during programming.
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by
MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While,
writing it indirectly leads to no operation. The memory
pointer register, MP0 and MP1, are 8-bit registers.
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. MP0 can only be applied to data
memory, while MP1 can be applied to data memory and
LCD display memory.
Accumulator - ACC
The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
Arithmetic and Logic Unit - ALU
Memory Pointers - MP0, MP1
This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in
the same way as normal registers providing a convenient way with which to address and track data. When
any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the
microcontroller is directed to is the address specified by
the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data
from Bank 0, while MP1 and IAR1 are used to access
data from all banks according to BP register. Direct Addressing can only be used with Bank 0 while all other
Banks must be addressed indirectly using MP1 and
IAR1.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PDF), and a
watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Bank Pointer - BP
Depending upon which device is used, the Program and
Data Memory are divided into several banks. Selecting
the required Program and Data Memory area is
achieved using the Bank Pointer. Bit 0 of the Bank
Pointer is used to select Data Memory Banks 0~1.
Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter
the TO or PDF flags. Operations related to the status
register, however, may yield different results from those
intended. The TO and PDF flags can only be changed
by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of
the latest operations.
The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power-down Mode,
in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data
Memory is not affected by the bank selection, which
· BP Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
¾
¾
DMBP0
R/W
¾
¾
¾
¾
¾
¾
¾
R/W
POR
¾
¾
¾
¾
¾
¾
¾
0
Bit 7~1 :
unimplemented, read as ²0²
Bit 0
DMBP0: Data Memory bank point
0: Bank 0
1: Bank 1
Rev. 1.00
12
July 19, 2011
HT46R75D-3
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
An external interrupt is triggered by an edge transition on
INT pin (software control bits select the edge transition
from high to low, low to high, both low to high and high to
low), and the related interrupt request flag (EIF; bit 4 of
INTC0) is set as well. After the interrupt is enabled, the
stack is not full, and the external interrupt is active, a subroutine call to location 04H occurs. The interrupt request
flag (EIF) and EMI bits are all cleared to disable other
maskable interrupts.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
Interrupts
The device provides one external interrupts, three internal timer/event counter interrupts, an ADC interrupt and
touch key interrupt. The interrupt control register 0
(INTC0;0BH) and interrupt control register 1
(INTC1;1EH) both contain the interrupt control bits that
are used to set the enable/ disable status and interrupt
request flags.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of INTC0), which is normally
caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 08H occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is
cleared to disable other maskable interrupts. The
Timer/Event Counter 1 is operated in the same manner
but its related interrupt request flag is T1F (bit 6 of
INTC0) and its subroutine call location is 0CH.
Once an interrupt subroutine is serviced, other interrupts are all blocked, by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becoming full.
Within this device there is one Multi-function interrupt.
Unlike the other independent interrupts, these interrupts
have no independent source, but rather are formed from
the Touch Key module timer interrupt sources and
Timer/Event Counter 2 interrupt.
A Multi-function interrupt request will take place when
any of the Multi-function interrupt request flags are set.
The Multi-function interrupt flags will be set when any of
their included functions generate an interrupt request
flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt
is enabled and the stack is not full, and either one of the
interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function
interrupt vectors will take place. When the interrupt is
serviced, the related Multi-Function request flag will be
automatically reset and the EMI bit will be automatically
cleared to disable other interrupts.
All interrupts will provide a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the
contents of the program counter onto the stack followed
by a branch to a subroutine at the specified location in the
Program Memory. Only the contents of the program
counter is pushed onto the stack. If the contents of the
register or of the status register is altered by the interrupt
service program which corrupts the desired control sequence, the contents should be saved in advance.
Rev. 1.00
13
July 19, 2011
HT46R75D-3
However, it must be noted that, although the
Multi-function Interrupt flags will be automatically reset
when the interrupt is serviced, the request flags from the
original source of the Multi-function interrupts, namely
the Touch Key module timer interrupts or the
Timer/Event Counter 2 interrupt, will not be automatically reset and must be manually reset by the application program.
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Interrupt Source
The A/D Converter interrupt is initialized by setting the
A/D Converter interrupt request flag (ADF; bit 5 of
INTC1), that is caused by an A/D conversion done signal. After the interrupt is enabled, and the stack is not
full, and the ADF bit is set, a subroutine call to location
14H occurs. The related interrupt request flag (ADF) is
reset and the EMI bit is cleared to disable further
maskable interrupts.
Priority
Vector
External interrupt
1
04H
Timer/Event Counter 0 overflow
2
08H
Timer/Event Counter 1 overflow
3
0CH
Multi-function Interrupt
4
10H
A/D converter interrupt
5
14H
Touch Key interrupt
6
18H
Once the interrupt request flags (TKF, ADF, MFF, T1F,
T0F and EIF) are all set, they remain in the INTC1 or
INTC0 respectively until the interrupts are serviced or
cleared by a software instruction.
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the ²RETI² instruction is executed or the EMI bit and the
related interrupt control bit are set both to 1 (if the stack
is not full). To return from the interrupt subroutine, ²RET²
or ²RETI² may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not.
It is recommended that a program should not use the
²CALL subroutine² within the interrupt subroutine. It¢s because interrupts often occur in an unpredictable manner
or require to be serviced immediately in some applications. During that period, if only one stack is left, and enabling the interrupt is not well controlled, operation of
the ²call² in the interrupt subroutine may damage the
original control sequence.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
Bit No.
Label
0
EMI
Controls the master (global) interrupt (1=enabled; 0=disabled)
Function
1
EEI
Controls the external interrupt (1=enabled; 0=disabled)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
4
EIF
External interrupt request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
¾
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC0 Register
Bit No.
Label
0
EMFI
Control Multi-function Interrupt (1=enabled; 0=disabled)
Function
1
EADI
Control the ADC interrupt (1=enabled; 0=disabled)
2
TKE
Control touch key interrupt (1=enabled; 0=disabled)
3
¾
4
MFF
Multi-function Interrupt request flag (1=active; 0=inactive)
5
ADF
ADC request flag (1=active; 0=inactive)
6
TKF
Touch key interrupt (1=active; 0=inactive)
7
¾
Unused bit, read as ²0²
Unused bit, read as ²0²
INTC1 Register
Rev. 1.00
14
July 19, 2011
HT46R75D-3
Interrupts for Touch Key Interrupt
purposes only. Device trimming during the manufacturing
process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the
power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a resistance/frequency reference point, it can be noted that
with an external 120kW resistor connected and with a 5V
voltage power supply and temperature of 25°C degrees,
the oscillator will have a frequency of 4MHz within a tolerance of 2%. Here only the OSC1 pin is used, which is
shared with I/O pin PA6, leaving pin PA5 free for use as a
normal I/O pin.
The Touch Key interrupt is initialised by setting the
Touch Key interrupt request flag, TKF, bit 6 of INTC1.
This is caused by a signal completion of the Touch Key
sensor. After the interrupt is enabled, and the stack is
not full, and the TKF bit is set, a subroutine call to location 18H occurs. The related interrupt request flag, TKF,
will be reset and the EMI bit is cleared to disable further
maskable interrupts.
Oscillator Configuration
The device provides three system oscillator circuits
known as a crystal oscillator (HXT), an external RC oscillator (ERC) and an internal high speed RC oscillator
(HIRC) which are used for the system clock. There are
also an internal 12kHz RC (LIRC) and a 32.768kHz
crystal oscillator (LXT) which can provide a source clock
for the WDT clock named fS, the LCD driver clock
named fSUB and the Timer/Event counters low frequency clock named fL for various timing purposes.
V
R
D D
O S C
O S C 1
4 7 0 p F
P A 5
In the Power down mode, the system oscillator, the internal 12kHz RC oscillator (LIRC) or the external
32.768kHz crystal oscillator (LXT) may be enabled or
disabled depending upon the corresponding clock control bit described in the relevant sections. The system
can be woken-up from the Power down mode by the occurrence of an interrupt, a transition determined by configuration options on any of the Port A pins, a WDT
overflow or a timer overflow.
External RC Oscillator - ERC
Internal RC Oscillator - HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal
RC oscillator has three fixed frequencies of either
4MHz, 8MHz or 12MHz. Device trimming during the
manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that
the influence of the power supply voltage, temperature
and process variations on the oscillation frequency are
minimised. As a result, at a power supply of either 3V or
5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 4MHz, 8MHz or 12MHz will have a
tolerance within 2%. Note that if this internal system
clock option is selected, as it requires no external pins
for its operation, I/O pins PA5 and PA6 are free for use
as normal I/O pins.
External Crystal/ Ceramic Oscillator - HXT
The External Crystal/Ceramic System Oscillator is one
of the system oscillator choices, which is selected via
configuration options. For most crystal oscillator configurations, the simple connection of a crystal across
OSC1 and OSC2 will create the necessary phase shift
and feedback for oscillation, without requiring external
capacitors. However, if a resonator instead of crystal is
connected between OSC1 and OSC2, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually
require two small value capacitors, C1 and C2, to be
connected for oscillation to occur. The values of C1 and
C2 should be selected in consultation with the crystal or
resonator manufacturer¢s specification.
H o lte k M C U
O S C 1
R f
R p
C i1
C i2
O S C 2
T o in te r n a l
c ir c u its
External RC Oscillator - ERC
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
Using the ERC oscillator only requires that a resistor, with
a value between 24kW and 1.5MW, is connected between
OSC1 and VDD, and a capacitor is connected between
OSC1 and ground, providing a low cost oscillator configuration. It is only the external resistor that determines the
oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability
Rev. 1.00
External Crystal/Ceramic Oscillator
15
July 19, 2011
HT46R75D-3
External 32.768kHz Crystal Oscillator - LXT
LXT Oscillator Low Power Function
The External 32.768kHz Crystal Oscillator is one of the
low frequency oscillator choices, which is selected via a
configuration option. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal
to be connected between pins OSC3 and OSC4. The
external resistor and capacitor components connected
to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are
essential, these components may be required to provide
frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to
start-up.
The LXT oscillator can function in one of two modes, the
Quick Start Mode and the Low Power Mode. The mode
selection is executed using the QOSC bit in the CTRL0
register.
C 1
R p
3 2 7 6 8 H z
N o te : 1 . R
2 . R
3 . A
p
T o in te r n a l
c ir c u its
O S C 4
C 2
T C O S
p , C 1 a
lth o u g h
a r a s itic
C : w ith o u t b u
n d C 2 a re re
n o t s h o w n p
c a p a c ita n c e
ild - in
q u ir e
in s h
o f a r
R C
d .
a v e a
o u n d 7 p F .
When the microcontroller enters the Power down Mode,
the system clock is switched off to stop microcontroller
activity and to conserve power. However, in many
microcontroller applications it may be necessary to keep
the internal timers operational even when the
microcontroller is in the Power down Mode. To do this,
another clock, independent of the system clock, must be
provided.
32768Hz
8pF
10pF
1
Low-power
The Internal 12kHz RC Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. It is a fully integrated RC oscillator with a
typical period of approximately 65ms at 5V, requiring no
external components for its implementation. If the system enters the Power Down Mode, the internal RC oscillator can still continue to run if its clock is necessary to
be used to clock the functions for timing purpose such
as the WDT function, LCD Driver or Timer/Event Counters. The internal RC oscillator can be disabled only
when it is not used as the clock source for all the peripheral functions determined by the configuration options of
the WDT function and the relevant control bits which determine the clock is enabled or disabled for related peripheral functions.
LXT Oscillator C1 and C2 Values
C2
Quick Start
Internal 12kHz Oscillator - LIRC
The exact values of C1 and C2 should be selected in
consultation with the crystal or resonator manufacturer¢s specification. The external parallel feedback resistor, Rp, is required.
C1
0
It should be noted that, no matter what condition the
QOSC bit is set to, the LXT oscillator will always function
normally; the only difference is that it will take more time
to start up if in the Low-power mode.
External 32.768kHz Oscillator - LXT
Crystal Frequency
LXT Mode
After power on the QOSC bit will be automatically
cleared to zero ensuring that the LXT oscillator is in the
Quick Start operating mode. In the Quick Start Mode the
LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can
be placed into the Low-power mode by setting the
QOSC bit high. The oscillator will continue to run but
with reduced current consumption, as the higher current
consumption is only required during the LXT oscillator
start-up. In power sensitive applications, such as battery
applications, where power consumption must be kept to
a minimum, it is therefore recommended that the application program sets the QOSC bit high about 2 seconds
after power-on.
H o lte k M C U
O S C 3
QOSC Bit
Note: 1. C1 and C2 values are for guidance only.
2. RP=5M~10MW is recommended.
32.768kHz Crystal Recommended
Capacitor Values
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HT46R75D-3
System oscillator
HXT
fSYS
ERC
CPU
HIRC
HALT
HALT,
OSCEN
System Oscillator
Configuration Options
Low Speed Oscillators
RTCEN
(CTRL1)
LXT
LIRCEN[1:0]
(WDTC)
LIRC
fL
Timer/Event Counter
0, 1, 2
LFS (CTRL0)
fSUB
LCD Driver
FSUBC (CTRL0)
fS
WDT
fSYS/4
fS Configuration Option
Watchdog Timer - WDT
regulator is to be used for the WDT Temperature-coefficient adjustment. In this case, the application
program should enable the regulator before switching to
the Regulator source. The LIRCEN1 and LIRCEN0 bits
can be used to enable or disable the LIRC oscillator (12
kHz). If the application does not use the LIRC oscillator,
then it needs to disable it in order to save power. When
the LIRC oscillator is disabled, then it is actually turned
off, regardless of the setting of the relevant control bits
which select the LIRC oscillator as its clock source. When
the LIRC oscillator is enabled, it can be used as the clock
source in the Power Down mode defined by the corresponding control bits of the peripheral functions.
The WDT is implemented using an internal 12kHz RC
oscillator known as LIRC, an external 32.768kHz crystal
oscillator or the instruction clock which is the system
clock divided by 4. The timer is designed to prevent a
software malfunction or sequence from jumping to an
unknown location with unpredictable results. The watchdog timer can be disabled by a configuration option. If
the watchdog timer is disabled, the WDT timer will have
the same manner as in the enable-mode except that the
timeout signal will not generate a chip reset. So in the
watchdog timer disable mode, the WDT timer counter
can be read out and can be cleared. This function is
used for the application program to access the WDT frequency to get the temperature coefficient for analog
component adjustment. The LIRC oscillator can be disabled or enabled by the oscillator enable control bits
WDTOSC1 and WDTOSC0 in the WDT control register
WDTC for power saving reasons.
Once the internal 12kHz RC oscillator LIRC with period
65ms normally is selected, it is divided by max. 215 to get
the time-out period of approximately 2.15s. This
time-out period may vary with temperature, VDD and
process variations.
There are 2 registers related to the WDT function named
WDTC and WDTD. The WDTC register can control the
WDT oscillator enable/disable and the WDT power
source. The WDTD register is the WDT counter content
register and this register is read only.
The WDT clock source may also come from the instruction clock, in which case the WDT will operate in the
same manner except that in the Power Down mode the
WDT may stop counting and lose its protecting purpose.
In this situation the device can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip LIRC oscillator is strongly
recommended, since the HALT instruction will stop the
system clock.
The LIRC oscillator power source selection bits named
LIRCPWR1 and LIRCPWR0 can be used to choose the
LIRC oscillator power source, the LIRC oscillator default
power source is from VOCHP. The main purpose of the
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HT46R75D-3
Of these two types of instruction, only one type of instruction can be active at a time depending on the configuration option - ²CLR WDT² times selection option. If
the ²CLR WDT² is selected (i.e., CLR WDT times equal
one), any execution of the ²CLR WDT² instruction clears
the WDT. If the ²CLR WDT1² and ²CLR WDT2² option is
chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT, otherwise the WDT may reset the chip due to a time-out.
The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the Power
Down Mode, the overflow initializes a ²warm reset², and
only the PC and SP are reset to zero. There are three
methods to clear the contents of the WDT, an external
reset (a low level on RES), a software instruction or a
²HALT² instruction. There are two types of software instructions; the single ²CLR WDT² instruction, or the pair
of instructions - ²CLR WDT1² and ²CLR WDT2².
Bit No.
Label
Function
The LIRC oscillator power source selection.
01: LIRC power comes from VOCHP
LIRCPWR0~ 10: LIRC power comes from Regulator
00/11: LIRC power comes from VOCHP
LIRCPWR1
It is strongly recommend to use ²01² for VOCHP to prevent the noise to let the LIRC lose
the power
0
1
2
3
LIRCEN0~
LIRCEN1
4
¾
The LIRC oscillator enable/disable control bits
01: LIRC oscillator is disabled
10: LIRC oscillator is enabled
00/11: LIRC oscillator is enabled
It is strongly recommended to use ²10² for LIRC OSC enable
Reserved
WS2~WS0: WDT prescaler rate select
5
6
7
WS0
WS1
WS2
WS2
WS1
WS0
WDT Rate
0
0
0
28/fS
0
0
1
29/fS
0
1
0
210/fS
0
1
1
211/fS
1
0
0
212/fS
1
0
1
213/fS
1
1
0
214/fS
1
1
1
215/fS
WDTC (1CH) Register
Note: The initial value of the LIRCEN1 and LIRCEN0 bits will be set to ²10² to enable the LIRC oscillator if both the
WDT function is enabled and the WDT clock is selected from the LIRC oscillator determined by the configuration options. Otherwise, the initial value of these two bits will be set to ²01².
The WDT clock (fS) is further divided by an internal counter to give longer watchdog time-out period. In this device, the division ratio can be varied by selecting different values of WS2~WS0bits to give 28/fS to 215/fS division
ratio range.
Bit No.
Label
0~7
WDTD0~
WDTD7
Function
The WDT Counter value (bit4 ~ bit11)
This register is read only and used for temperature adjusting.
WDTD (1DH) Register
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HT46R75D-3
V O C H P
V O R E G
L IR C
P W R
C L R W D T 1 F la g
C L R W D T 2 F la g
1 /2 In s tr u c tio n s
O S C
E n a b le
L IR C
O S C
fL
IR C
L X T O S C
E n a b le
L X T
O S C
fL
X T
L IR C
fS
Y S
/4
C o n tro l
L o g ic
W D T S o u rc e
C o n fig u r a tio n
O p tio n
C L R
fS
1 5 - B it C o u n te r
W D T D iv
W S 2 ~ W
2 8/fS ,
2 11/fS ,
2 14
b 4 ~ b 1 1
is io n
W D T
S 0
E N /D IS
2 9/fS , 2 10/fS ,
2 12/fS , 2 13/fS ,
/fS , 2 15/fS
W D T
T im e - o u t
D a ta B u s
Watchdog Timer
Buzzer Output
The buzzer is driven by the Timer/Event Counter 0 or
Timer/Event Counter 1 overflow signal divided by 2 selected by the clock source selection bit named BZCS in
the CTRL1 register.
The Buzzer function provides a means of producing a
variable frequency output, suitable for applications such
as Piezo-buzzer driving or other external circuits that require a precise frequency generator. The BZ and BZ
pins form a complimentary pair, and are pin-shared with
I/O pins, PA1 and PA2. The selection bits named BZS
and BZS in the SFS register are used to select the
buzzer options. Note that the BZ pin is the inverse of the
BZ pin which together generates a differential output
which can supply more power to connected interfaces
such as buzzers.
If the software selection bits have selected both pins
PA1 and PA2 to function as a BZ and BZ complementary
pair of buzzer outputs, then for correct buzzer operation
it is essential that both pins must be setup as outputs by
setting bits PAC1 and PAC2 of the PAC port control register to zero. The PA1 data bit in the PA data register
T im e r O v e r flo w
B u z z e r C lo c k
P A 1 D a ta
P A 2 D a ta
B Z O u tp u t a t P A 1
B Z O u tp u t a t P A 2
Buzzer Output Pin Control
PAC Register
PAC1
PAC Register
PAC2
PA Data Register
PA1
PA Data Register
PA2
Output Function
0
0
0
X
PA1=²0², PA2=²0²
0
0
1
X
PA1=BZ, PA2=BZ
0
1
0
X
PA1=²0², PA2=Input Line
0
1
1
X
PA1=BZ, PA2=Input Line
1
0
1
X
PA1=Input Line, PA2=BZ
1
0
0
X
PA1=Input Line, PA2=²0²
1
1
X
X
PA1=Input Line, PA2=Input Line
²X² stands for don¢t care
PA1/PA2 Pin Function Control
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HT46R75D-3
must also be set high to enable the buzzer outputs, if set
low, both pins PA1 and PA2 will remain low. In this way
the single bit PA1 of the PA data register can be used as
an on/off control for both the BZ and BZ buzzer pin outputs. Note that the PA2 data bit in the PA data register
has no control over the BZ buzzer pin PA2.
· The contents of the on-chip Data Memory and of the
If software selection bits have selected that only the PA1
pin is to function as a BZ buzzer pin, then the PA2 pin
can be used as a normal I/O pin. For the PA1 pin to function as a BZ buzzer pin, PA1 must be setup as an output
by setting bit PAC1 of the PAC port control register to
zero. The PA1 data bit in the PA data register must also
be set high to enable the buzzer output, if set low pin
PA1 will remain low. In this way the PA1 bit can be used
as an on/off control for the BZ buzzer pin PA1. If the
PAC1 bit of the PAC port control register is set high, then
pin PA1 can still be used as an input even though the
software selection bit has configured it as a BZ buzzer
output.
· The LCD driver keeps running if the LCD clock fSUB is
registers remain unchanged.
· The WDT is cleared and starts recounting (if the WDT
clock source is from the LIRC or the LXT oscillator).
· All I/O ports maintain their original status.
· The PDF flag is set but the TO flag is cleared.
enabled by setting the FSUBC bit to ²1² and the
LCDON bit in the HALTC register is set to ²1².
The system leaves the Power down mode by means of
an external reset, an interrupt, an external transition signal on Port A, or a WDT overflow. An external reset
causes device initialisation, and the WDT overflow performs a ²warm reset². After examining the TO and PDF
flags, the reason for chip reset can be determined. The
PDF flag is cleared by system power-up or by executing
the ²CLR WDT² instruction, and is set by executing the
²HALT² instruction. On the other hand, the TO flag is set if
WDT time-out occurs, and causes a wake-up that only resets the program counter and SP, and leaves the others
in their original state.
Note that no matter what the software selection bit is
chosen for the buzzer, if the port control register has
setup the pin to function as an input, then this will override the software selection and force the pin to always
behave as an input pin. This arrangement enables the
pin to be used as both a buzzer pin and as an input pin,
so regardless of the software selection chosen; the actual function of the pin can be changed dynamically by
the application program by programming the appropriate port control register bit.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each pin
of port A can be independently selected to wake-up the
device using the corresponding wake-up control bits. After awakening from an I/O port stimulus, the program
will resume execution at the next instruction. However, if
awakening from an interrupt, two sequences may occur.
If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. But if the interrupt is
enabled, and the stack is not full, the regular interrupt response takes place.
Note: The Buzzer Output Pin Control drawing shows the
situation where both pins PA1 and PA2 are selected by
software selection bits to be BZ and BZ buzzer pin outputs. The Port Control Register of both pins must have
already been setup as outputs. The data setup on pin
PA2 has no effect on the buzzer outputs.
When an interrupt request flag is set before entering the
²HALT² status, the system cannot be awakened using
that interrupt.
Power Down Operation - HALT
If a wake-up events occur, it takes 1024 tSYS (system
clock periods) or 2 tSYS depending upon the SST configuration option value, the OSCON bit setting and the selected system oscillator type to resume normal
operation. In other words, a dummy period is inserted
after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine
execution is delayed by more than one cycle. However,
The Power down mode is initialised by the ²HALT² instruction and results in the following.
· The system oscillator stops running if the system os-
cillator is selected to be turned off by clearing the
OSCON bit in the HALTC register to zero. Otherwise,
the system oscillator will keep running if it is selected
to be turned on in the power down mode.
Bit No.
Label
Function
0
LCDON
LCD module state in Power down mode
1: LCD module remains on (if fSUB is active) regardless of the configuration option setting
0: LCD state is determined by the LCD_ON configuration option
1~6
¾
7
OSCON
Reserved, read as ²0²
System oscillator state in Power down mode
1: System oscillator keeps running in Power down mode
0: System oscillator stops running in Power down mode
HALTC Register
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20
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HT46R75D-3
set conditions. Most registers are reset to their initial
conditions once the reset conditions are met. By examining the PDF and TO flags, the program can distinguish
between different chip resets.
if the wake-up results in the next instruction execution,
the execution will be performed immediately after the
dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
System
Oscillator
TO
PDF
SST
Time
0
0
RES reset during power-up
u
u
RES or LVR reset during normal operation
0
1024 tSYS
0
1
RES Wake-up HALT
1
2 tSYS
1
u
WDT time-out during normal operation
1
1
WDT Wake-up HALT
SST Configuration OSCON
Option
Bit
HXT
x
ERC
HIRC
RESET Conditions
0
0
1024 tSYS
0
1
2 tSYS
Note: ²u² stands for unchanged
1
x
2 tSYS
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 or 2 system clock pulses dependent
upon the configuration option and software setting when
the system awakes from the HALT state or during
power-up. Awaking from the HALT state or system
power-up, the SST delay is added.
0
0
1024 tSYS
0
1
2 tSYS
1
x
2 tSYS
x: don¢t care
System Start-up Time (SST) Period
An extra SST delay is added during the power-up period, and any wake-up from HALT may enable only the
SST delay.
Reset
There are several ways in which a reset may occur.
The functional unit chip reset status is shown below.
· RES is reset during normal operation
· RES is reset during HALT
Program Counter
000H
· Low Voltage Reset
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT
Cleared. After master reset,
WDT starts counting
Timer/Event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
· WDT time-out is reset during normal operation
The WDT time-out during Power Down Mode differs
from other chip reset conditions, for it can perform a
²warm reset² that resets only the program counter and
SP and leaves the other circuits at their original state.
Some registers remain unaffected during any other reV D D
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
H A L T
Reset Timing Chart
W a rm
R e s e t
W D T
V
V
D D
D D
1 0 0 k W
1 0 0 k W
R E S
O S C 1
R E S
0 .1 m F
B a s ic
R e s e t
C ir c u it
1 0 k W
0 .1 m F
E x te rn a l
R E S
0 .0 1 m F
H i-n o is e
R e s e t
C ir c u it
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
C o ld
R e s e t
R e s e t
Reset Configuration
Reset Circuit
Note: Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the
Hi-noise Reset Circuit.
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21
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HT46R75D-3
The register states are summarized below:
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
IAR0
---- ----
---- ----
---- ----
---- ----
---- ----
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuuuuuu
uuuu uuuu
IAR1
---- ----
---- ----
---- ----
---- ----
---- ----
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
BP
---- ---0
---- ---0
---- ---0
---- ---0
---- ---u
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
CTRL0
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTRL1
---- --01
---- --01
---- --01
---- --01
---- --uu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1000
0000 1000
0000 1000
0000 1000
uuuu uuuu
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
0000 1000
0000 1000
0000 1000
0000 1000
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
PBC
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
ADCR
-000 x000
-000 x000
-000 x000
-000 x000
-uuu xuuu
ADCD
0000 -111
0000 -111
0000 -111
0000 -111
uuuu -uuu
WDTC
111- ss01
111- ss01
111- ss01
111- ss01
uuu- uuuu
WDTD
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
INTC1
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
CHPRC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR2H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR2L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR2C
0000 1000
0000 1000
0000 1000
0000 1000
uuuu uuuu
HALTC
0--- ---0
0--- ---0
0--- ---0
0--- ---0
u--- ---u
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTRL1
00-- --01
00-- --01
00-- --01
00-- --01
uu-- --uu
VIBRC
---- ---0
---- ---0
---- ---0
---- ---0
---- ---u
REGC
---- ---0
---- ---0
---- ---0
---- ---0
---- ---u
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAWK
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
LCDOUT
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HT46R75D-3
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
PAPU
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
PBPU
--00 0000
--00 0000
--00 0000
--00 0000
--uu uuuu
PCPU
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
Register
SFS
---- --00
---- --00
---- --00
---- --00
---- --uu
LCDC
-0-0 -000
-0-0 -000
-0-0 -000
-0-0 -000
-u-u -uuu
MFIC
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
TKM016DH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM016DL
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM0C0
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM0C1
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM0C2
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM0C3
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
Note: ²*² stands for warm reset
²u² stands for unchanged
²-² not implement
²x² stands for unknown
²s² stands for ²depending upon the configuration options². Refer to the WDT section for more details.
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Timer/Event Counter
Three timer/event counters are implemented in the
microcontroller. Timer/Event Counter 0 contains an 8-bit
programmable count-up counter whose clock may
come from an external source or an internal clock
source. An internal clock source comes from fSYS or the
Internal low frequency clock known as fL. The clock fL is
derived from the LIRC or LXT oscillator and can be selected by the Low Frequency selection bit LFS bit in the
CTRL0 register. Timer/Event Counter 1 contains a
16-bit programmable count-up counter whose clock
may come from an external source or an internal clock
source. An internal clock source comes from fSYS/4 or
the Internal low frequency clock known as fL. The clock
fL is derived from the LIRC or LXT oscillator and can be
selected by the Low Frequency selection bit LFS bit in
the CTRL0 register. The external clock input allows the
user to count external events, measure time intervals or
pulse widths, or to generate an accurate time base.
Timer/Event Counter 2 contains a 16-bit programmable
count-up counter whose clock may come from an external source or an internal clock source. An internal clock
source comes from fSYS/4 or the the internal low frequency clock known as fL. The external clock input allows the user to count external events, measure time
intervals or pulse widths, or to generate an accurate
time base.
L IR C (1 2 k H z )
M
L X T (3 2 .7 6 8 k H z )
fS
U
X
M
Y S
fL
U
fT
X
T 0 S
0
8 - s ta g e P r e s c a le r
f IN
8 -1 M U X
L F S
There are two registers related to the Timer/Event
Counter 0; TMR0 and TMR0C. Writing to TMR0 puts the
starting value in the Timer/Event Counter 0 register and
reading TMR0 reads out the contents of Timer/Event
Counter 0. The TMR0C is a timer/event counter control
register, which defines the overall operations. There are
three registers related to the Timer/Event Counter 1;
TMR1H, TMR1L and TMR1C. Writing to TMR1L will
only put the written data into an internal lower-order byte
buffer (8-bit) while writing to TMR1H will transfer the
specified data and the contents of the lower-order byte
buffer to both the TMR1H and TMR1L registers, respectively. The Timer/Event Counter 1 preload register is
changed when each time there is a write operation to
TMR1H. Reading TMR1H will latch the contents of
TMR1H and TMR1L counters to the destination and the
lower-order byte buffer, respectively. Reading TMR1L
will read the contents of the lower-order byte buffer.
TMR1C is the Timer/Event Counter 1 control register,
which defines the operating mode, counting enable or
disable, the TMR1 active edge and the prescaler stage
selections. Also there are three registers related to the
Timer/Event Counter 2 named TMR2H, TMR2L and
TMR2C. The operations of reading from and writing to
the Timer/Event Counter 2 registers named TMR2H and
TMR2L are the same with Timer/Event Counter 1 described above.
D a ta B u s
T 0
T 0 M 1
T 0 M 0
T 0 P S C 2 ~ T 0 P S C 0
T M R 0
8 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
8 - b it T im e r /E v e n t C o u n te r
(T M R 0 )
O v e r flo w
to In te rru p t
1 /2
B Z 0
Timer/Event Counter 0
L IR C (1 2 k H z )
L X T (3 2 .7 6 8 k H z )
M
U
fS
X
L F S
Y S
fL
/4
M
U
fT
X
T 1 S
D a ta B u s
1
8 - s ta g e P r e s c a le r
f IN
8 -1 M U X
L o w B y te
B u ffe r
T 1
T 1 M 1
T 1 M 0
T 1 P S C 2 ~ T 1 P S C 0
1 6 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
T 1 E
T M R 1
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T 1 M 1
T 1 M 0
T 1 O N
H ig h B y te
L o w
R e lo a d
O v e r flo w
to In te rru p t
B y te
1 6 - B it T im e r /E v e n t C o u n te r
1 /2
B Z 1
Timer/Event Counter 1
Rev. 1.00
24
July 19, 2011
HT46R75D-3
L IR C
(1 2 k H z )
L X T (3 2 .7 6 8 k H z )
M
fS
U
Y S
fL
X
L F S
/4
M
U
fT
X
T 2 S
2
8 - s ta g e P r e s c a le r
f IN
8 -1 M U X
T 2 P S C 2 ~ T 2 P S C 0
D a ta B u s
T 2
L o w B y te
B u ffe r
T 2 M 1
T 2 M 0
1 6 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
T 2 E
T M R 2
T 2 M 1
T 2 M 0
T 2 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te
L o w
B y te
1 6 - B it T im e r /E v e n t C o u n te r
R e lo a d
O v e r flo w
to In te rru p t
Timer/Event Counter 2
Bit No.
Label
Function
T0PSC0
T0PSC1
T0PSC2
To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT0=fT0
001: fINT0=fT0/2
010: fINT0=fT0/4
011: fINT0=fT0/8
100: fINT0=fT0/16
101: fINT0=fT0/32
110: fINT0=fT0/64
111: fINT0=fT0/128
3
T0E
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T0ON
0
1
2
5
6
7
T0S
T0M0
T0M1
Enable/disable timer counting (0=disabled; 1=enabled)
Defines the TMR0 internal clock source
0: fSYS
1: Low Frequency clock fL
Defines the operating mode T0M1, T0M0=
01: Event count mode (External clock)
10: Timer mode (Internal clock)
11: Pulse Width measurement mode (External clock)
00: Unused
TMR0C (0EH) Register
Rev. 1.00
25
July 19, 2011
HT46R75D-3
Bit No.
Label
Function
T1PSC0
T1PSC1
T1PSC2
To define the prescaler stages, T1PSC2, T1PSC1, T1PSC0=
000: fINT1=fT1
001: fINT1=fT1/2
010: fINT1=fT1/4
011: fINT1=fT1/8
100: fINT1=fT1/16
101: fINT1=fT1/32
110: fINT1=fT1/64
111: fINT1=fT1/128
3
T1E
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1: count on falling edge;
0: count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T1ON
5
T1S
0
1
2
6
7
T1M0
T1M1
Enable/disable timer counting (0=disabled; 1=enabled)
Defines the TMR1 internal clock source
0: fSYS/4
1: Low Frequency clock fL
Defines the operating mode T1M1, T1M0=
01: Event count mode (External clock)
10: Timer mode (Internal clock)
11: Pulse Width measurement mode (External clock)
00: Unused
TMR1C (11H) Register
Bit No.
Label
Function
T2PSC0
T2PSC1
T2PSC2
To define the prescaler stages, T2PSC2, T2PSC1, T2PSC0=
000: fINT2=fT2
001: fINT2=fT2/2
010: fINT2=fT2/4
011: fINT2=fT2/8
100: fINT2=fT2/16
101: fINT2=fT2/32
110: fINT2=fT2/64
111: fINT2=fT2/128
3
T2E
Defines the TMR2 active edge of the timer/event counter:
In Event Counter Mode (T2M1,T2M0)=(0,1):
1: count on falling edge;
0: count on rising edge
In Pulse Width measurement mode (T2M1,T2M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T2ON
5
T2S
0
1
2
6
7
T2M0
T2M1
Enable/disable timer counting (0=disabled; 1=enabled)
Defines the TMR2 internal clock source
0: fSYS/4
1: fL
Defines the operating mode T2M1, T2M0=
01: Event count mode (External clock)
10: Timer mode (Internal clock)
11: Pulse Width measurement mode (External clock)
00: Unused
TMR2C Register
Rev. 1.00
26
July 19, 2011
HT46R75D-3
The TxM0 and TxM1 bits in TMRxC register where x
may be equal to 0, 1 or 2 define the operation mode. The
event count mode is used to count external events,
which means that the clock source must come from the
external (TMR0, TMR1 or TMR2) pin. The timer mode
functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the
pulse width measurement mode can be used to count a
high or low level duration of an external signal on the
TMR0, TMR1 or TMR2 pins with the timing based on the
internally selected clock source.
strongly recommended to load a desired value into the
Timer/Event Counter Register TMRx or TMRxH/TMRxL
first, before turning on the related timer/event counter,
for proper operation since the initial value of TMRx or
TMRxH/TMRxL is unknown. Due to the Timer/Event
Counter scheme, the programmer should pay special
attention to the instructions which enables then disables
the timer for the first time, whenever there is a need to
use the timer/event counter function, to avoid unpredictable results. After this procedure, the timer/event function can be operated normally.
In the event count or timer mode, the Timer/Event Counter starts counting at the current contents in the
Timer/Event Counter and ends at FFH for -8-bit counter
or FFFFH for 16-bit counter. Once an overflow occurs,
the counter is reloaded from the timer/event counter
preload register, and generates an interrupt request
flag, T0F, T1F or T2F. In the pulse width measurement
mode with the values of the Timer enable control bit
TxON and the active edge control bit TxE equal to ²1²,
after the TMRx pin has received a transient from low to
high (or high to low if the TxE bit is ²0²), it will start counting
until the TMRx pin returns to the original level and resets
the TxON bit. The measured result remains in the
timer/event counter even if the activated transient occurs
again. Therefore, only a 1-cycle measurement can be
made until the TxON bit is again set. The cycle measurement will re-function as long as it receives further transient
pulses. In this operation mode, the timer/event counter begins counting not according to the logic level but to the
transient edges. In the case of counter overflows, the
counter is reloaded from the timer/event counter register
and issues an interrupt request, as in the other two modes,
i.e., event and timer modes.
The bit0~bit2 of the Timer/Event Counter control register TMRxC can be used to define the pre-scaling stages
of the internal clock sources of Timer/Event Counters.
Input/Output Ports
There are up to 22 bidirectional input/output lines in the
microcontroller, labeled as PA, PB and PC. All of these
I/O ports can be used for input and output operations.
For input operation, these ports are non-latching, that is,
the inputs must be ready at the T2 rising edge of instruction ²MOV A, [m]². For output operation, all the data is
latched and remains unchanged until the output latch is rewritten.
Each I/O line has its own control register, PAC, PBC and
PCC, to control the input/output configuration. With this
control register, CMOS outputs or Schmitt trigger inputs
with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control
register must write ²1². The input source also depends
on the control register. If the control register bit is ²1²,
the input will read the pad state. If the control register bit
is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify-write²
instruction. For output function, CMOS is the only configuration except PA7. These control registers are
mapped to the RAM memory locations respectively.
To enable the counting operation, the Timer enable bit
known as TxON in TMRxC where x indicates 0, 1 or 2
should be set to ²1². In the pulse width measurement
mode, the TxON is automatically cleared after the measurement cycle is completed. But in the other two modes,
the TxON bit can only be reset by instructions. The overflow of the Timer/Event Counters is one of the wake-up
sources. No matter what the operation mode is, writing a
²0² to the related Timer/Event counter interrupt enable
control bit ETxI disables the related interrupt service.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
and 15H.
After a chip reset, these input/output lines remain at high
levels or in a floating state, depending upon the pull-high
configuration options. Each bit of these input/output
latches can be set or cleared by ²SET [m].i² and ²CLR
[m].i² instructions.
In the case of a Timer/Event Counter OFF condition,
writing data to the timer/event counter preload register
also reloads that data to the timer/event counter. But if
the timer/event counter is turned on, data written to the
timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
When the Timer/Event Counter Register TMRx or
TMRxH/TMRxL is read, the clock is blocked to avoid errors, however as this may result in a counting error, it
should be taken into account by the programmer. It is
Rev. 1.00
Each line of port A has the capability of waking-up the
device.
27
July 19, 2011
HT46R75D-3
V
D a ta B u s
W r ite C o n tr o l R e g is te r
P u ll- H ig h
O p tio n
C o n tr o l B it
Q
D
Q
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
S
Q
M
P A 1 , P A 2
B Z , B Z
M
R e a d D a ta R e g is te r
S y s te m
U
U
X
E N
X
W a k e -u p
( P A o n ly )
P A W K 0 ~ P A W K 6
D D
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
/V IB
/B Z
/B Z
/O S
/O S
/O S
/O S
P B 0
P B 1
P B 2
P B 3
P B 4
P B 5
/T K
/T K
/T K
/T K
/IN
/T M
P C 0
P C 1
P C 2
P C 3
P C 4
P C 5
P C 6
P C 7
/T M
/T M
/S E
/S E
/S E
/S E
/S E
/S E
C 4
C 3
C 2
C 1
0
1
T
2
3
R 0
R 1 /S E G 0
R 2 /S E G 1
G 2
G 3
G 4
G 5
G 6
G 7
T M R 0 , T M R 1 , T M R 2 , IN T
Input/Output Ports
D a ta B u s
W r ite C o n tr o l R e g is te r
C o n tr o l B it
Q
D
C K
Q
S
C h ip R e s e t
P A 7 /R E S
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
R e a d D a ta R e g is te r
S y s te m
U
X
W a k e -u p (P A 7 )
P A W K 7
R E S fo r P A 7 o n ly
PA7 Pin
Rev. 1.00
28
July 19, 2011
HT46R75D-3
Each pin of these three I/O ports except PA7 pin has a
pull-high resistor determined by a software option. Once
the pull-high software option is selected, the I/O pin has
a pull-high resistor connected. Take note that a
non-pull-high I/O pin setup as an input will be in a floating condition.
input mode always retains its original function. Once the
software selection bits are selected as the BZ/BZ function, the buzzer output signals are controlled by the PA1
data register.
It is recommended that unused or not bonded out I/O
lines should be set as output pins using software instructions to avoid consuming power when in an input
floating state.
PA1 and PA2 are pin-shared with BZ and BZ signal, respectively. If the software selection bits are selected
these pins as buzzer function, the output signals in the
output mode of PA1/PA2 can be the buzzer signal. The
· I/O Register Lists
Register
Name
Bit
7
6
5
4
3
2
1
0
BZS
SFS
¾
¾
¾
¾
¾
¾
BZBS
PA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PAC
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAWK
PAWK7
PAWK6
PAWK5
PAWK4
PAWK3
PAWK2
PAWK1
PAWK0
PAPU
¾
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PB
¾
¾
PB5
PB4
PB3
PB2
PB1
PB0
PBC
¾
¾
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU0
PBPU
¾
¾
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PCC
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
PCPU7
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
²¾² Unimplemented, read as ²0²
PAn, PBn, PCn: I/O line data bit.
PACn, PBCn, PCCn: I/O line control bit.
PAPUn, PBPUn, PCPUn: I/O line pull-high control.
0: disabled
1: enabled
PAWKn: Port A wake-up control.
0: disabled
1: enabled
· SFS Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
¾
BZBS
BZS
R/W
¾
¾
¾
¾
¾
¾
R/W
R/W
POR
¾
¾
¾
¾
¾
¾
0
0
Bit 7~2
²¾² Unimplemented, read as ²0²
Bit 1
BZBS: PA2 pin-shared function selection
0: I/O
1: BZ
Bit 0
BZS: PA1 pin-shared function selection
0: I/O
1: BZ
Rev. 1.00
29
July 19, 2011
HT46R75D-3
Charge Pump and Voltage Regulator
There is one charge pump and one voltage regulator implement in this device.
If the REGCEN bit is set to 0, the regulator will be disabled. When the regulator is disabled, the regulator output can be connected to a grounded resistor to allow its
output to fall to zero rapidly. The regulator output can
also be selected to be in a floating state. The VOSW bit
in the REGC register is used to select the regulator output state when the regulator is disabled.
The charge pump can be enabled or disabled by the application program. The charge pump uses VDD as its input, and has the function of doubling the VDD voltage.
The output voltage of the charge pump will be VDDx2.
The regulator can generate a stable voltage of 3.3V, for
internal LIRC oscillator, ADC and also can provide an
external bridge sensor excitation voltage or supply a reference voltage for other applications. The user needs to
guarantee the charge pump output voltage is greater
than 3.6V to ensure that the regulator generates the required 3.3V voltage output. The block diagram of this
module is shown below.
C H P C 2
C H P C 1
CHPRC is the Charge Pump/Regulator Control register,
which controls the charge pump on/off, regulator on/off
functions as well as setting the clock divider value to
generate the clock for the charge pump.
The CHPCKD4~CHPCKD0 bits are use to set the clock
divider to generate the desired clock frequency for
proper charge pump operation. The actual frequency is
determined by the following formula.
V O R E G
V O C H P
Actual Charge Pump Clock= (fSYS/16)/(CHPCKD +1).
V D D
V D D
C h a rg e P u m p
( V o lta g e D o u b le r )
fS
Y S
D iv id e r
C H P C K D
R e g u la to r
(3 .3 V )
V D D x 2
3 .3 V
The suggested charge pump clock frequency is 20kHz.
The application needs to set the correct value to get the
desired clock frequency. For a 4MHz application, the
CHPCKD bits should be set to the value 11, and for a
2MHz application, the bits should be set to 5.
L IR C
A D C
The REGCEN bit in the CHPRC register is the Regulator/ Charge-pump module enable/disable control bit. If
this bit is disabled, then the regulator will be disabled
and the charge pump will be also be disabled to save
power. When REGCEN = 0, the module will enter the
Power Down Mode ignoring the CHPEN setting. The
ADC and OPA will also be disabled to reduce power.
R E G C E N
C H P E N
Additionally, the device also includes a band gap voltage
generator for the 1.5V low temperature sensitive reference voltage. This reference voltage is used as the zero
adjustment and for a single end type reference voltage.
R e g u la to r
R E F
R
B a n d G a p
E n h a n c e
If REGCEN is set to ²1², the regulator will be enabled. If
CHPEN is enabled, the charge pump will be active and
will use VDD as its input to generate the double voltage
output. This double voltage will be used as the input voltage for the regulator. If CHPEN is set to ²0², the charge
pump is disabled and the charge pump output will be
equal to the charge pump input, VDD.
I
V O B G P
F IL
B G P Q S T b it
0 : O ff (s h o rt)
1 : O n
C
F IL
It is necessary to take care of the VDD voltage. If the voltage is less than 3.6V, then CHPEN should be set to 1 to
enable the charge pump, otherwise CHPEN should be
set to zero. If the Charge pump is disabled and VDD is
less than 3.6V then the output voltage of the regulator
will not be guaranteed.
RFIL is about 100kW and the recommend CFIL is 10mF.
Note: VOBGP signal is only for chip internal used.
Don¢t connect to external component except the
recommend CFIL
· REGC Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
¾
¾
VOSW
R/W
¾
¾
¾
¾
¾
¾
¾
R/W
POR
¾
¾
¾
¾
¾
¾
¾
0
Bit 7~1
²¾² Unimplemented, read as ²0²
Bit 0
VOSW: Voltage regulator output selection
0: VOREG is connected a resistor to ground
1: VOREG is in a floating state.
Rev. 1.00
30
July 19, 2011
HT46R75D-3
Bit No.
Label
0
REGCEN
1
CHPEN
2
3~7
Function
Enable/disable Regulator/Charge-Pump module. (1=enable; 0=disable)
Charge Pump Enable/disable setting. (1=enable; 0=disable)
Note: this bit will be ignore if the REGCEN is disable
BGPQST
Band gap quickly start-up function
0: R short, quickly start
1: R connected, normal RC filter mode
Every time when REGCEN change from 0 to 1 (Regulator turn on) This bit should be set
to 0 and then set to 1 to make sure the quickly stable. (the minimum 0 keeping time is
about 2ms now )
The Charge pump clock divider. This 5 bits can form the clock divide by 1~32.
CHPCKD0~
Following the below equation:
CHPCKD4
Charge Pump clock = (fSYS/16) / (CHPCKD+1)
CHPRC (1FH) Register
REGCEN CHPEN
Charge
Pump
VOCHP
Regulator
Pin
VOREG Pin OPA ADC
Description
The whole module is disable,
OPA/ADC will lose the Power
0
X
OFF
VDD
OFF
Hi-Impedance
Disable
1
0
OFF
VDD
ON
3.3V
Active
Use for VDD is greater than 3.6V
(VDD>3.6V)
1
1
ON
2´VDD
ON
3.3V
Active
Use for VDD is less than 3.6V
(VDD=2.2V~3.6V)
ADC - Dual Slope
ADDISCH1 and ADDISCH0, are used to control the
Dual slope circuit charging and discharging behavior.
The ADCMPO bit is read only for the comparator output,
while the ADINTM bits can set the ADCMPO trigger
mode for interrupt generation. The ADC PGA input signal can come from the DCHOP, TH/LB or AI pin selected by the ADIS selection bit in ADCD register. The
PGA gain can be either 2 or 4 determined by the PGAG
gain selection bit in the ADCD register. The reference
voltages of the ADC integrator and comparator named
VINT and VCMP shown in the Dual Slope ADC structure
diagram can be selected by the ADRR0 selection bit.
A Dual Slope A/D converter is implemented in this
microcontroller. The dual slope module includes an Operational Amplifier, a Programmable Gain Amplifier PGA
for the amplification of differential signals, an Integrator
and a comparator for the main dual slope AD converter.
There are 2 special function registers related to this
function known as ADCR and ADCD. The ADCR register is the A/D control register, which controls the ADC
block power on/off, the chopper clock on/off, the
charge/discharge control and is also used to read out
the comparator output status. The ADCD register is the
A/D Chopper clock divider register, which defines the
chopper clock to the ADC module.
Dual Slope ADC Operation
The ADPWREN bit, defined in ADCR register, is used to
control the ADC module on/off function. The ADCCKEN
bit defined in the ADCR register is used to control the
chopper clock on/off function. When ADCCKEN is set to
²1² it will enable the Chopper clock, with the clock frequency defined by the ADCD register. The ADC module
includes the OPA, PGA, integrator and comparator.
However, the Bandgap voltage generator is independent of this module. It will be automatically enabled when
the regulator is enabled, and also be disabled when the
regulator is disabled. The application program should
enable the related power to permit them to function and
disable them when entering the power down mode to
conserve power. The charge/discharge control bits,
Rev. 1.00
The following descriptions are based on the fact that the
ADRR0 bit is set to ²0².
C o m p a ra to r
4 /6 V D S O
1 /6 V D S O
+
A D C M P O
In te g r a to r
D S R R
V
D S C C
D S R C
V
A
R
D S
C
C
D S
The amplifier and buffer combination, form a differential input pre-amplifier which amplifies the sensor input signal.
31
July 19, 2011
HT46R75D-3
Bit No.
Label
Function
0
1
2
ADCD0
ADCD1
ADCD2
Define the chopper clock (ADCCKEN should be enable), the suggestion clock is around
10kHz.
The chopper clock define :
0: clock= (fSYS/32)/1
1: clock= (fSYS/32)/2
2: clock= (fSYS/32)/4
3: clock= (fSYS/32)/8
4: clock= (fSYS/32)/16
5: clock= (fSYS/32)/32
6: clock= (fSYS/32)/64
7: clock= (fSYS/32)/128
3
¾
4
ADRR0
ADC integrator and comparator reference voltage selection
0: (VINT, VCMP) = (4/6 VDSO, 1/6 VDSO)
1: (VINT, VCMP) = (4.4/6 VDSO, 1/6 VDSO)
5
6
ADIS0
ADIS1
AD PGA input selection
00: from AI pin
01: from TH/LB pin
10: from DCHOP pin
11: reserved
7
PGAG
ADC PGA gain selection
0: gain = 2
1: gain = 4
Unimplemented, read as ²0²
ADCD (1AH) Register
V D S O
P W R
C o n tro l
V O R E G
R v f1
V
D O P A P
+
A D IS
-
D O P A N
P G A
( G a in = 2 ,4 )
M U X
A m p lifie r
fro m
D C H O P
A D P W R E N
IN T
R v f2
M
V
U
X
+
-
P G A G
C M P
+
In te g ra to r
fro m
T H /L B
R v f3
A D D IS C H 0
A D D IS C H 1
O n C h ip
D O P A O
O ff C h ip
N o te : V
IN T
, V
A D C M P O
C o m p a ra to r
C M P
D C H O P
s ig n a l c a n c o m e fr o m
D S R R
T H /L B
( A D in p u t fo r e x te r n a l
th e r m a l/lo w b a tte r y d e te c tio n
o r o th e r u s a g e )
d iffe r e n t R
D S R C
D S C C
g r o u p s w h ic h a r e s e le c te d b y s o ftw a r e r e g is te r s .
Dual Slope ADC Structure
Rev. 1.00
32
July 19, 2011
HT46R75D-3
1 0 0 k W
2 5 k W
V O R E G
D O P A O
D C H O P
D O P A N
V B
B r id g e
S e n s o r
P G A
C h o p p e r
A m p lifie r
V A
D O P A P
O ff C h ip
2 7 n F
O n C h ip
N o te : A ll " R " a n d " C " v a lu e s h e r e a r e fo r r e fe r e n c e o n ly
Dual Slope ADC with Bridge Sensor input
The combination of the Integrator, the comparator, the
resistor RDS, between DSRR and DSRC and the capacitor CDS, between DSRC and DSCC form the main body
of the Dual slope ADC.
called Ti, which is the integrating time. It will then switch
to the dis-charging mode and wait for Vc to drop to less
than 1/6 VDSO. At this point the comparator will change
state and store the time taken, TC, which is the
de-integrating time. The following formula 1 can then be
used to calculate the input voltage VA.
The Integrator integrates the output voltage increase or
decrease and is controlled by the ²Switch Circuit² - refer
to the block diagram. The integration and de-integration
curves are illustrated by the following.
formula 1: VA= (1/3)´VDSO´(2-Tc/Ti).
(Based on ADRR0=0)
In user applications, it is required to choose the correct
value of RDS and CDS to determine the Ti value, to allow
the VC value to operate between 5/6 VDSO and 1/6
VDSO. VFULL cannot be greater than 5/6 VDSO and
VZERO cannot be less than 1/6 VDSO.
The ²comparator² will switch the state from high to low
when VC, which is the DSCC pin voltage,drops to less
than 1/6 VDSO.
In general applications, the application program will
switch the ADC to the charging mode for a fixed time
V
C
V
F U L L
V
V
Z E R O
1 /6 V D S O
T i
T c (z e ro )
T c
T c ( fu ll)
In te g r a te tim e
Rev. 1.00
D e - In te g r a te tim e
33
July 19, 2011
HT46R75D-3
Bit No.
0
Label
Function
ADPWREN
Dual slope block (including input OP) power on/off switching.
0: disable Power
1: Power source comes from the regulator.
Defines the ADC discharge/charge. (ADDISCH1:0)
00: reserved
ADDISCH0~
01: charging (Integrator input connect to buffer output)
ADDISCH1
10: discharging (Integrator input connect to VDSO)
11: reserved
1~2
ADCMPO
Dual Slope ADC - last stage comparator output.
Read only bit, write data instructions will be ignored.
During the discharging state, when the integrator output is less than the reference voltage,
the ADCMPO will change from high to low.
4~5
ADINTM0~
ADINTM1
ADC integrator interrupt mode definition. These two bit define the ADCMPO data interrupt
trigger mode: (ADINTM1:0)=
00: no interrupt
01: rising edge
10: falling edge
11: both edge
6
ADCCKEN
ADC OP chopper clock source on/off switching.
0: disable
1: enable (clock value is defined by ADCD register)
7
¾
3
Unimplemented, read as ²0²
ADCR (18H) Register
LCD Driver
The LCD clock is driven by the fSUB clock, which then
passes through a divider, the division ratio of which is
selected by the LCD clock selection bits LCDCK1 and
LCDCK0 in the CTRL0 register to provide a LCD clock
frequency of fSUB/3, fSUB/4 or fSUB/8. The LCD clock
source fSUB can be derived from the LIRC or LXT oscillator selected by the selection bit named FSUBS. Note
that the fSUB clock can be enabled or disabled in the
power down mode by the fSUB clock control bit FSUBC
in the CTRL0 register.
LCD Display Memory
The device provides an area of embedded data memory
for the LCD display. This area is located at 40H to 5BH in
Bank 1 of the Data Memory. The bank pointer BP enables either the General Purpose Data Memory or LCD
Memory to be chosen. When BP is set to ²1², any data
written into location range 40H~5BH will affect the LCD
display. When the BP is cleared to ²0², any data written
into 40H~5BH will access the general purpose data
memory. The LCD display memory can be read and written to only indirectly using MP1. When data is written
into the display data area, it is automatically read by the
LCD driver which then generates the corresponding
LCD driving signals. To turn the display on or off, a ²1² or
a ²0² is written to the corresponding bit of the display
memory, respectively. The figure illustrates the mapping
between the display memory and LCD pattern for the
device.
4 0 H
C O M
4 1 H
4 2 H
4 3 H
5 9 H
5 A H
5 B H
0
1
1
2
2
S E G M E N T
The output number of the LCD driver device can be configured as 24´8 to 28´4 using the corresponding software selection bits. The LCD driver bias type can be ²R²
type or ²C² type determined by the RCS bit in the LDC
register. The LCD driver has a fixed 1/3 bias value. If the
²C² type bias is selected, a capacitor mounted between
C1 and C2 pins is needed and two capacitors are
needed to be connected to the ground for VAB and VC
pins. All the capacitance of capacitors used for LCD bias
generator is suggested to use the 0.1mF.
B it
0
3
LCD Driver Output
0
3
1
2
3
2 5
2 6
2 7
Display Memory
Rev. 1.00
34
July 19, 2011
HT46R75D-3
· LCDC Register
Bit
7
6
5
4
Name
¾
R/W
¾
POR
¾
3
2
1
0
VAS
¾
R/W
¾
RCS
¾
CSS2
CSS1
CSS0
R/W
¾
R/W
R/W
R/W
0
¾
0
¾
0
0
0
Bit 7
unimplemented, read as 0
Bit 6
VAS: VAB pin voltage selection
0: VAB = VOREG
1: VAB = 1.5 ´ VOREG
This bit is only available when the LCD bias generator is selected to be ²C² type. When the
charge pump output voltage is equal to VDD and the C type bias generator is selected, the VAB
voltage can only be selected as the VOREG voltage. If the charge pump output voltage is equal
to 2´VDD, the VAB voltage can be selected as either the VOREG or 1.5´VOREG voltage.
When ²RCS² is set to ²0² (R type), the user must write ²1² to this bit.
Bit 5
unimplemented, read as 0
Bit 4
RCS: LCD R type or C type bias selection
0: R type
1: C type
Bit 3
unimplemented, read as 0
Bit 2~0
CSS2~CSS0: LCD COM/SEG selection
Theses bits are used to configure the pin-shared COM/SEG function. Depending upon the CSS
bits settings, the LCD driver can be configured as 1/4 to 1/8 duty display. The configurations are
shown in the following table.
Pin-shared Function
Maximum
SEG´COM
CCS2~0
Duty
000
1/4
SEG27
SEG26
SEG25
SEG24
28´4
001
1/5
COM4
SEG26
SEG25
SEG24
27´5
010
1/6
COM4
COM5
SEG25
SEG24
26´6
COM4/SEG27 COM5/SEG26 COM6/SEG25 COM7/SEG24
011
1/7
COM4
COM5
COM6
SEG24
25´7
1xx
1/8
COM4
COM5
COM6
COM7
24´8
· LCDOUT Register
Bit
7
6
5
4
3
2
1
0
Name
LCDS7
LCDS6
LCDS5
LCDS4
LCDS3
LCDS2
LCDS1
LCDS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~1
Rev. 1.00
LCDSn: LCD SEG or I/O function selection
0: I/O function -- Pcn
1: SEG function -- SEGn
35
July 19, 2011
HT46R75D-3
V A
V B
V C
C O M 0
V S S
V A
V B
V C
C O M 1
V S S
V A
V B
V C
C O M 2
V S S
V A
V B
C O M 3
V C
V S S
V A
V B
V C
L C D s e g m e n ts O N
C O M 2 s id e lig h te d
V S S
E x a m p le : 1 /4 d u ty , 1 /3 b ia s , R ty p e , V
A
= V
D D
, V
B
= 2 /3 V
D D
, V
C
= 1 /3 V
D D
LCD Driver Output (1/4 Duty)
Rev. 1.00
36
July 19, 2011
HT46R75D-3
Low Voltage Reset Function
The LVR includes the following specifications:
There is a low voltage reset, LVR, circuit implemented in
the microcontroller. The LVR functions can be enabled
or disabled by the LVR function configuration option.
· The low voltage, which is specified as 0.9V~VLVR, has
to remain within this range for a period of time greater
than 1ms. If the low voltage state does not exceed
1ms, the LVR will ignore it will not perform a reset
function.
The LVR has the same effect or function as the external
RES signal which performs a device reset. When in the
Power down Mode, the LVR function is disabled.
· The LVR has an ²OR² function with the external RES
The microcontroller provides a low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range 0.9V~VLVR,
such as what might happen when changing a battery, the
LVR will automatically reset the device internally.
V
signal to perform a chip reset.
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
R e s e t
N o r m a l O p e r a tio n
R e s e t
*1
*2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since a low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.
Operation Mode
The device has two operational modes. The system clock may come from external RC (ERC), external crystal (HXT) or
internal RC (HIRC) oscillator, and whose operational modes can be either Normal Mode or Power down mode. When in
the Power down mode, the clocks in this device are all enabled or disabled using software.
HALT
Instruction
Mode
System
Oscillator
FSUBC
fSUB Clock
RTCEN
RTC Oscillator
(OSC3/OSC4)
Not executed
Normal
On
x
Enable
x
On
Power Down
On (OSCON=1)
Off (OSCON=0)
0
Disable
1
On
Power Down
On (OSCON=1)
Off (OSCON=0)
1
Enable
1
On
Power Down
On (OSCON=1)
Off (OSCON=0)
0
Disable
0
Off
Power Down
On (OSCON=1)
Off (OSCON=0)
1
Enable
0
Off
Executed
Note: The LIRCEN [1:0] and LIRCPWR [1:0] bits in the WDTC register should be properly configured to enable the
LIRC oscillator and select its power supply source. Otherwise, the LIRC OSC will always be disabled. Refer to
the WDT section for the LIRC oscillator setup details.
Rev. 1.00
37
July 19, 2011
HT46R75D-3
Bit No.
Label
Function
0
QOSC
32.765kHz crystal oscillator quick start-up control
0: quick start-up
1: low-power
1
FSUBS
fSUB Clock source selection
0: LIRC oscillator
1: LXT oscillator
2
FSUBC
fSUB Power down mode clock control
0: disabled
1: enabled
3
4
To select the LCD driver clock:
LCDCK0 00: LCD clock = fSUB/3
LCDCK1 01: LCD clock = fSUB/4
1x: LCD clock = fSUB/8
5
LFS
6
7
¾
Low Frequency clock source fL selection
0: LIRC oscillator
1: LXT oscillator
Reserved, should be kept as ²00².
CTRL0 Register
Bit No.
Label
0
RTCEN
1
BZCS
2~5
¾
6
7
EINTC1
EINTC0
Function
32.768kHz oscillator (LXT) control in Power down mode
0: disabled
1: enabled
Buzzer clock source selection
0: from Timer/Event Counter 0
1: from Timer/Event Counter 1
Unimplemented, read as ²0²
External interrupt trigger edge selection
00: disabled
01: falling edge
10: rising edge
11: double edges
CTRL1 Register
Vibration Sensor Amplifier
The device contains a Vibration Sensor Amplifier to amplify the small electrical signals generated from vibration
sensors. When the sensor is connected to the vibration
input pin, VIB, and a small signal resulting from a vibration detection is generated on the VIB pin, the internal
amplifier will amplify the low amplitude signal which will
then be used as a wake-up source when the device is in
the Power down mode. The Vibration Sensor Amplifier
can be enabled or disable by the control bit, VIBREN, in
the VIBRC register for power saving considerations.
Bit No.
0
1~7
Function
Vibration Sensor Amplifier control
VIBREN 0: disabled
1: enabled
Unimplemented, read as ²0²
¾
VIBRC Register
V IB
V ib r a tio n
S e n s o r
Rev. 1.00
Label
38
A m p lifie r
C ir c u its
M C U
w a k e -u p
V IB R E N
July 19, 2011
HT46R75D-3
Touch Key Module
The device provides four touch key functions. The touch
key function is fully integrated and requires no external
components, allowing touch key functions to be implemented by the simple manipulation of internal registers.
Touch Key Register Definition
The touch key module, which contains four touch key
functions, has its own suite of six registers. The following
table shows the register set for the touch key module.
Touch Key Structure
The touch keys are pin-shared with the PB logic I/O
pins, with the desired function chosen via register bits.
These four keys are organised into a module and it contains its own control logic circuits and register set.
Name
Description
TKM016DH
16-bit C/F counter high byte
TKM016DL
16-bit C/F counter low byte
TKM0C0
Control Register 0
Key Select / x2 frequency / filter control / frequency select
TKM0C1
Control Register 1
Internal reference / Touch pad reference
TKM0C2
Control Register 2
Counter on-off and clear control / reference clock control / TKST start bit
TKM0C3
Control Register 3
Counter overflow bits
Register Description
Bit
Register
Name
7
6
5
4
3
2
1
0
TKM016DH
D7
D6
D5
D4
D3
D2
D1
D0
D0
D7
D6
D5
D4
D3
D2
D1
TKM0C0
TKM016DL
M0MXS1
M0MXS0
D5
D4
D3
D2
D1
D0
TKM0C1
M0K4OEN
M0K3OEN
M0K2OEN
M0K1OEN
M0K4IO
M0K3IO
M0K2IO
M0K1IO
TKM0C2
M016CTON
D6
M0ST
M0ROEN
M0RCCLR
M016CTCLR
D1
M0ROS
TKM0C3
D7
D6
M0RCOV
M016CTOV
D3
M0ROVS2
M0ROVS1
M0ROVS0
Register Listing
· TKM016DH Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
Touch Key module 0 16-bit counter high byte contents
· TKM016DL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
Touch Key module 0 16-bit counter low byte contents
39
July 19, 2011
HT46R75D-3
· TKM0C0 Register
Bit
7
6
5
4
3
Name
M0MXS1
M0MXS0
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bits 7~6
M0MXS1, M0MXS0: Multiplexer Key Select
00: KEY 1
01: KEY 2
10: KEY 3
11: KEY 4
Bit 5~0
D5~D0: These bits must be set to the binary value ²011000²
2
1
0
· TKM0C1 Register
Bit
Name
7
6
5
4
M0K4OEN M0K3OEN M0K2OEN M0K1OEN
3
2
1
0
M0K4IO
M0K3IO
M0K2IO
M0K1IO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~4
M0KnOEN: Key Selector control (n=1~4)
0: disable
1: enable
Bit 3~0
M0KnIO: Touch Key Function Select (n=1~4)
0: I/O pin
1: KEY n
· TKM0C2 Register
Bit
7
6
5
4
3
2
1
0
Name
M016CTON
D6
M0ST
M0ROEN
M0RCCLR
M016CTCLR
D1
M0ROS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
M016CTON: 16-bit C/F counter control
0: disable
1: enable
Bit 6
D6: This bit must be cleared to zero.
Bit 5
M0ST: Time slot counter start control
0: time slot counter stopped
0 ® 1: enable time slot counter.
When this bit changes from low to high, the time slot counter will be enabled and the touch sense
procedure started. When the time slot counter has completed its counting, an interrupt will be
generated.
Bit 4
M0ROEN: Reference clock control
0: disable
1: enable
Bit 3
M0RCCLR: Time slot counter clear control
0: no change
1: clear counter
This bit must be first set to 1 and then to 0.
Bit 2
M016CTCLR: 16-bit C/F counter clear control
0: no change
1: clear counter
This bit must be first set to 1 and then to 0.
Bit 1
D1: This bit must be cleared to zero.
Bit 0
M0ROS: Time slot counter clock source
0: reference clock
1: KEY 4 sensor oscillator
Rev. 1.00
40
July 19, 2011
HT46R75D-3
· TKM0C3 Register
Bit
7
6
5
4
3
2
Name
D7
D6
M0RCOV
R/W
R
R
POR
0
0
M016CTOV
D3
M0ROVS2
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit 7~6
D7, D6: Read only bits -- unknown values
Bit 5
M0RCOV: Time slot counter overflow flag
0: no overflow
1: overflow
Bit 4
M016CTOV: 16-bit C/F counter overflow flag
0: no overflow
1: overflow
Bit 3
D3: This bit must be cleared to zero.
Bits 2~1
M0ROVS2~M0ROVS0: Time slot counter overflow time setup
000: 64 count
001: 128 count
010: 256 count
011: 512 count
100: 1024 count
101: 2048 count
110: 4096 count
111: 8192 count
Touch Key Operation
1
0
M0ROVS1 M0ROVS0
The time slot counter interrupt has its own interrupt vector while the 16-bit C/F counter interrupts are contained
within the Multi-function interrupts and therefore do not
have their own vector. Care must be taken during programming as the 16-bit C/F counter interrupt flags contained within the Multi-function interrupts will not be
automatically reset upon entry into the interrupt service
routine but rather must be reset manually by the application program. More details regarding the touch key interrupts are located in the interrupt section of the
datasheet.
When a finger touches or is in proximity to a touch pad,
the capacitance of the pad will increase. By using this
capacitance variation to change slightly the frequency of
the internal sense oscillator, touch actions can be
sensed by measuring these frequency changes. Using
an internal programmable divider the reference clock is
used to generate a fixed time period. By counting a
number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can
be determined.
The device contains four touch key inputs which are
shared with logical I/O pins, with the desired function selected using register bits. The Touch Key module also
has its own interrupt vectors and set of interrupts flags.
Programming Considerations
After the relevant registers are setup, the touch key detection process is initiated the changing the M0ST bit
from low to high. This will enable and synchronise all relevant oscillators. The M0RCOV flag, which is the time
slot counter flag will go high and remain high until the
counter overflows. When this happens an interrupt signal will be generated.
During this reference clock fixed interval, the number of
clock cycles generated by the sense oscillator is measured, and it is this value that is used to determine if a
touch action has been made or not. At the end of the
fixed reference clock time interval, a Touch Key interrupt
signal will be generated.
When the external touch key size and layout are defined, their related capacitances will then determine the
sensor oscillator frequency.
Touch Key Interrupt
The touch key module, which consists of four touch
keys, has the corresponding interrupts, one for each of
the 16-bit C/F counter and time slot counter.
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Touch Key (1 Set = Touch Key*4)
Key0
Key1
C/F &
Mux.
Key2
16-bit C/F
Counter
16-bit C/F Counter INT Flag
16-bit C/F Counter Overflow Flag
Enable
Key3
Time Slot
Counter
Mux.
Reference Clock
Time Slot Counter INT flag
Time Slot Counter Overflow flag
Time Slot Counter
Clock Select
Touch Switch Module Block Diagram
M 0 K 4 IO
I/O
E x te r n a l P in
o r T o u c h K e y
T o u c h C ir c u its
L o g ic I/O c ir c u its
M 0 K 3 IO
I/O
T o u c h C ir c u its
L o g ic I/O c ir c u its
b it
E x te r n a l P in
o r T o u c h K e y
T o u c h C ir c u its
L o g ic I/O c ir c u its
M 0 K 1 IO
I/O
b it
E x te r n a l P in
o r T o u c h K e y
M 0 K 2 IO
I/O
b it
E x te r n a l P in
o r T o u c h K e y
b it
T o u c h C ir c u its
L o g ic I/O c ir c u its
Touch Key or I/O Function Select
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Configuration Options
The following table shows all kinds of options in the micro-controller. All of the options must be defined to ensure proper
system functioning.
No.
Options
Watchdog Options
1
WDT function: enable or disable
2
CLRWDT instruction(s): one or two clear WDT instruction(s)
Oscillator Options
3
System oscillator selection -- fSYS:
High frequency Internal RC oscillator (HIRC)
External RC oscillator (ERC)
External Crystal oscillator (HXT)
4
High frequency Internal RC oscillator (HIRC) frequency selection -- 4MHz, 8MHz or 12MHz
5
System oscillator SST period selection -- 1024 clocks or 2 clocks
6
fS internal clock source: fSYS /4 or LIRC or LXT
LVD/LVR Options
7
LVR Low Voltage Reset function: enable or disabled
8
LVR Voltage select: 2.1V, 3.15V or 4.2V
LCD Options
9
LCD function in power down mode: enabled or disabled
10
R type driving current: 50mA or 100mA
I/O Pin Options
11
I/O pin or RES pin
12
I/O pin or LXT OSC3/OSC4 pin
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Application Circuits
VDD
100KO
0.1uF
COM[7:0]
PC[7:0]/SEG[23:0]
VAB,VC
C1,C2
0.1uF
PA7/RES
LCD
Panel
10KO
0.1uF
OSC
Circuit
OSC
Circuit
Vibration
Sensor
PA0/VIB
VSS
PA1/BZ
PA2/BZ
PB0/TK1
PB1/TK2
PB2/TK3
PB3/TK4
PA6/OSC1
PA5/OSC2
Touch
Key
PA4/OSC3
VOREG
47uF
PA3/OSC4
VOCHP
AI
HT46R75D-3
10uF
VOBGP
PB4/INT
10uF
PB5/TMR0
DOPAP
DOPAN
Weight or Fat
Circuit
CHPC1
DOPAO
10uF
DCHOP
CHPC2
VDD
DSCC
TH/LB
47uF
DSRC
300KO
DSRR
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
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Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine
will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
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SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
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XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
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Package Information
Note that the package information provided here is for consultation purposes only. As this information may be updated
at
re g u l ar
intervals
us e r s
ar e
reminded
to
co n su l t
the
Holtek
w e b si t e
(http://www.holtek.com.tw/english/literature/package.pdf) or the latest version of the package information.
64-pin LQFP (7mm´7mm) Outline Dimensions
C
D
4 8
G
3 3
H
I
3 2
4 9
F
A
B
E
6 4
1 7
K
a
J
1 6
1
Symbol
Rev. 1.00
Dimensions in inch
Min.
Nom.
Max.
A
0.350
¾
0.358
B
0.272
¾
0.280
C
0.350
¾
0.358
D
0.272
¾
0.280
E
¾
0.016
¾
F
0.005
¾
0.009
G
0.053
¾
0.057
H
¾
¾
0.063
I
0.002
¾
0.006
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
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HT46R75D-3
Symbol
A
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
8.90
¾
9.10
B
6.90
¾
7.10
C
8.90
¾
9.10
D
6.90
¾
7.10
E
¾
0.40
¾
F
0.13
¾
0.23
G
1.35
¾
1.45
H
¾
¾
1.60
I
0.05
¾
0.15
J
0.45
¾
0.75
K
0.09
¾
0.20
a
0°
¾
7°
59
July 19, 2011
HT46R75D-3
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
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