TI CD54AC283

CD54/74AC283,
CD54/74ACT283
Data sheet acquired from Harris Semiconductor
SCHS251D
4-Bit Binary Fill Adder With Fast Carry
August 1998 - Revised May 2000
Features
Description
• Buffered Inputs
The ’AC283 and ’ACT283 4-bit binary adders with fast carry
that utilize Advanced CMOS Logic technology. These
devices add two 4-bit binary numbers and generate a carryout bit if the sum exceeds 15.
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
Because of the symmetry of the add function, this device
can be used with either all active-HIGH operands (positive
logic) or with all active-LOW operands (negative logic).
When using positive logic, the carry-in input must be tied
LOW if there is no carry-in.
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
Ordering Information
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
PART
NUMBER
TEMP.
RANGE (oC)
CD54AC283F3A
PACKAGE
-55 to 125
16 Ld CERDIP
CD74AC283E
0 to 70oC, -40 to 85,
-55 to 125
16 Ld PDIP
CD74AC283M
0 to 70oC, -40 to 85,
-55 to 125
16 Ld SOIC
CD54ACT283F3A
-55 to 125
16 Ld CERDIP
0 to 70oC, -40 to 85,
CD74ACT283E
16 Ld PDIP
-55 to 125
0 to 70oC, -40 to 85,
-55 to 125
CD74ACT283M
16 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office or
customer service for ordering information.
Pinout
Functional Diagram
CD54AC283, CD54ACT283
(CERDIP)
CD74AC283, CD74ACT283
(PDIP, SOIC)
TOP VIEW
S1 1
16 VCC
B1 2
15 B2
A1 3
14 A2
S0 4
13 S2
A0 5
12 A3
B0 6
11 B3
CIN 7
10 S3
GND 8
A0
B0
A1
B1
A2
B2
A3
B3
CIN
9 COUT
5
S0
6
3
1
1
S1
2
14
13
S2
15
12
10
S3
11
7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © 2000, Texas Instruments Incorporated
4
9
COUT
GND = 8
VCC = 16
CD54/74AC283, CD54/74ACT283
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Thermal Impedance (Typical, Note 5)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. The package thermal impedance is calculated in accordance with JESD 51.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VIH
-
-
1.5
1.2
-
1.2
-
1.2
-
V
3
2.1
-
2.1
-
2.1
-
V
5.5
3.85
-
3.85
-
3.85
-
V
1.5
-
0.3
-
0.3
-
0.3
V
AC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VIL
VOH
-
VIH or VIL
-
-0.05
3
-
0.9
-
0.9
-
0.9
V
5.5
-
1.65
-
1.65
-
1.65
V
1.5
1.4
-
1.4
-
1.4
-
V
-0.05
3
2.9
-
2.9
-
2.9
-
V
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-4
3
2.58
-
2.48
-
2.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
2
CD54/74AC283, CD54/74ACT283
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Low Level Output Voltage
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VOL
VIH or VIL
0.05
1.5
-
0.1
-
0.1
-
0.1
V
0.05
3
-
0.1
-
0.1
-
0.1
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
12
3
-
0.36
-
0.44
-
0.5
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
High Level Input Voltage
VIH
-
-
4.5 to
5.5
2
-
2
-
2
-
V
Low Level Input Voltage
VIL
-
-
4.5 to
5.5
-
0.8
-
0.8
-
0.8
V
High Level Output Voltage
VOH
VIH or VIL
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
Input Leakage Current
Quiescent Supply Current
MSI
ACT TYPES
Low Level Output Voltage
Input Leakage Current
Quiescent Supply Current
MSI
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
VOL
VIH or VIL
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
2.4
-
2.8
-
3
mA
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.
ACT Input Load Table
INPUT
UNIT LOAD
A0, B0, A2, B2
1.66
A1, B1
1.9
A3, B3
1.4
CIN
1.1
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
3
CD54/74AC283, CD54/74ACT283
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPLH, tPHL
1.5
-
-
199
-
-
219
ns
3.3
(Note 9)
6.3
-
22.4
6.2
-
24.6
ns
5
(Note 10)
4.5
-
16
4.4
-
17.6
ns
1.5
-
-
207
-
-
228
ns
3.3
6.6
-
23.2
6.4
-
25.5
ns
5
4.7
-
16.5
4.6
-
18.2
ns
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
120
-
-
120
-
pF
Propagation Delay,
An or Bn to COUT
CIN to Sn
CIN to COUT
tPLH, tPHL
5
(Note 10)
4.5
-
16
2.7
-
17.6
ns
Propagation Delay,
An or Bn to Sn
tPLH, tPHL
5
4.7
-
16.5
3.3
-
18.2
ns
Input Capacitance
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
120
-
-
120
-
pF
PARAMETER
AC TYPES
Propagation Delay,
An or Bn to COUT
CIN to Sn
CIN to COUT
Propagation Delay,
An or Bn to Sn
tPLH, tPHL
Input Capacitance
Power Dissipation Capacitance
ACT TYPES
Power Dissipation Capacitance
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. CPD is used to determine the dynamic power consumption per function.
AC: PD = VCC2 fi (CPD + CL)
ACT: PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
tr ≤ 3ns
tf ≤ 3ns
OUTPUT
INPUT LEVEL
90%
INPUT
RL (NOTE)
500Ω
VS
DUT
10%
OUTPUT
LOAD
GND
CL
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
INVERTING
OUTPUT
tPHL
VS
AC
ACT
VCC
3V
Input Switching Voltage, VS
0.5 VCC
1.5V
Output Switching Voltage, VS
0.5 VCC
0.5 VCC
Input Level
tPLH
FIGURE 2. PROPAGATION DELAY TIMES
FIGURE 1. PROPAGATION DELAY TIMES
4
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