ICS525-03 PECL Input OSCaR™ User Configurable Clock Description Features The ICS525-03 are the most flexible way to generate a high-quality, high-accuracy, high-frequency clock output from a PECL input. The name OSCaR stands for OSCillator Replacement, as they are designed to replace crystal oscillators in almost any electronic system. The user can configure the device to produce nearly any output frequency from any input frequency by grounding or floating the select pins. Neither microcontroller, software, nor device programmer are needed to set the frequency. Using Phase-Locked Loop (PLL) techniques, the device accepts a PECL clock to produce output clocks up to 250 MHz, keeping them frequency locked together. Resistors are for PECL outputs only. • Packaged as 28-pin SSOP (150 mil body) • Highly accurate frequency generation • User determines the output frequency by setting all • • • • • • • • • • • • For simple multipliers to produce common frequencies, refer to the LOCOTM family of parts, which are smaller and more cost effective. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. internal dividers Eliminates need for custom oscillators No software needed Pull-ups on all select inputs PECL input clock frequency of 0.5 to 250 MHz Output clock frequencies up to 250 MHz Very low jitter Operating voltage of 3.0 V or 5.5 V 25 mA drive capability at TTL levels Ideal for oscillator replacement Industrial temperature Available in Pb (lead) free package Advanced, low-power CMOS process Block Diagram 2 VDD VDD 62 Ohm CLK1 PECLIN PECLIN Phase Comparator, Charge Pump, and Loop Filter Reference Divider 270 Ohm Output Divider VCO VDD VCO Divider 62 Ohm CLK2 2 7 R6:R0 GND 3 S2:S0 270 Ohm RES 1 MDS 525-03 H Integrated Circuit Systems, Inc. 9 V8:V0 ● 525 Race Street, San Jose, CA 95126 Revision 010906 ● tel (408) 297-1201 ● www.icst.com ICS525-03 PECL Input OSCaR™ User Configurable Clock Pin Assignment RES Value Table 28 R4 RES CLK1 CLK2 Pre-divide (P) 2 27 R3 0 CMOS CMOS 2 3 26 R2 S1 4 25 R1 1.1 kΩ Resistor to VDD PECL PECL 1 R5 1 R6 S0 S2 5 24 R0 VDD 6 23 VDD PECL 7 22 CLK2 PECLIN 8 21 CLK1 GND 9 20 GND V0 10 19 RES V1 11 18 V8 V2 12 17 V7 V3 13 16 V6 V4 14 15 V5 28-pin SSOP Output Divider and Maximum Output Frequency Table S0 S1 S2 CLK Max. Output Frequency (MHz) pin 5 pin 4 pin 3 Output Divider (OD) VDD = 5 V VDD = 3.3 V RES = 0 RES = 1.1 kΩ RES = 0 RES = 1.1 kΩ 0 0 0 6 67 34 40 20 0 0 1 2 200 100 120 60 0 1 0 8 50 25 30 15 0 1 1 4 100 50 60 30 1 0 0 5 80 40 48 24 1 0 1 7 57 29 34 17 1 1 0 1 250 200 200 125 1 1 1 3 133 80 80 40 Note: 0 = connect directly to ground; 1 = connect directly to VDD. 2 MDS 525-03 H Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 010906 ● tel (408) 297-1201 ● www.icst.com ICS525-03 PECL Input OSCaR™ User Configurable Clock Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1, 2, 24-28 R5, R6, R0-R4 I(PU) Reference divider word input pins determined by user. Forms a binary number from 0 to 127. 3, 4, 5 S0, S1, S2 I(PU) Select pins for output divider determined by user. See table above. 6, 23 VDD Power Connect to VDD. 7 PECLIN Input PECL input. 8 PECLIN Input Complementary PECL input. 9, 20 GND Power Connect to ground. 10 - 18 V0 - V8 I(PU) VCO divider word input pins determined by user. Forms a binary number from 0 to 511. 19 RES Input Select eithe PECL or CMOS outputs. See table above. 21 CLK1 Output Output clock. Either PECL or CMOS determined by RES. 22 CLK2 Output Output clock. Either PECL or CMOS determined by RES. KEY: I(PU) = Input with internal pull-up resistor. Output Clock Selection If RES is connected directly to ground, CLK1 and CLK2 are low skew, CMOS outputs clocks. They are not complementary. If RES is connected to VDD through a 1.1 kΩ resistor, then CLK1 and CLK2 become complementary PECL outputs which require the external resistor network shown in the the block diagram. Refer to Application Note MAN09 for additional information. 3 MDS 525-03 H Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 010906 ● tel (408) 297-1201 ● www.icst.com ICS525-03 PECL Input OSCaR™ User Configurable Clock External Components/Crystal Selection Also, the following operating ranges should be observed: 10 MHz < Input frequency x P x (VDW+8) <350 MHz at 5.0 V or (RDW+2) <250 MHz at 3.3 V Decoupling Capacitors The ICS525-03 requries two 0.01µF decoupling capacitors to be connected between VDD and GND, one on each side of the chip. The capacitor must be connected close to the device to minimize lead inductance. No external power supply filtering is required for this device. External Resistors If PECL outputs are desired, RES should be tied to VDD with a 1.1 kΩ resistor. Each output needs a resistive network of 62Ω and 270Ω per the block diagram on page 1. Application note MAN09 gives more information about resistor selection. Determining (setting) the Output Frequency Users have full control in setting the desired output frequency over the range shown in the table on page 2. To replace a standard oscillator, users should connect the divider select input pins directly to ground (or VDD, although this is not required because of internal pull-ups) during Printed Circuit Board layout. The ICS525-03 will automatically produce the correct clock when all components are soldered. It is also possible to connect the inputs to parallel I/O ports to switch frequencies. By choosing divides carefully, the number of inputs which need to be changed can be minimized. Observe the restrictions on allowed values of VDW and RDW. 200 kHz < Input Frequency (RDW+2) (See table on page 2 for full details of maximum output) The dividers are expressed as integers, so that if a 66.66 MHz PECL output is desired from a 14.31818 PECL input, the Reference Divider Word (RDW) should be 59 and the VCO Divider Word (VDW) should be 276, with an Output Divider (OD) of 1. To select PECL outputs, the RES pin should be tied to VDD with a 1.1kΩ resistor. In this example, R6:R0 is 100010100, and S2:S0 is 110. Since all of these inputs have pull-up reistors, it is only necessary to ground the zero pins, namely V7, V6, V5, V3, V1, V0, R6, R2 and S0. To determine the best combination of VCO, reference, and output divide, use the ICS525 Calculator on our web site: www.icst.com/products/ics525inputForm.html. The online form is easy to use and quickly shows you up to three options for these settings. Alternately, you may send an e-mail to [email protected]. The output of the ICS525-03 can be determined by the following simple equation: ( VDW + 8 ) ( RDW + 2 ) • OD CLK Frequency = Input Frequency × P x --------------------------------------------- Where: Reference Divider Word (RDW) = 0 to 127 VCO Divider Word (VDW) = 0 to 511 Output Divider (OD) = values on page 2 Pre-divide (P) = values on page 2 under RES Value Table 4 MDS 525-03 H Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 010906 ● tel (408) 297-1201 ● www.icst.com ICS525-03 PECL Input OSCaR™ User Configurable Clock Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS525-03. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature, Industrial -40 to +85°C Storage Temperature -65°C to 150°C Junction Temperature 125°C Soldering Temperature 260°C (max. of 10 seconds) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V Parameter Symbol Conditions Min. Typ. Max. Units 5.5 V Operating Voltage VDD 3.0 Operating Supply Current IDD 60 MHz out, no load 15 mA Operating Supply Current, LVPECL mode IDD With termination resistors 35 mA Input High Voltage VIH Input Low Voltage VIL 2 V 0.8 V V Peak-to-peak Input Voltage PECLIN, PECLIN 0.3 1 Common Mode Range PECLIN, PECLIN VDD-1.4 VDD-0.6 Output High Voltage VOH IOH = -25 mA, CMOS out Output Low Voltage VOL IOL = 25 mA, CMOS out Short Circuit Current 2.4 V 0.4 CMOS out V ±70 mA Input Capacitance CIN V, R, S select pins 4 pF On-chip Pull-up Resistor RPU V, R, S select pins 270 kΩ 5 MDS 525-03 H Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 010906 ● tel (408) 297-1201 ● www.icst.com ICS525-03 PECL Input OSCaR™ User Configurable Clock AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V Parameter Symbol Input Frequency Conditions FIN Min. Clock input Typ. Max. Units 0.5 250 MHz Output Frequency, VDD=4.5 to 5V FOUT OD = 1 1 250 MHz Output Frequency, VDD=3.0 to 3.6 V FOUT OD = 1 1 200 MHz Output Clock Rise Time, CMOS clock 0.8 to 2.0 V 1 ns Output Clock Fall Time, CMOS clock 2.0 to 0.8 V 1 ns Output Clock Duty Cycle, even output dividers at VDD/2 45 55 % Output Clock Duty Cycle, odd output dividers at VDD/2 40 60 % Absolute Clock Period Jitter tja Deviation from mean ±350 ps One Sigma Clock Period Jitter tjs One Sigma 125 ps 6 MDS 525-03 H Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 010906 ● tel (408) 297-1201 ● www.icst.com ICS525-03 PECL Input OSCaR™ User Configurable Clock Package Outline and Package Dimensions (28-pin SSOP, 150 mil Body) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 28 Millimeters Symbol E1 E INDEX AREA 1 2 D A 2 Min A A1 A2 b C D E E1 e L α aaa A Inches Max Min 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 9.80 10.00 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0° 8° -0.10 Max .053 .069 .0040 .010 -.059 .008 .012 .007 .010 .386 .394 .228 .244 .150 .157 0.025 Basic .016 .050 0° 8° -0.004 A 1 c -Ce SEATING PLANE b L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS525R-03I ICS525R-03I Tubes 28-pin SSOP -40 to +85°C ICS525R-03IT ICS525R-03I Tape and Reel 28-pin SSOP -40 to +85°C ICS525R-03ILF ICS525R-03ILF Tubes 28-pin SSOP -40 to +85°C ICS525R-03ILFT ICS525R-03ILF Tape and Reel 28-pin SSOP -40 to +85°C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments 7 MDS 525-03 H Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 010906 ● tel (408) 297-1201 ● www.icst.com