ICS ICS601-25

ICS601-25
LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER
Description
Features
The ICS601-25 is a low-cost, low phase noise, high
performance clock synthesizer for applications which
require low phase noise, low jitter, and low skew fanout.
It is ICS’ lowest phase noise multiplier, and also the
lowest CMOS part in the industry. Using ICS’ patented
analong and digital Phase Locked Loop (PLL)
techniques, the chip accepts a 10-27 MHz crystal or
clock input, and produces output clocks up to 156 MHz.
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Packaged in 20-pin SSOP
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Powerdown mode lowers power consumption
Uses fundamental 10 - 27 MHz crystal or clock
Output clocks up to 156 MHz
Low phase noise: -132 dBc/Hz at 10 kHz
Five low skew (<250 ps) outputs
Low jitter - 18 ps one sigma at 125 MHz
Full swing CMOS outputs with 25 mA drive capability
at TTL levels
Advanced, low power, sub-micron CMOS process
Industrial temperature version available
Available in Pb (lead) free package
Operating voltage of 3.3 V
Block Diagram
VDD
5
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLK1
CLK2
CLK3
X1/ICLK
Crystal or
clock input
VCO
Divide
Crystal
Oscillator
CLK4
X2
CLK5
ROM Based
Multipliers
4
S3:0
GND
PD
1
MDS 601-25 C
I n t e gra te d C i r c u i t S y s t e m s
3
●
525 Race Stre et, San Jo se, CA 9 5126
Revision 071505
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te l (40 8) 2 97-12 01
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w w w. i c st . c o m
ICS601-25
LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER
Pin Assignment
Output Select Table
X1/ICLK
1
20
X2
VDD
2
19
GND
S0
3
18
VDD
VDD
4
17
CLK2
VDD
5
16
CLK3
S1
6
15
GND
GND
7
14
CLK4
S3
8
13
CLK5
PD
9
12
VDD
S2
10
11
CLK1
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
20 Pin (150 mil) SSOP
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Multiplier
x1
x2
x3
x4
x5
x6
x8
x16
x7
x9
x10
x11
x12
output tristates
x14
x15
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
X1/ICLK
XI
2
VDD
Power
Pin Description
Crystal or clock input. Connect to a 10-27 MHz fundamental parallel mode
crystal or clock input.
Connect to +3.3 V.
3
S0
Input
Select pin 0. Internal pull-up.
4, 5
VDD
Power
Connect to +3.3 V.
6
S1
Input
Select pin 1. Internal pull-up.
7
GND
Power
Connect to ground.
8
S3
Input
Select pin 3. Internal pull-down.
9
PD
Input
Powerdown when held low. Internal pull-up.
Select pin 2. Internal pull-up.
10
S2
Input
11
CLK1
Output
Clock output.
12
VDD
Power
Connect to +3.3 V.
13
CLK5
Output
Clock output.
14
CLK4
Output
Clock output.
15
GND
Power
Connect to ground.
16
CLK3
Output
Clock output.
17
CLK2
Output
Clock output.
18
VDD
Power
Connect to +3.3 V.
19
GND
Power
Connect to ground.
20
X2
XO
2
MDS 601-25 C
In te grated Circuit Systems
Crystal connection. Connect to a 10-27 MHz fundamental parallel mode
crystal or leave unconnected for clock input.
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 071505
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS601-25
LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER
External Components
The ICS601-25 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01 µF and 0.1 µF should be connected between VDD and GND, as close to the part as
possible. A 33Ω series terminating resistor should be used on each clock output. The crystal must be
connected as close to the chip as possible. The crystal should be fundamental mode, parallel resonant. Do
not use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1
to ground and X2 to ground. In general, the value of these capacitors is given by the following equation,
where CL is the crystal load capacitance: Crystal caps (pF) = (CL-5) x 2. So for a crystal with 16 pF load
capacitance, two 22 pF caps can be used. For any given board layout, ICS can measure the board
capacitance and recommend the exact capacitance value to use.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS601-25. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature, Commercial version
0 to +70 °C
Ambient Operating Temperature, Industrial version
-40 to +85 °C
Storage Temperature
-65 to +150 °C
Junction Temperature
125 °C
Soldering Temperature
260 °C
Recommended Operation Conditions
Parameter
Min.
Max.
Units
0
+70
°C
-40
+85
°C
+2.97
+3.63
V
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
Typ.
DC Electrical Characteristics
VDD=3.3 V ±10%, Ambient temperature -40 to +85°C
Parameter
Symbol
Conditions
Operating Voltage
VDD
Input High Voltage
VIH
X1/ICLK pin only
Input Low Voltage
VIL
X1/ICLK pin only
Typ.
2.97
●
525 Ra ce Street, San Jose, CA 9512 6
Max.
Units
3.63
V
VDD/2+1
V
VDD/2-1
3
MDS 601-25 C
In te grated Circuit Systems
Min.
V
Revision 071505
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tel (4 08) 297-1 201
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w w w. i c s t . c o m
ICS601-25
LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER
DC Electrical Characteristics (continued)
Parameter
Symbol
Conditions
Min.
Typ.
Units
VDD
V
0.8
V
Input High Voltage
VIH
Input Low Voltage
VIL
Output High Voltage, CMOS
level
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOL = -12 mA
2.4
V
Output Low Voltage
VOL
IOL = 12 mA
Operating Supply Current
IDD
No load, 125 MHz
Short Circuit Current
IOS
Each output
Input Capacitance
2
Max.
45
± 40
0.4
V
60
mA
± 60
mA
5
pF
20
Ω
Select pins
Output Impedance
ZOUT
On Chip Pull-up Resistor
RPU
S2, S1, S0, PD
pins
510
kΩ
On Chip Pull-down Resistor
RPD
S3 pin
240
kΩ
AC Electrical Characteristics
VDD = 3.3V ±10%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Input Frequency
Min.
Typ.
10
Output Frequency
Max. Units
27
MHz
At 3.3V
156
MHz
Output Rise Time
tOR
0.8 to 2.0 V, Note 1
1.5
ns
Output Fall Time
tOF
0.8 to 2.0 V, Note 1
1.5
ns
50
55
%
Output Clock Duty Cycle
At VDD/2, Note 1
45
Maximum Absolute jitter, short
term, 125 MHz
Note 1
±50
±75
ps
Maximum jitter, one sigma, 125
MHz (x5)
Note 1
18
25
ps
Phase Noise, relative to carrier,
125 MHz (x5)
100 Hz offset
-90
-95
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
1 kHz
-115
-120
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
10 kHz offset
-118
-123
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
100 kHz offset
-115
-120
dBc/Hz
Output to Output Skew
25M in, 125M out,
Note 1
250
ps
Note 1: Measured with 15 pF load
4
MDS 601-25 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 071505
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS601-25
LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches*
20
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
E
INDEX
AREA
1 2
D
A
A2
Min
Max
Min
1.35
1.75
0.10
0.25
-1.50
0.20
0.30
0.18
0.25
8.55
8.75
5.80
6.20
3.80
4.00
0.635 Basic
0.40
1.27
0°
8°
-0.10
Max
.0532
.0688
.0040 0.0098
-.059
0.008
0.012
.007
.010
.337
.344
.228
.244
.1497
.1574
0.025 Basic
.016
.050
0°
8°
-0.004
*For reference only. Controlling dimensions in mm.
A1
c
-Ce
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS601R-25
ICS601R-25
Tubes
20-pin SSOP
0 to +70° C
ICS601R-25T
ICS601R-25
Tape and Reel
20-pin SSOP
0 to +70° C
ICS601R-25I
ICS601R-25I
Tubes
20-pin SSOP
-40 to 85° C
ICS601R-25IT
ICS601R-25I
Tape and Reel
20-pin SSOP
-40 to 85° C
ICS601R-25LF
601R-25LF
Tubes
20-pin SSOP
0 to +70° C
ICS601R-25LFT
601R-25LF
Tape and Reel
20-pin SSOP
0 to +70° C
ICS601R-25ILF
601R-25ILF
Tubes
20-pin SSOP
-40 to 85° C
ICS601R-25ILFT
601R-25ILF
Tape and Reel
20-pin SSOP
-40 to 85° C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those
requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant
any ICS product for use in life support devices or critical medical instruments.
5
MDS 601-25 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 071505
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m