PRELIMINARY Integrated Circuit Systems, Inc. ICS844011I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS844011I is a Fibre Channel Clock Generator and a member of the HiPerClocksTM HiPerClockS™ family of high performance devices from ICS. The ICS844011I uses an 18pF parallel resonant crystal over the range of 20.4MHz - 28.3MHz. For Fibre Channel applications, a 26.5625MHz crystal is used. The ICS844011I has excellent <1ps phase jitter performance, over the 637kHz - 10MHz integration range. The ICS844011I is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • (1) Differential LVDS output ICS • Crystal oscillator interface, 18pF parallel resonant crystal (20.4MHz - 28.3MHz) • Output frequency range: 81.66MHz - 113.33MHz • VCO range: 490MHz - 680MHz • RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.75ps (typical) • 3.3V or 2.5V operating supply • -40°C to 85°C ambient operating temperature COMMON CONFIGURATION TABLE - FIBRE CHANNEL Inputs Crystal Frequency (MHz) M N 26.5625 24 6 Multiplication Value M/N 4 25 24 6 4 Output Frequency (MHz) 106.25 100 BLOCK DIAGRAM PIN ASSIGNMENT OE Pullup XTAL_IN OSC XTAL_OUT Phase Detector VCO 490MHz - 680MHz N = ÷6 (fixed) Q nQ VDDA GND XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q nQ OE ICS844011I 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View M = ÷24 (fixed) The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 844011AGI www.icst.com/products/hiperclocks.html REV. A JUNE 28, 2005 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS844011I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDA Power Analog supply pin. 2 GND XTAL_OUT, XTAL_IN Power 5 OE Input 6, 7 nQ, Q Output Power supply ground. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Output enable pin. When HIGH, Q/nQ output is active. When LOW, the Q/nQ output is in a high impedance state. LVCMOS/LVTTL interface levels. Differential clock outputs. LVDS interface levels. 8 VDD Power Core supply pin. 3, 4 Type Description Input Pullup NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ 844011AGI Test Conditions www.icst.com/products/hiperclocks.html 2 Minimum Typical Maximum Units REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844011I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 3.465 VDDA Analog Supply Voltage IDD Power Supply Current TBD mA IDDA Analog Supply Current TBD mA V TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 2.375 2.5 2.625 V 2.375 2.5 2.625 VDDA Analog Supply Voltage IDD Power Supply Current TBD mA V IDDA Analog Supply Current TBD mA TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol VIH Parameter Input High Voltage Test Conditions Minimum Maximum Units VDD = 3.3V 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V 5 µA VIL Input Low Voltage IIH Input High Current OE VDD = VIN = 3.465V or 2.625V IIL Input Low Current OE VDD = 3.465V or 2.625V, VIN = 0V 844011AGI Typical www.icst.com/products/hiperclocks.html 3 -150 µA REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844011I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 350 mV Δ VOD VOD Magnitude Change 40 mV VOS Offset Voltage 1.25 V Δ VOS VOS Magnitude Change 50 mV NOTE: Please refer to Parameter Measurement Information for output information. TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 350 mV Δ VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.2 V Δ VOS VOS Magnitude Change 40 mV NOTE: Please refer to Parameter Measurement Information for output information. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units 28.3 MHz Fundamental Frequency 20.4 Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units 113.33 MHz TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) t R / tF RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time Test Conditions Minimum Typical 81.66 106.25MHz @ Integration Range: 637kHz - 10MHz 100MHz @ Integration Range: 637kHz - 10MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section. TBD ps 0.75 ps 275 ps 50 % TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter ( Random); NOTE 1 t R / tF Output Rise/Fall Time Test Conditions Typical 81.66 106.25MHz @ Integration Range: 637kHz - 10MHz 100MHz @ Integration Range: 637kHz - 10MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section. 844011AGI Minimum www.icst.com/products/hiperclocks.html 4 Maximum Units 113.33 MHz TBD ps 0.93 ps 295 ps 50 % REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844011I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION SCOPE Qx 3.3V±5% POWER SUPPLY Qx 2.5V±5% POWER SUPPLY LVDS + Float GND - + Float GND - SCOPE LVDS nQx nQx LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot Noise Power nQ Q t PW t Phase Noise Mask odc = f1 Offset Frequency PERIOD t PW x 100% t PERIOD f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VVDD DD out 80% DC Input VSW I N G Clock Outputs LVDS ➤ 80% 20% 20% tR out tF ➤ VOS/Δ VOS ➤ OFFSET VOLTAGE SETUP OUTPUT RISE/FALL TIME VDD V DD LVDS 100 ➤ VOD/Δ VOD out ➤ DC Input ➤ out DIFFERENTIAL OUTPUT VOLTAGE SETUP 844011AGI www.icst.com/products/hiperclocks.html 5 REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844011I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844011I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. 3.3V or 2.5V VDD .01μF 10 Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS844011I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 26.5625MHz, 18pF par- allel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p Figure 2. CRYSTAL INPUt INTERFACE 844011AGI www.icst.com/products/hiperclocks.html 6 REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844011I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR 3.3V, 2.5V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 2.5V or 3.3V VDD LVDS_Driv er + R1 100 - 100 Ohm Differential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION 844011AGI www.icst.com/products/hiperclocks.html 7 REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844011I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS844011I is: 2533 844011AGI www.icst.com/products/hiperclocks.html 8 REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS844011I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR 8 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 844011AGI www.icst.com/products/hiperclocks.html 9 REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844011I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS844011AGI 4011A 8 lead TSSOP tube -40°C to 85°C ICS844011AGIT 4011A 8 lead TSSOP 2500 tape & reel -40°C to 85°C The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844011AGI www.icst.com/products/hiperclocks.html 10 REV. A JUNE 28, 2005