INF8582E
256 Х 8 BIT STATIC CMOS EEPROM WITH I2С-BUS.
( ANALOG - MICROCIRCUIT PCF8582Е, F.PHILIPS).
INF8582E - 2Кbit (256х8 bit) electronically erasable programmable ROM with
“floating” gate. Internal reduntant code correcting errors as single bit errors is used to
enhance the reliability. Microcircuit operates in systems with serial I2C-bus consisting of
two lines: for data signals (SDA) (bidirectional) and for clock signals (SCL). Up to 8 microcircuits may be connected to I2C-bus. Stacker programming is done by tunneling
electrons. Programming voltage is generated by voltage multiplier built-in chip. The implementation of CMOS technology in full provides low power consumption.
These products are purposed for implementation in portable consumer applications, in autoelectronics, in peripheric computer devices. Thea are used in TV channel selectors, for storage of frequency, volume and image data, in tuning control blocks
in radioset,
, in measuring devices for standard curves storage, calibration data,
minimum and maximum values, in
, seat position adgusting systems, side glass, in
speedometers.
Characteristic properties:
- without decay storage 2 Кbit 10 years;
- single-error correction circuit;
- one power supply (Uсс=4,5V - 5,5V);
- built-in voltage multiplier in chip;
- input/output consecutive bus ;
- automatic increment of word address;
- internal timer for recording;
- 100 000 cycles erasure/recording on byte with low failure rate;
- unlimited number of reading cycles;
- low power consumption;
- temperature range -40 - +85 ОС.
The basing circuit diagram and Pins purpose table are given below in fig.1, main
electrical characteristics are indicated in Table 1.
Microcircuit basing diagram
А
Ucc
А
12
87
А
3
6
SCL
Uss
4
5
SDA
Package: 2101.8-A
TEST
Pins purpose table
Pin №
1
2
3
4
5
6
7
8
Рис.1
1
Symbol
A0
A1
A2
Uss
SDA
SCL
ТЕSТ
Ucc
Purpose
address input
address input
address input
"ground"
data line, input/output
clock signal line (input)
synchronizing signal of programming
power supply
INF8582E
BLOCK DIAGRAM
PTC
SCL(6)
SDA(5)
INPUT
FILTER
ADDRESS
SWITCH
I2C-BUS
CONTROL
LOGIC
ADDRESS
HIGH
REGISTER
SHIFT
REGISTER
DDRESS
HIGH
REGISTER 1
TIMER
BYTE
LATCH
DIVIDER
(/128)
INTERNAL BUS
A0(1)
A1(2)
A2(3)
TEST MODE
DECODER
ADDRESS
POINTER
EEPROM
GND(4)
2
TEST MODE
DECODER 1
POWER-ON
RESET
(7)
INF8582E
Table 1 - Main characteristics of microcircuits
Parameters
Dynamic consumption current (reading), mA
Dynamic consumption current(erasure/recording),
mА
Supply voltage, V
Static consumption current, µА
Clock frequency, кHz
Max output current, mА
Duration of " erasure/recording " cycle, ms:
- input external control TEST
- inside chip control
Mode
fSCL=100кHz
UCC=5.5V
fSCL=100кHz
UCC=5.5V
UCC=5,5V
Symbol
ICC0(RD)
Min
-
Max
1,6
ICC0(E/WR)
-
2,5
VDD
ICCS
fSCL
IОL
tE/WR
4.5
0
5.5
10,0
100
3.0
5
25
10 ÷ 13 (standard)
Input ТЕSТ
High level input voltage, V
Low level input voltage, V
UIH
UIL
0,9UCC
-0,8
UCC+0,8
0,1UCC
InputsSCL and SDA
High level input voltage, V
Low level input voltage, V
UIH
UIL
0,7UCC
-0,8
UCC+0,8
0,3UCC
UOL
-
0,4
Output SDA
Low level output voltage, V
IOL=3,0 mA
UCC=4,5 V
In order to make the understanding of the microcircuit INF8582E way of operation easier it
is necessary to examine I2C-bus interface characteristics.
I2C-bus is a bidirectional double-wire serial bus purposed for data exchange between different (various) integrated circuits. It consists of date line (SDA) and clock signals line (SCL). In
common case the both lines should be connected to the positive power supply by charging resistor (output stage with open drain/collector). As for the designed product, only SDA line (input/output) is bidirectional therefore charging resistor on SCL line is not necessary. Resistor
nominal value is limited at the bottom - by load capability of microcircuit (IOL=3,0 mA), at the
top - by the build-up font duration (tR=1,0 µs). Operation of the microcurcuit is stable within the
resistance range from 1,5 kOhm up to 10 kOhm. The possible operation modes of I2C-bus are
showed in figure 2.
Operation modes of I2С-bus
ST
Input
Input
Output
Input
SP
SDA
SCL
bus is
free
1
8
9
condition
Data transmission with acknowledgment bit
"start",
start of
ransmission
Fig. 2
3
condition "stop",
end of transmission
bus
is free
INF8582E
2
The following modes of I С-bus are defined:
- bus is free (not engaged) - both lines are in "high" mode;
- transmission start (condition "Start") - passing of the line SDA from "high" level to
"low" when SCL is in "high" mode;
- data transmission;
- end of transmission (condition "Stop") - passing of the line SDA from "low" level to
"high" while the line SCL is in "high" mode.
The data transmission can start only when the bus is free. During the data transmission
the data line must be stable all the time while clock line is “high”. The SDA line mode can
change only when the clock signals line SCL is in “low” mode. One clock signal falls at one data
bit. The change in SDA line mode when Clock line is “high” will be interpreted as check signals:
“Start” or “Stop”.
Each transmission of data starts with the condition “Start” and is finished with the condition
“Stop”. The information is always transmitted in bytes. The number of data bytes transmitted between the conditions “Start” and “Stop” is limited in “Erasure/recording” mode and not limited in
“Reading” mode. Each word of 8 bits (each byte) is accompanied by the 9th test bit, acknowledgment bit. This bit is always generated on SDA line by the device which received the previous
data byte (i.e. “receiver”). The device acknowledging the receipt of the data (if it meets the requirements), rarefies the SDA line so that this line is constantly “low” during all period of “high”
level of clock acknowledgment pulse (9th bit) on SCL line. The device transmitting the data during acknowledgment forming must take the mode with high output resistance. If the received
data byte does not comply with the requirements, the receiving device does not generate the
acknowledgment which indicates to the error in exchange protocol on I2С-bus.
All devices connected to I2С-bus may be devided in two groups: «main» devices which
control the data transmission along the bus (microcontrollers, microprocessors), and «subordinate» devices, which are controlled by «main» devices (service and peripheric devices). In their
turn the both groupsof devices may be as «receivers» (devices receiving the data at that moment) and «transmitters» (devices transmitting the data the bus). The designed microcircuit
INF8582E may be only «subordinate receiver» or «subordinate transmitter».The time diagram of
I2С-bus is showed in fig.3. Signal parameters of I2С-bus time diagram are given in table 2.
I2С-bus time diagram
SDA
tBUF
tHD, STA
THD.DAT
tR
SCL
TSU.DAT
1
tLOW
TSU.ACK
tHIGH
8
tF
TSU.STA
SDA
Fig. 3
4
THD.ACK
9
TSU.STO
INF8582E
Table 2 Signal parameters on I2С-bus
Parameter name,
unit of the measurement
Time when the bus is free before generation of «start» condition, µs
Condition«start» set up time, µs
Condition «start» retention time, µs
«Low» period of clock signal, µs
«High» period of clock signal, µs
Rise front duration, ns
Fall front duration, ns
Symbol
Notes
tBUF
Value
min
max
4.7
-
TSU. STA
tHD. STA
tLOW
tHIGH
tR
tF
4.7
4.0
4.5
4.0
-
1
Data retention time,ns
Data retention time, µs
Data set up time, ns
tHD. DAT
tHD. DAT
tSU. DAT
Acknowledgment generation time, µs
Acknowledgment retention time, µs
Condition «Stop» set up time, µs
tSU. ACK
tHD. ACK
tHD. STO
0
5.0
250.
0
0
4.7
1.0
300.
0
-
2
3
3.5
-
Notes: 1. For repeated start.
2. Microcircuit INF8582E is a "subordinate transmitter".
3.Microcircuit INF8582E is a "subordinate receiver".
Among the parameters stipulated in table 2 the particular attention should be paid to set up
and data retention time. Two modes should be considered.
The first mode.
Первый режим. Microcircuit INF8582E receive data, i.e. is a "subordinate receiver. In this
case time tSU.DAT and tHD.DAT must be garanteed by "main transmitter". "Latchup" of data being received in microcircuit is effected onback front of clock pulse.
The second mode. Microcircuit INF8582E generate a data which goes to the line SDA,
i.e.. is a " subordinate transmitter". In this case time tSU.DAT and tHD.DAT are determined by the microcircuit parameters. True information on the line SDA is set by back front of the previous clock
pulse. In other words, usefull information is already on the leading edge of the next clock pulse
on the line SDA.
The protocols of I2C -bus for all microcircuits operating modes are shown in fig. 4-6, in fig.7
- time diagram of signals on the bus in the mode «erasure/recording» using external master oscillator. The signal parameters in the mode «erasure/recording» are stated in table 3, in tables
4,5 - interpretation of key words and symbols, used for presentation of these protocols.
I2С-bus protocol in the «Reading » mode with input of word address
S
T
CS/WR
A
s
WA
A
s
S
T
CS/R
D
A
s
DA
Am
DA
Am
n bytes
last byte
↑
automatic increment of word being read-out
Fig. 4
I2С-bus short protocol in the mode "Reading"
ST
CS/RD
As
DA
Am
DA
5
Am
SP
SP
INF8582E
n bytes
last byte
↑
automatic increment of the word being read-out
Fig. 5
The particularity of protocols in the mode «Reading» is the change of direction of the data
transfer on SDA line: before the end of the control word CS/RD microcircuit receives the information and afterwards the data transfer (read-out) Once setting the protocol it is possible to
read-out an unlimited number of data bytes sequentially. After each byte is read-out embedded
address counter automatically get an increment of «unit» after having received the acknowledgment from «main receiver» (Аm=0). And so on up to the address 256. When the counter is
overfilled «zero» address is initialized. Straight away after Acknowledgment clock pulse negative front (in case if As or Am=0) microcircuit output is lowimpedence and the first bit of the
read-out information byte is set on SDA line. In case of the transfer by microcircuit («sabordinate
transmitter») of the last byte «main receiver» has to transmit to «sabordinate transmitter» the information about the end of receit (Am=1), not to generate a sygnal conforming the receipt. In this
case after Acknowledgment clock pulse back front output of microcircuit is set in the condition
with high output resistance (is closing ), high level is set on SDA line permitting «main receiver»
to generate the condition «Stop».
Short protocol of the mode “Reading” (without writing the address of word being read-out)
is used if while working with the microcircuit (without turning off supply voltage) the necessity to
continue reading from the last address occured.
I2С-bus short protocol in the mode "erasure/зrecording"
ST
CS/W
R
As
WA
As
DE
As
DE
As
SP
↑
automatic increment of the word being read-out
Fig. 6
The active reprogramming process starts after supply of the whole protocol on generating
condition “Stop”. The presence of the second data byte is not necessary. In one cycle ‘erasure/recording’ no more than two information bytes may be programmed. The programming can
be effected under embedded control (the internal programming master oscillator is used), as well
as using external generator.
If an internal generator is meant to be used, high level must be set on output “TEST" or it
must be let free (inside the chip this output is connected to the bus Uсс through resistor approx.
1,5 кОhm). In this case programming cycle duration depends on the manufacturing process, it
is equal to 10.0 - 15.0 ms when recording one data byte and 20.0 - 25.0 ms - two.
6
INF8582E
When using external master oscillator on output “Test” low level must be set preliminary.
The information on logical state on this particular output is fixed after supplying the 8th bit of the
address byte (along clock sygnal back front). Time diagram is generated on I2С-bus as per
fig.7.
Time diagram of signals in the mode "erasure/recording" of one information byte
when using external generator.
tR
tD
(1)
TEST
tF
tHIGH
tLOW
1
2
257
SDS
SCL
"STOP"
Active programming process, I2C-bus free for interaction with other
devices
1 - in the mode "erasure /recording" two information bytes 513 pulses are applied to the input
«TEST». Programming cycle duration for 1 byte is approximately 5ms, when recording
two bytes - 10 ms.
Fig. 7.
Таблица 3
Parameter name,
measurement unit
Input "ТЕSТ" clock frequency, кHz
Duration of the "high", mks
Duration of the "low", mks
Duration of the rise front, ns
Fall front duration, ns
Delay time, mks
7
Symbol
Min
Max
fP
tHICH
tLOW
tR
tF
tD
10
10
10
0
50
300
300
tLOW
INF8582E
Table 4 - Control words
Word
Word byte No
Purpose
9-th bit (acknowledgment
bit after the
word)
name
CS/W
R
01
1
02
0
03
1
04
0
05
A2
06
A1
07
A0
08
0
word of chip selection for
recording information in m/c
"0", acknowledgment from
m/c
"0", acknowledgment from
m/c
"0", acknowledgment from
m/c
"0", acknowledgment from
m/c
"0" or "1" from
the "main"
CS/RD
1
0
1
0
A2
A1
A0
1
Word of chip selection for
reading data from m/c
WA
X7
X6
X5
X4
X3
X2
X1
X0
word of byte address,
which is addressed to
DE
D7
D6
D5
D4
D3
D2
D1
D0
Data word for recording in
microcircuit EEPROM
DA
D7
D6
D5
D4
D3
D2
D1
D0
Data word read-out from
m/c EEPROM
The word of chip selection consists of several parts.
- bits 1-4 are strictly defined combination, programmed inside chip;
- bits 5-7 (selection bits of device А2-А0) make achievable the connection of 8 memory
devices to the bus. Выбор определенного прибора достигается, если логическое состояние
данного бита соответствует распайке выводов корпуса А2-А0 на плате. Если выводы на
плате не подключены, то в слове выбора кристалла биты 5-7 должны иметь "низкий" логический уровень, так как по включению напряжения питания эти входы внутри кристалла
сбрасываются в "0";
- 8 bit define action ("0" – writing of data to circuit, "1" – reading of data);
Developed circuit play role of “Slave receiver” in work with most cases of control words
and provide confirmation, exception is case of reading of data, when a external device (“Host
receiver”) provide the confirmation .
Table 5 Symbol
ST
SP
As
Am
X0 - X7
D0 - D7
Definition
START
STOP
Confirmation bite from circuit
Confirmation bite from “Host receiver”
Address bits of byte
Data bits
8